Cdma

Digital Design ofDS-CDMA TransmitterUsing VHDL and FPGA

Khalid Eltahir Mohamed, Borhanuddin Mohd. Ali(uofg [email protected], [email protected])

Department of Computer and Communications Systems, Faculty of Engineering, University PutraMalaysia (UPM), 43400 Serdang, Selangor, Malaysia

Abstract- This paper describes the Direct Sequence Code DivisionMultiple Access (DS-CTDMA) wireless transmitter design using FieldProgrammable Gate Array (FPGA), which has been adopted in manywireless access technologies. Four separate blocks have been designedusing digital approach to form the transmitter circuit diagram usingthe oscillator, the PN-code generator, the Parity Check, and the BPSKmodulator. The Synopsys software has been used for the designsynthesis and simulation; the Very High Speed Integrated CircuitHardware Description Language (VHDL) program was used forcoding and FPGA for compiling and downloading the simulaton.The DS-CDMA wireless tansmitter was designed to trnsmit withdata rates up to 2Mbps. Ihe transmitted signals were camed with a40 M:Hz carrer frequency.

Keywords: DS-CDMA, tansmitter, VHDI FPGA, PNgenerator.

I. INTRODUCTION

In recent years, there has been a significant amount of researchperformed in both industry and academia into the developmentof CDMA systems. A clear description of a CDMA has beenelusive, since it has a different meaning to every researcherinvolved in the topic [6].

DS-CDMA is a type of spread-spectrum communicationsystem in which multiple signal channels occupy the samefrequency band, being distinguished by the use of differentspreading codes [2]. CDMA communication is employed in,for example, digital cellular telephone systems and personalcommunication services. In these systems, a base stationcommunicates with a plurality of mobile stations, onefrequency band being used for all of the up-links from themobile stations to the base station, and another frequency bandbeing used for all of the down-links from the base station tothe mobile stations [3].

This paper describes the design and a circuit for pseudorandom PN coding and synchronization of a wirelesstransmitter for DS-CDMA using VHDL software. The circuitfor the transmitter is comprised of basic digital components,

such as flip-flops, oscillators, shift registers, PN coder and aBPSK modulator.

FPGA was selected to implement this circuit. The researghinvolved two phases - simulation and synthesis of the VHDLcodes using the Synopsys package and converting theintegrated circuit of the transmitter in the FPGA compiler fordownloading on the Xilinx FPGA board.

A VHDL design begins with an ENTITY block that describesthe interface for the design. The interface defines the input andoutput logic signals of the circuit. The ARCHITECTUREblock describes the internal operation of the design. Withinthese blocks, there are numerous other functional blocks usedto build the design elements ofthe logic circuit created [8].

The source code written using the normal TEXT editor, thensaved as a VHDL file with '.vhd' extension and transferred toany of the VHDL design compilers (DC). If the compilationshows no error(s), the file can be simulated, synthesized andimplemented with FPGA [9].

The transmitter components were designed individually usingthe bottom-up approach. The designs were then combined anddefined by a component declaration and port mapping.Generally, this is an easy method although it could have hadcomplications.

The basic transmitter circuit used was adopted from thefollowing digital components; flip-flops, shift registers, PNcoder and a BPSK modulator with 40 MHz DIP oscillatorproviding the reference frequency [1].

This paper concentrates on the application of VHDLsimulation tool and FPGA compiler to wireless datacomponents. Networks operating over unlicensed bands haverecently received increased attention with the prominence ofsuch standards as IEEE 802.11 and Bluetooth. In 3G, theinfornation transferred is not limited to having voices, images

1-4244-0000-7/05/$20.00 02005 IEEE. 632

and digital data separately. Users will have full coverage andmobility for 144 kbps (preferably 348 kbps) and eventually upto 2 Mbps. With this wide bandwidth, users are able to accessthe information in full multimedia form, wirelessly and withbetter quality [7].

The next section of this paper describes the PN codegenerator, which is the important part of the design. The thirdsection of this paper presents the transmitter block diagramwith the flow chart of the program. The fourth section presentslanguage options in creating the design and also the simulationand synthesize tool. Section five presents the hardwareimplementation.

lI. PN CODE GENERATOR

The PN generator was used with Linear Feedback ShiftRegisters (LFSRs) to provide and assign synchronization andunique codes to the individual users across the transmissioninterface [4].

The LFSR sequence goes through (2n -1) states, where n is thenumber of registers in the LFSR. The contents of the registersare shifted one position to the right per clock cycle. Thefeedback from predefined registers, or taps to the leftmostregister, are XORed together. Table I presents the mainvariables used in this research.

TABLE IVARIABLES FOR LFSR DESIGN

Variable Set valueNumber of stages in the shift register, n. 16Number of taps in the feedback ath. 4Position of each tap (polynomial representation) f(x) = x'+ +XI + X4

+1

The polynomial f (x) = X +x + x5 + x4 +1 was chosenbecause it gives good autocorrelation. The polynomial couldhave taken in any form, as long as it gives good crosscorrelation.

Cross correlation is defined as the correlation between twodifferent signals. It is calculated by subtracting thedisagreements from the agreements between two differentsequences as opposed to the time-shifted replicas of the samesignal.

It is important to use a set ofPN sequences with minimal crosscorrelation with each other in order to reduce the effect ofadjacent channel interference. If the cross correlation is notsmall, there is a possibility that the data coded from one usercan be incorrectly identified and assigned to another becauseof similarity between the two keys.

Figure 1 shows the conceptual diagram for the 16-stage LFSR.Datain is an input port for the initial PN sequence, while theFillsel port selects the multiplexer input from either thefeedback or Datain. The registers are based on D flip-flops.The system timed by an internal clock, which sampled the PN

chip at half the rate as at the BPSK modulator. The Shiftenport used for shift enables or RESET. The resultant coded datamodulated using the BPSK modulator with a data rate of up to2 Mbps.

Fig. 1. Conceptual diagram of the 16-stage LFSR

The PN generator generates with chip clock signal starting foran initial state determined by initialization data.

A flow diagram of the basic steps of the PN code generatordesign is shown in Figure 2. Two major steps are explained inthis flow diagram as was just noted. Generation of the PNcode and multiplying it with the data entered were the twomain steps. When the 'data ready' is available at the input ofthe PN generator the code for each bit of the data will b,eavailable and waiting for data to enter. Shielen control the dataentering and shifted out of the PN generator. The coded data isshifted serially to PN generator output bit by bit. The shiltenswitch the PN generator ON until 16-bit coded data wereshifted out from the PN. Then the coded data had to wait for2-clock cycles to start shifting again. The data was stored inthe buffer during this time.

Fig. 2. The flow chart of the PN code generator

III. TRANSMITTER BLOCK DIAGRAM

Figure 3 shows the block diagram of the transmitter. Itcontains 7 blocks, namely, PN code generator, control block,multiplexer, 16-bit shift register, parity bit, 1-bit shift registerand PBSK modulator. The PN generator generates a DS-CDMA code, which is multiplied by the data entering the PNgenerator. The Shiften port is controlled by the PN codegenerator.

633

Here, the Control Block controls all the operations of thetransmitter and the timing for the transmitted bits, enabling themultiplexer and the 16-bit shift register. The multiplexer fedcoded data from the PN code generator and parity bit. The 16-bit shift register is used to shift the coded data parallel andserial to the parity and to the BPSK modulator simultaneously.The 16-bit coded data is shifted first to the parallel XORedparity calculation and fed back to the multiplexer after storagein the 1-bit shift register. The parity bit is added to the 16-bitwaiting for transmission in the 16-bit shift register. It is addedat the end of the 16-bit coded data.

This description of the design is intended to present basicideas behind the method and it omits details that mightobscure basic ideas. One such detail concems the nature of thelink between each step and timing. Flow chart design gives aclear idea about the design and its steps and links. A flowdiagram showing the basic flow of the DS-CDMA wirelesstransmitter is given in Figure 4. The operation is as follows:

* The coded data from the PN generator is multiplexedimmediately when it appears at the PN output.

* The coded data is delayed for 2-clock cycle at the PNgenerator after each 16-clock cycle (state at previous flowchart).

* The multiplexed data is shifted and stored at 16-bit shiftregister.

* For 16 clock cycles the multiplexer multiplex the outputof the PN generator.

* For 2 clock cycles after each 16-clock cycle themultiplexer waits to multiplex one bit from the parityoutput.

. For the initial time of simulation the data appears at thePN output after 32-clock cycle.

* The 16-bit shift register shifted the coded data in parallelto parity to perform 1-bit parity and stored in 1-bit shiftregister.

* The data stored at the 16-bit shift register waited for 2-clock cycle to start transmission through the BPSKmodulator in serial.

* The transmitted data frame contains 16-bit data with 1-bitparity.

Lsilt

3^ +-3 0 ~~~~~~~~~~~~~~~~~~~~~.144|t Fig. 4. The flow chart of the DS-CDMA wireless transmitter

IV. VHDL AND FPGA COMPILER II

The VHDL source code files were already created and savedin the same folder, all with the extension '.vhd'. These fileswere for the PN code generator, parity check (includingcontrol block, multiplexer, 16-bit shift register, parity bit and1-bit shift register), oscillator and BPSK modulator. A top-level design was created for the parity check files for thewhole design. Then the design was simulated and synthesizedto check its logical operation. The individual elements weresimulated using vhdlan and vhdlsim in the DOS command forWindows NT. The FPGA Compiler 11 was used for compilingand synthesizing the VHDL source code. The synthesisallowed the timing factors and the other influences of theactual FPGA devices to affect the simulation, thereby resultingin a more thorough check before the design was committed tothe FPGA. The results of this simulation and synthesis are theFPGA optimized chip. Test-bench files were created to test allthe above files. The purpose of a test bench is to verify thefunctionality of a model or package.

Figure 5 shows the input and output ports of the transmittersection. All transmitter components (PN code generator,BPSK modulator, oscillator, parity, control block, 16-bit shiftregister, multiplexer and 1-bit shift register) were combined atthis top-level design. The FPGA optimized chip for thetransmitter is shown in Figure 6. The final result waveformfrom the created test-bench for the top-level design is shownin Figure 7. The DS-CDMA wireless transmitter was designedto transmit data with higher data rates. 2 MHz was selected asthe clock rate to come out with 2 Mbps data rate. The

Fig. 3. The block diagram of the DS-CDMA transmitter.

634

calculation for this higher rate is taken manually from the VSSwaveform.

The time period used for this simulation was 250ns per halfcycle, which means 500 ns per full cycle. The data willtransmit serially through the BPSK modulator. At each clockcycle 1-bit will be transmitted. Because of the initialization ofthe transmission as shown in Figure 8 there are seen no data(U) appear at the transmitter output. After that, the data istransmitted continuously.

*1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.o t s o - d o......t .

FigThe inut oupu port of th to-ee dsig ,::th trns?te

The relationship between the frequency and the time period is:

tTwhere f is the frequency and T is the period time [5]. Theclock frequency used was 2 MHz so the period is 0.5 ,us, 500ns. For the 1st transmission, the data comes out from the BPSKmodulator after 34 clock cycles (34 clock cycle * 500 ns =1700), as shown in Figure 9. For 2 Mbps data rate there is2000000 bits per Is, so 2000000 clock cycles represent thesebits transmission. That means the data will come out after(2000000 clock cycle * 500 ns = 1000000000 ns) as shown inFigure 10. The data bits are calculated manually from thewavefonn viewer. From the calculation, it was observed thatthe transmitted data was less than 2 Mbps (1999964 bits onlycome out in I s). This happens because of the lost bits duringthe initial period.

c:~~ ~TOj.T

PTEOATI\

No data appears atthe output of theBPSKduetoirdtial

Fig. 8. VSS waveform represents the initialization of the transmission

Fig. 6. The Optimized FPGA Chip for the top-Level Design ofthe Transmitter

I 1011108 1208 1300 14a150I.. I.1 Ji !t! -l!.1. t!.tJi1.! !1}!t.}1.!J!!!!'!

flO

/TOP WTStFTEN 1

/loP -TaYFSEL 1

flop TB/DATAIN

iTO TSCO NX [(TOP TBS 0

fOPTIBP OUTI4 ±Ir: J c :.± . th _

I F - 182IC

-.dP TE- X .:

M-1p TN

First bit appears atthe BPSK output

100 17550 1i0t 0.! .

UI I

a,,.,.,,,{-,..t.-.<. . S t < > ^ q 24..... .....f : 1...:J ;.:

Fig. 9. VSS waveform of the transmitter showing the first transnsmitted bitsappear from the BPSK after 1 7000ns

635

Fig. 7 VSS waveform of the VHDL top-level file of the transmitter

riffliMllI-M

"'.-

l....

rim =..zom.:.:',' ',7:7,'::: ', Z: ::,', ''::':: :'; :.:.i'. :'< ',: 'z: ':'::''--:'A -' :' Si' ::' :.:...

... 1

VI. CONCLUSION

TO_--...l~ TATAJ'MP

MI T'PIZ1ThLast bit appear at the BPSK

C..........

output after Is simulation time *--,

Fig. 10. VSS waveform of the transmitter showing the end of I s timesimulation

V. HARDWARE IMPLEMENTATION

The FPGA compiler directory was used for simulation andsynthesis and downloading of the results to the XSV FPGAboard. This board, from Xilinx Virtex FPGA family board,with a single Virtex FPGA from 50K to 800K contained twoindependent banks of 512*16 SRAM for local buffering ofsignals and data.

The first step in downloading the design to the Xilinx XSV-300 FPGA board was the installation of the software. This wasto install the utility and configuration files for testing andprogramming the board. The second step was to configure thejumpers in the board. The XSV-300 Board came with shuntson the jumpers in their default arrangement. After this, powerapplied to the board from an ATX PC power supply. The nextstep was to connect the board to the parallel port of the PCthrough a 6-foot DB25 cable. Once the board is connected tothe PC with jumpers in their default configuration, it is nowready for testing. The last step was to program the interface tothe board and then download the design to the board using thegxload window of the software. Figure 11 shows thetransmitter after the final step of the downloading in the XCV-300 board. The board was tested. The LEDs were used toshow the 16-bit data and 1 -bit parity check at the output of thetransmitter.

VHDL behavioral modeling is useful in digital systems designbecause the designer can model the circuit in a program thatsimulates the circuit operation rather than spend time oncomplex finite state machines or truth tables. This greatlyfacilities and reduces the design time for a large digitalsystem.

The simulation waveforms presented in this paper have proventhe reliability of the VHDL implementation to describe thecharacteristics and the architecture of the digital transmitter.The simulated waveforms also have shown the observer howlong the test result can be achieved by using test-bench file.From the waveforms the digital transmitter transmitted at highdata rates of up to 2 Mbps with the BPSK modulator holdingthe data during transmission. The transmitted data included a1-bit parity that acted as error detection.

From the optimized FPGA circuit for top-level design, thecircuit of the transmitter was reduced sufficiently fordownloading to the Xilinx FPGA board. From testing, bothhardware and software components performed well andreliably.

REFERENCES

[1] Chang, K., C. (1997), Digital Design and Modeling with VHDL andSynthesis, IEEE service center, Piscataway.

[2] Cheah, J., Y, C., Practical Wireless Data Modem Design, Artech HousePublishers, Boston, London, 1999.

[3] Feher, K. (1995), Wireless Digital Communications, Prentice Hall, Inc.,Upper Saddle River, New Jersey.

[4] Gil, H., K., PN Code Acquisition Using Nonparametric Detectors in DS-CDMA Systems, Department of Electrical and Electronic, KoreaAdvanced Institute of Science and Technology (KAiST), SouthKorea,2000.

[51 Halsall, F., Data Commuunications, Computer Networks and Open Systems,Addison-Wesley Publications company, Harlow, England, 1996.

[6] Jakes, W. C., Jr. (1994), Microwave Mobile Communications, J. Wiley &Sons, New York, 1974; reprinted by IEEE Press, 1994, ISBN 0-7803-1069-1. http://www.cdg.org. Accessed on 2 Oct. 2001.

[71 Oianpera, T., Prasad, R., Wideband CDMA for Third Generation MobileCommunications, Artech House Publishers, Boston, London, 1998.

[8] Rushton, A., VIDL for Logic Synthesis, John Wiley & Sons Ltd,Chichester, England,1998.

[9] Zwolinski, M. (2000), Digital System Design with VHDL, PearsonEducation Ltd., England.

Fig. 1. The FPGA board after downloading the simulated and synthesizesVHDL files of the transmitter

636