CC430 Family

ECCN 5E002 TSPA - Technology / Software Publicly Available.

CC430 Family

User's Guide

Literature Number: SLAU259EMay 2009Revised January 2013


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Copyright 20092013, Texas Instruments Incorporated

Contents

Preface ...................................................................................................................................... 331 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) ...................... 35

1.1 System Control Module (SYS) Introduction ............................................................................ 361.2 System Reset and Initialization .......................................................................................... 36

1.2.1 Device Initial Conditions After System Reset ................................................................. 381.3 Interrupts .................................................................................................................... 38

1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 391.3.2 SNMI Timing ...................................................................................................... 401.3.3 Maskable Interrupts .............................................................................................. 411.3.4 Interrupt Processing .............................................................................................. 411.3.5 Interrupt Nesting .................................................................................................. 421.3.6 Interrupt Vectors .................................................................................................. 421.3.7 SYS Interrupt Vector Generators ............................................................................... 43

1.4 Operating Modes .......................................................................................................... 441.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4 ............................................ 471.4.2 Entering and Exiting Low-Power Modes LPMx.5 ............................................................. 471.4.3 Extended Time in Low-Power Modes .......................................................................... 48

1.5 Principles for Low-Power Applications .................................................................................. 501.6 Connection of Unused Pins .............................................................................................. 501.7 Reset Pin (RST/NMI) Configuration ..................................................................................... 511.8 Configuring JTAG pins .................................................................................................... 511.9 Boot Code .................................................................................................................. 511.10 Bootstrap Loader (BSL) .................................................................................................. 511.11 Memory Map Uses and Abilities ...................................................................................... 53

1.11.1 Vacant Memory Space ......................................................................................... 531.11.2 JTAG Lock Mechanism via the Electronic Fuse ............................................................. 53

1.12 JTAG Mailbox (JMB) System ............................................................................................ 541.12.1 JMB Configuration ............................................................................................... 541.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox ................................................................ 541.12.3 JMBIN0 and JMBIN1 Incoming Mailbox ...................................................................... 541.12.4 JMB NMI Usage ................................................................................................. 55

1.13 Device Descriptor Table .................................................................................................. 551.13.1 Identifying Device Type ......................................................................................... 561.13.2 TLV Descriptors ................................................................................................. 571.13.3 Peripheral Discovery Descriptor ............................................................................... 581.13.4 CRC Computation ............................................................................................... 621.13.5 Calibration Values ............................................................................................... 63

1.14 SFR Registers ............................................................................................................. 651.14.1 SFRIE1 Register ................................................................................................. 661.14.2 SFRIFG1 Register ............................................................................................... 671.14.3 SFRRPCR Register ............................................................................................. 69

1.15 SYS Registers ............................................................................................................. 701.15.1 SYSCTL Register ................................................................................................ 711.15.2 SYSBSLC Register .............................................................................................. 721.15.3 SYSJMBC Register ............................................................................................. 73

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1.15.4 SYSJMBI0 Register ............................................................................................. 741.15.5 SYSJMBI1 Register ............................................................................................. 741.15.6 SYSJMBO0 Register ............................................................................................ 751.15.7 SYSJMBO1 Register ............................................................................................ 751.15.8 SYSUNIV Register .............................................................................................. 761.15.9 SYSSNIV Register .............................................................................................. 771.15.10 SYSRSTIV Register ........................................................................................... 781.15.11 SYSBERRIV Register ......................................................................................... 79

2 Power Management Module and Supply Voltage Supervisor ................................................... 802.1 Power Management Module (PMM) Introduction ..................................................................... 812.2 PMM Operation ............................................................................................................ 83

2.2.1 VCORE and the Regulator ......................................................................................... 832.2.2 Supply Voltage Supervisor and Monitor ....................................................................... 832.2.3 Supply Voltage Supervisor and Monitor - Power-Up ........................................................ 892.2.4 Increasing VCORE to Support Higher MCLK Frequencies ..................................................... 892.2.5 Decreasing VCORE for Power Optimization ..................................................................... 912.2.6 Transition From LPM3 and LPM4 Modes to AM ............................................................. 912.2.7 LPM3.5 and LPM4.5 ............................................................................................. 912.2.8 Brownout Reset (BOR), Software BOR, Software POR ..................................................... 912.2.9 SVS and SVM Performance Modes and Wakeup Times ................................................... 922.2.10 PMM Interrupts .................................................................................................. 952.2.11 Port I/O Control .................................................................................................. 952.2.12 Supply Voltage Monitor Output (SVMOUT, Optional) ...................................................... 95

2.3 PMM Registers ............................................................................................................ 962.3.1 PMMCTL0 Register .............................................................................................. 972.3.2 PMMCTL1 Register .............................................................................................. 982.3.3 SVSMHCTL Register ............................................................................................ 992.3.4 SVSMLCTL Register ........................................................................................... 1002.3.5 SVSMIO Register ............................................................................................... 1012.3.6 PMMIFG Register ............................................................................................... 1022.3.7 PMMRIE Register ............................................................................................... 1042.3.8 PM5CTL0 Register ............................................................................................. 105

3 Unified Clock System (UCS) .............................................................................................. 1063.1 Unified Clock System (UCS) Introduction ............................................................................ 1073.2 UCS Operation ........................................................................................................... 109

3.2.1 UCS Module Features for Low-Power Applications ........................................................ 1093.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ............................................... 1093.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO) ......................................... 1103.2.4 XT1 Oscillator ................................................................................................... 1103.2.5 RF XT2 Oscillator ............................................................................................... 1113.2.6 Digitally-Controlled Oscillator (DCO) ......................................................................... 1113.2.7 Frequency Locked Loop (FLL) ................................................................................ 1113.2.8 DCO Modulator .................................................................................................. 1123.2.9 Disabling FLL Hardware and Modulator ..................................................................... 1133.2.10 FLL Operation From Low-Power Modes .................................................................... 1133.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules ............................... 1133.2.12 UCS Module Fail-Safe Operation ............................................................................ 1153.2.13 Synchronization of Clock Signals ............................................................................ 118

3.3 Module Oscillator (MODOSC) .......................................................................................... 1193.3.1 MODOSC Operation ............................................................................................ 119

3.4 UCS Module Registers .................................................................................................. 1203.4.1 UCSCTL0 Register ............................................................................................. 1213.4.2 UCSCTL1 Register ............................................................................................. 122

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3.4.3 UCSCTL2 Register ............................................................................................. 1233.4.4 UCSCTL3 Register ............................................................................................. 1243.4.5 UCSCTL4 Register ............................................................................................. 1253.4.6 UCSCTL5 Register ............................................................................................. 1263.4.7 UCSCTL6 Register ............................................................................................. 1283.4.8 UCSCTL7 Register ............................................................................................. 1293.4.9 UCSCTL8 Register ............................................................................................. 1303.4.10 UCSCTL9 Register ............................................................................................ 131

4 CPUX .............................................................................................................................. 1324.1 MSP430X CPU (CPUX) Introduction .................................................................................. 1334.2 Interrupts .................................................................................................................. 1354.3 CPU Registers ............................................................................................................ 136

4.3.1 Program Counter (PC) ......................................................................................... 1364.3.2 Stack Pointer (SP) .............................................................................................. 1364.3.3 Status Register (SR) ............................................................................................ 1384.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 1394.3.5 General-Purpose Registers (R4 R15) ...................................................................... 140

4.4 Addressing Modes ....................................................................................................... 1424.4.1 Register Mode ................................................................................................... 1434.4.2 Indexed Mode ................................................................................................... 1444.4.3 Symbolic Mode .................................................................................................. 1484.4.4 Absolute Mode .................................................................................................. 1534.4.5 Indirect Register Mode ......................................................................................... 1554.4.6 Indirect Autoincrement Mode .................................................................................. 1564.4.7 Immediate Mode ................................................................................................ 157

4.5 MSP430 and MSP430X Instructions .................................................................................. 1594.5.1 MSP430 Instructions ............................................................................................ 1594.5.2 MSP430X Extended Instructions .............................................................................. 164

4.6 Instruction Set Description .............................................................................................. 1754.6.1 Extended Instruction Binary Descriptions .................................................................... 1764.6.2 MSP430 Instructions ............................................................................................ 1784.6.3 Extended Instructions .......................................................................................... 2304.6.4 Address Instructions ............................................................................................ 273

5 Flash Memory Controller .................................................................................................. 2885.1 Flash Memory Introduction ............................................................................................. 2895.2 Flash Memory Segmentation ........................................................................................... 290

5.2.1 Segment A ....................................................................................................... 2915.3 Flash Memory Operation ................................................................................................ 292

5.3.1 Erasing Flash Memory ......................................................................................... 2925.3.2 Writing Flash Memory .......................................................................................... 2965.3.3 Flash Memory Access During Write or Erase ............................................................... 3035.3.4 Stopping Write or Erase Cycle ................................................................................ 3045.3.5 Checking Flash Memory ....................................................................................... 3045.3.6 Configuring and Accessing the Flash Memory Controller ................................................. 3055.3.7 Flash Memory Controller Interrupts ........................................................................... 3055.3.8 Programming Flash Memory Devices ........................................................................ 306

5.4 FCTL Registers ........................................................................................................... 3075.4.1 FCTL1 Register ................................................................................................. 3085.4.2 FCTL3 Register ................................................................................................. 3095.4.3 FCTL4 Register ................................................................................................. 3105.4.4 SFRIE1 Register ................................................................................................ 311

6 RAM Controller (RAMCTL) ................................................................................................ 3126.1 RAM Controller (RAMCTL) Introduction .............................................................................. 313




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6.2 RAMCTL Operation ...................................................................................................... 3136.3 RAMCTL Registers ...................................................................................................... 314

6.3.1 RCCTL0 Register ............................................................................................... 3157 Direct Memory Access (DMA) Controller Module ................................................................. 316

7.1 Direct Memory Access (DMA) Introduction ........................................................................... 3177.2 DMA Operation ........................................................................................................... 319

7.2.1 DMA Addressing Modes ....................................................................................... 3197.2.2 DMA Transfer Modes ........................................................................................... 3197.2.3 Initiating DMA Transfers ....................................................................................... 3257.2.4 Halting Executing Instructions for DMA Transfers .......................................................... 3257.2.5 Stopping DMA Transfers ....................................................................................... 3267.2.6 DMA Channel Priorities ........................................................................................ 3267.2.7 DMA Transfer Cycle Time ..................................................................................... 3277.2.8 Using DMA With System Interrupts ........................................................................... 3277.2.9 DMA Controller Interrupts ...................................................................................... 3277.2.10 Using the USCI_B I2C Module With the DMA Controller ................................................. 3297.2.11 Using ADC12 With the DMA Controller ..................................................................... 3297.2.12 Using DAC12 With the DMA Controller ..................................................................... 329

7.3 DMA Registers ........................................................................................................... 3307.3.1 DMACTL0 Register ............................................................................................. 3327.3.2 DMACTL1 Register ............................................................................................. 3337.3.3 DMACTL2 Register ............................................................................................. 3347.3.4 DMACTL3 Register ............................................................................................. 3357.3.5 DMACTL4 Register ............................................................................................. 3367.3.6 DMAxCTL Register ............................................................................................. 3377.3.7 DMAxSA Register ............................................................................................... 3397.3.8 DMAxDA Register ............................................................................................... 3407.3.9 DMAxSZ Register ............................................................................................... 3417.3.10 DMAIV Register ................................................................................................ 342

8 Digital I/O Module ............................................................................................................ 3438.1 Digital I/O Introduction ................................................................................................... 3448.2 Digital I/O Operation ..................................................................................................... 345

8.2.1 Input Registers (PxIN) .......................................................................................... 3458.2.2 Output Registers (PxOUT) ..................................................................................... 3458.2.3 Direction Registers (PxDIR) ................................................................................... 3458.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) .................................................. 3458.2.5 Output Drive Strength Registers (PxDS) ..................................................................... 3468.2.6 Function Select Registers (PxSEL) ........................................................................... 3468.2.7 Port Interrupts ................................................................................................... 3468.2.8 Configuring Unused Port Pins ................................................................................. 348

8.3 I/O Configuration and LPMx.5 Low-Power Modes ................................................................... 3488.4 Digital I/O Registers ..................................................................................................... 350

8.4.1 P1IV Register .................................................................................................... 3568.4.2 P2IV Register .................................................................................................... 3578.4.3 P1IES Register .................................................................................................. 3588.4.4 P1IE Register .................................................................................................... 3588.4.5 P1IFG Register .................................................................................................. 3588.4.6 P2IES Register .................................................................................................. 3598.4.7 P2IE Register .................................................................................................... 3598.4.8 P2IFG Register .................................................................................................. 3598.4.9 PxIN Register .................................................................................................... 3608.4.10 PxOUT Register ................................................................................................ 3608.4.11 PxDIR Register ................................................................................................. 360




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8.4.12 PxREN Register ................................................................................................ 3618.4.13 PxDS Register .................................................................................................. 3618.4.14 PxSEL Register ................................................................................................ 361

9 Port Mapping Controller ................................................................................................... 3629.1 Port Mapping Controller Introduction .................................................................................. 3639.2 Port Mapping Controller Operation .................................................................................... 363

9.2.1 Access ............................................................................................................ 3639.2.2 Mapping .......................................................................................................... 363

9.3 Port Mapping Controller Registers ..................................................................................... 3659.3.1 PMAPKEYID Register .......................................................................................... 3669.3.2 PMAPCTL Register ............................................................................................. 3669.3.3 PxMAPy Register ............................................................................................... 366

10 Cyclic Redundancy Check (CRC) Module ........................................................................... 36710.1 Cyclic Redundancy Check (CRC) Module Introduction ............................................................. 36810.2 CRC Standard and Bit Order ........................................................................................... 36810.3 CRC Checksum Generation ............................................................................................ 369

10.3.1 CRC Implementation .......................................................................................... 36910.3.2 Assembler Examples .......................................................................................... 370

10.4 CRC Registers ........................................................................................................... 37210.4.1 CRCDI Register ................................................................................................ 37310.4.2 CRCDIRB Register ............................................................................................ 37310.4.3 CRCINIRES Register .......................................................................................... 37410.4.4 CRCRESR Register ........................................................................................... 374

11 AES Accelerator .............................................................................................................. 37511.1 AES Accelerator Introduction ........................................................................................... 37611.2 AES Accelerator Operation ............................................................................................. 377

11.2.1 Encryption ....................................................................................................... 37811.2.2 Decryption ...................................................................................................... 37911.2.3 Decryption Key Generation ................................................................................... 38011.2.4 Using the AES Accelerator With Low-Power Modes ...................................................... 38111.2.5 AES Accelerator Interrupts ................................................................................... 38111.2.6 Implementing Block Cipher Modes .......................................................................... 381

11.3 AES_ACCEL Registers ................................................................................................. 38211.3.1 AESACTL0 Register ........................................................................................... 38311.3.2 AESACTL1 Register ........................................................................................... 38411.3.3 AESASTAT Register .......................................................................................... 38511.3.4 AESAKEY Register ............................................................................................ 38611.3.5 AESADIN Register ............................................................................................. 38711.3.6 AESADOUT Register .......................................................................................... 38711.3.7 AESAXDIN Register ........................................................................................... 38811.3.8 AESAXIN Register ............................................................................................. 388

12 Watchdog Timer (WDT_A) ................................................................................................. 38912.1 WDT_A Introduction ..................................................................................................... 39012.2 WDT_A Operation ....................................................................................................... 392

12.2.1 Watchdog Timer Counter (WDTCNT) ....................................................................... 39212.2.2 Watchdog Mode ................................................................................................ 39212.2.3 Interval Timer Mode ........................................................................................... 39212.2.4 Watchdog Timer Interrupts ................................................................................... 39212.2.5 Clock Fail-Safe Feature ....................................................................................... 39312.2.6 Operation in Low-Power Modes ............................................................................. 39312.2.7 Software Examples ............................................................................................ 393

12.3 WDT_A Registers ........................................................................................................ 394




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12.3.1 WDTCTL Register ............................................................................................. 39513 Timer_A .......................................................................................................................... 396

13.1 Timer_A Introduction .................................................................................................... 39713.2 Timer_A Operation ....................................................................................................... 399

13.2.1 16-Bit Timer Counter .......................................................................................... 39913.2.2 Starting the Timer .............................................................................................. 39913.2.3 Timer Mode Control ........................................................................................... 40013.2.4 Capture/Compare Blocks ..................................................................................... 40313.2.5 Output Unit ...................................................................................................... 40513.2.6 Timer_A Interrupts ............................................................................................. 409

13.3 Timer_A Registers ....................................................................................................... 41113.3.1 TAxCTL Register ............................................................................................... 41213.3.2 TAxR Register .................................................................................................. 41313.3.3 TAxCCTLn Register ........................................................................................... 41413.3.4 TAxCCRn Register ............................................................................................ 41613.3.5 TAxIV Register ................................................................................................. 41613.3.6 TAxEX0 Register ............................................................................................... 417

14 Real-Time Clock (RTC) Overview ....................................................................................... 41814.1 RTC Overview ............................................................................................................ 418

15 Real-Time Clock (RTC_A) .................................................................................................. 41915.1 RTC_A Introduction ...................................................................................................... 42015.2 RTC_A Operation ........................................................................................................ 422

15.2.1 Counter Mode .................................................................................................. 42215.2.2 Calendar Mode ................................................................................................. 42215.2.3 Real-Time Clock Interrupts ................................................................................... 42415.2.4 Real-Time Clock Calibration .................................................................................. 426

15.3 RTC_A Registers ........................................................................................................ 42815.3.1 RTCCTL0 Register ............................................................................................ 43015.3.2 RTCCTL1 Register ............................................................................................ 43115.3.3 RTCCTL2 Register ............................................................................................ 43215.3.4 RTCCTL3 Register ............................................................................................ 43215.3.5 RTCNT1 Register .............................................................................................. 43315.3.6 RTCNT2 Register .............................................................................................. 43315.3.7 RTCNT3 Register .............................................................................................. 43315.3.8 RTCNT4 Register .............................................................................................. 43315.3.9 RTCSEC Register Calendar Mode With Hexadecimal Format ........................................ 43415.3.10 RTCSEC Register Calendar Mode With BCD Format ................................................ 43415.3.11 RTCMIN Register Calendar Mode With Hexadecimal Format ....................................... 43515.3.12 RTCMIN Register Calendar Mode With BCD Format ................................................. 43515.3.13 RTCHOUR Register Calendar Mode With Hexadecimal Format .................................... 43615.3.14 RTCHOUR Register Calendar Mode With BCD Format .............................................. 43615.3.15 RTCDOW Register Calendar Mode ..................................................................... 43715.3.16 RTCDAY Register Calendar Mode With Hexadecimal Format ...................................... 43715.3.17 RTCDAY Register Calendar Mode With BCD Format ................................................ 43715.3.18 RTCMON Register Calendar Mode With Hexadecimal Format ...................................... 43815.3.19 RTCMON Register Calendar Mode With BCD Format ................................................ 43815.3.20 RTCYEARL Register Calendar Mode With Hexadecimal Format ................................... 43915.3.21 RTCYEARL Register Calendar Mode With BCD Format ............................................. 43915.3.22 RTCYEARH Register Calendar Mode With Hexadecimal Format ................................... 44015.3.23 RTCYEARH Register Calendar Mode With BCD Format ............................................. 44015.3.24 RTCAMIN Register Calendar Mode With Hexadecimal Format ..................................... 44115.3.25 RTCAMIN Register Calendar Mode With BCD Format ............................................... 44115.3.26 RTCAHOUR Register Calendar Mode With Hexadecimal Format .................................. 442




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15.3.27 RTCAHOUR Register Calendar Mode With BCD Format ............................................ 44215.3.28 RTCADOW Register ......................................................................................... 44315.3.29 RTCADAY Register Calendar Mode With Hexadecimal Format ..................................... 44315.3.30 RTCADAY Register Calendar Mode With BCD Format .............................................. 44315.3.31 RTCPS0CTL Register ....................................................................................... 44415.3.32 RTCPS1CTL Register ....................................................................................... 44515.3.33 RT0PS Register .............................................................................................. 44615.3.34 RT1PS Register .............................................................................................. 44615.3.35 RTCIV Register ............................................................................................... 446

16 Real-Time Clock D (RTC_D) ............................................................................................... 44716.1 Real-Time Clock RTC_D Introduction ................................................................................. 44816.2 RTC_D Operation ........................................................................................................ 450

16.2.1 Counter Mode .................................................................................................. 45016.2.2 Calendar Mode ................................................................................................. 45016.2.3 Real-Time Clock Interrupts ................................................................................... 45316.2.4 Real-Time Clock Calibration .................................................................................. 45416.2.5 Real-Time Clock Operation in LPMx.5 Low-Power Mode ................................................ 456

16.3 RTC_D Registers ........................................................................................................ 45716.3.1 RTCCTL0 Register ............................................................................................ 45916.3.2 RTCCTL1 Register ............................................................................................ 46016.3.3 RTCCTL2 Register ............................................................................................ 46116.3.4 RTCCTL3 Register ............................................................................................ 46116.3.5 RTCNT1 Register .............................................................................................. 46216.3.6 RTCNT2 Register .............................................................................................. 46216.3.7 RTCNT3 Register .............................................................................................. 46216.3.8 RTCNT4 Register .............................................................................................. 46216.3.9 RTCSEC Register Hexadecimal Format ................................................................. 46316.3.10 RTCSEC Register BCD Format .......................................................................... 46316.3.11 RTCMIN Register Hexadecimal Format ................................................................ 46416.3.12 RTCMIN Register BCD Format .......................................................................... 46416.3.13 RTCHOUR Register Hexadecimal Format ............................................................. 46516.3.14 RTCHOUR Register BCD Format ....................................................................... 46516.3.15 RTCDOW Register Calendar Mode ..................................................................... 46616.3.16 RTCDAY Register Hexadecimal Format ................................................................ 46616.3.17 RTCDAY Register BCD Format .......................................................................... 46616.3.18 RTCMON Register Hexadecimal Format ............................................................... 46716.3.19 RTCMON Register BCD Format ......................................................................... 46716.3.20 RTCYEAR Register Calendar Mode With Hexadecimal Format ..................................... 46816.3.21 RTCYEAR Register Calendar Mode With BCD Format .............................................. 46816.3.22 RTCAMIN Register Hexadecimal Format ............................................................... 46916.3.23 RTCAMIN Register BCD Format ......................................................................... 46916.3.24 RTCAHOUR Register Hexadecimal Format ............................................................ 47016.3.25 RTCAHOUR Register BCD Format ...................................................................... 47016.3.26 RTCADOW Register ......................................................................................... 47116.3.27 RTCADAY Register Hexadecimal Format .............................................................. 47116.3.28 RTCADAY Register BCD Format ........................................................................ 47116.3.29 RTCPS0CTL Register ....................................................................................... 47216.3.30 RTCPS1CTL Register ....................................................................................... 47316.3.31 RTCPS0 Register ............................................................................................ 47416.3.32 RTCPS1 Register ............................................................................................ 47416.3.33 RTCIV Register ............................................................................................... 47516.3.34 BIN2BCD Register ........................................................................................... 47616.3.35 BCD2BIN Register ........................................................................................... 476




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17 32-Bit Hardware Multiplier (MPY32) .................................................................................... 47717.1 32-Bit Hardware Multiplier (MPY32) Introduction .................................................................... 47817.2 MPY32 Operation ........................................................................................................ 480

17.2.1 Operand Registers ............................................................................................. 48117.2.2 Result Registers ................................................................................................ 48217.2.3 Software Examples ............................................................................................ 48317.2.4 Fractional Numbers ............................................................................................ 48417.2.5 Putting It All Together ......................................................................................... 48717.2.6 Indirect Addressing of Result Registers ..................................................................... 49017.2.7 Using Interrupts ................................................................................................ 49017.2.8 Using DMA ...................................................................................................... 491

17.3 MPY32 Registers ........................................................................................................ 49217.3.1 MPY32CTL0 Register ......................................................................................... 494

18 REF ................................................................................................................................ 49518.1 REF Introduction ......................................................................................................... 49618.2 Principle of Operation ................................................................................................... 498

18.2.1 Low-Power Operation ......................................................................................... 49818.2.2 REFCTL ......................................................................................................... 49918.2.3 Reference System Requests ................................................................................. 500

18.3 REF Registers ............................................................................................................ 50218.3.1 REFCTL0 Register (offset = 00h) [reset = 0080h] ......................................................... 503

19 ADC10_A ........................................................................................................................ 50519.1 ADC10_A Introduction ................................................................................................... 50619.2 ADC10_A Operation ..................................................................................................... 508

19.2.1 10-Bit ADC Core ............................................................................................... 50819.2.2 ADC10_A Inputs and Multiplexer ............................................................................ 50819.2.3 Voltage Reference Generator ................................................................................ 50919.2.4 Auto Power Down .............................................................................................. 50919.2.5 Sample and Conversion Timing .............................................................................. 50919.2.6 Conversion Result ............................................................................................. 51119.2.7 ADC10_A Conversion Modes ................................................................................ 51119.2.8 Window Comparator ........................................................................................... 51619.2.9 Using the Integrated Temperature Sensor ................................................................. 51719.2.10 ADC10_A Grounding and Noise Considerations ......................................................... 51819.2.11 ADC10_A Interrupts .......................................................................................... 518

19.3 ADC10_A Registers ..................................................................................................... 52019.3.1 ADC10CTL0 Register ......................................................................................... 52119.3.2 ADC10CTL1 Register ......................................................................................... 52219.3.3 ADC10CTL2 Register ......................................................................................... 52419.3.4 ADC10MEM0 Register ........................................................................................ 52519.3.5 ADC10MEM0 Register, 2s-Complement Format .......................................................... 52519.3.6 ADC10MCTL0 Register ....................................................................................... 52619.3.7 ADC10HI Register ............................................................................................. 52719.3.8 ADC10HI Register, 2s-Complement Format ............................................................... 52719.3.9 ADC10LO Register ............................................................................................ 52819.3.10 ADC10LO Register, 2s-Complement Format ............................................................. 52819.3.11 ADC10IE Register ............................................................................................ 52919.3.12 ADC10IFG Register .......................................................................................... 53019.3.13 ADC10IV Register ............................................................................................ 531

20 ADC12_A ........................................................................................................................ 53220.1 ADC12_A Introduction ................................................................................................... 53320.2 ADC12_A Operation ..................................................................................................... 536

20.2.1 12-Bit ADC Core ............................................................................................... 536




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20.2.2 ADC12_A Inputs and Multiplexer ............................................................................ 53620.2.3 Voltage Reference Generator ................................................................................ 53720.2.4 Auto Power Down .............................................................................................. 53820.2.5 Sample and Conversion Timing .............................................................................. 53820.2.6 Conversion Memory ........................................................................................... 54020.2.7 ADC12_A Conversion Modes ................................................................................ 54020.2.8 Using the Integrated Temperature Sensor ................................................................. 54620.2.9 ADC12_A Grounding and Noise Considerations .......................................................... 54720.2.10 ADC12_A Interrupts .......................................................................................... 548

20.3 ADC12_A Registers ..................................................................................................... 55020.3.1 ADC12CTL0 Register ......................................................................................... 55220.3.2 ADC12CTL1 Register ......................................................................................... 55420.3.3 ADC12CTL2 Register ......................................................................................... 55520.3.4 ADC12MEMx Register ........................................................................................ 55620.3.5 ADC12MCTLx Register ....................................................................................... 55720.3.6 ADC12IE Register ............................................................................................. 55820.3.7 ADC12IFG Register ........................................................................................... 56020.3.8 ADC12IV Register ............................................................................................. 562

21 Comp_B .......................................................................................................................... 56321.1 Comp_B Introduction .................................................................................................... 56421.2 Comp_B Operation ...................................................................................................... 565

21.2.1 Comparator ..................................................................................................... 56521.2.2 Analog Input Switches ......................................................................................... 56521.2.3 Port Logic ....................................................................................................... 56521.2.4 Input Short Switch ............................................................................................. 56521.2.5 Output Filter .................................................................................................... 56621.2.6 Reference Voltage Generator ................................................................................ 56721.2.7 Comp_B, Port Disable Register CBPD ..................................................................... 56821.2.8 Comp_B Interrupts ............................................................................................. 56821.2.9 Comp_B Used to Measure Resistive Elements ............................................................ 568

21.3 Comp_B Registers ....................................................................................................... 57021.3.1 CBCTL0 Register .............................................................................................. 57121.3.2 CBCTL1 Register .............................................................................................. 57221.3.3 CBCTL2 Register .............................................................................................. 57421.3.4 CBCTL3 Register .............................................................................................. 57521.3.5 CBINT Register ................................................................................................ 57721.3.6 CBIV Register .................................................................................................. 578

22 Universal Serial Communication Interface UART Mode ...................................................... 57922.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 58022.2 USCI Introduction UART Mode ...................................................................................... 58122.3 USCI Operation UART Mode ........................................................................................ 583

22.3.1 USCI Initialization and Reset ................................................................................. 58322.3.2 Character Format .............................................................................................. 58322.3.3 Asynchronous Communication Format ..................................................................... 58322.3.4 Automatic Baud-Rate Detection ............................................................................. 58622.3.5 IrDA Encoding and Decoding ................................................................................ 58722.3.6 Automatic Error Detection .................................................................................... 58822.3.7 USCI Receive Enable ......................................................................................... 58922.3.8 USCI Transmit Enable ........................................................................................ 58922.3.9 UART Baud-Rate Generation ................................................................................ 59022.3.10 Setting a Baud Rate .......................................................................................... 59222.3.11 Transmit Bit Timing ........................................................................................... 59222.3.12 Receive Bit Timing ........................................................................................... 593




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22.3.13 Typical Baud Rates and Errors ............................................................................. 59422.3.14 Using the USCI Module in UART Mode With Low-Power Modes ..................................... 59722.3.15 USCI Interrupts ............................................................................................... 597

22.4 USCI_A UART Mode Registers ........................................................................................ 59922.4.1 UCAxCTL0 Register ........................................................................................... 60022.4.2 UCAxCTL1 Register ........................................................................................... 60122.4.3 UCAxBR0 Register ............................................................................................ 60222.4.4 UCAxBR1 Register ............................................................................................ 60222.4.5 UCAxMCTL Register .......................................................................................... 60222.4.6 UCAxSTAT Register ........................................................................................... 60322.4.7 UCAxRXBUF Register ........................................................................................ 60422.4.8 UCAxTXBUF Register ......................................................................................... 60422.4.9 UCAxIRTCTL Register ........................................................................................ 60522.4.10 UCAxIRRCTL Register ...................................................................................... 60522.4.11 UCAxABCTL Register ....................................................................................... 60622.4.12 UCAxIE Register ............................................................................................. 60722.4.13 UCAxIFG Register ........................................................................................... 60722.4.14 UCAxIV Register ............................................................................................. 608

23 Universal Serial Communication Interface SPI Mode ......................................................... 60923.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 61023.2 USCI Introduction SPI Mode ......................................................................................... 61123.3 USCI Operation SPI Mode ........................................................................................... 613

23.3.1 USCI Initialization and Reset ................................................................................. 61323.3.2 Character Format .............................................................................................. 61323.3.3 Master Mode .................................................................................................... 61423.3.4 Slave Mode ..................................................................................................... 61523.3.5 SPI Enable ...................................................................................................... 61523.3.6 Serial Clock Control ........................................................................................... 61623.3.7 Using the SPI Mode With Low-Power Modes .............................................................. 61623.3.8 SPI Interrupts ................................................................................................... 617

23.4 USCI_A SPI Mode Registers ........................................................................................... 61823.4.1 UCAxCTL0 Register ........................................................................................... 61923.4.2 UCAxCTL1 Register ........................................................................................... 62023.4.3 UCAxBR0 Register ............................................................................................ 62123.4.4 UCAxBR1 Register ............................................................................................ 62123.4.5 UCAxMCTL Register .......................................................................................... 62123.4.6 UCAxSTAT Register ........................................................................................... 62223.4.7 UCAxRXBUF Register ........................................................................................ 62323.4.8 UCAxTXBUF Register ......................................................................................... 62323.4.9 UCAxIE Register ............................................................................................... 62423.4.10 UCAxIFG Register ........................................................................................... 62423.4.11 UCAxIV Register ............................................................................................. 625

23.5 USCI_B SPI Mode Registers ........................................................................................... 62623.5.1 UCBxCTL0 Register ........................................................................................... 62723.5.2 UCBxCTL1 Register ........................................................................................... 62823.5.3 UCBxBR0 Register ............................................................................................ 62923.5.4 UCBxBR1 Register ............................................................................................ 62923.5.5 UCBxMCTL Register .......................................................................................... 62923.5.6 UCBxSTAT Register ........................................................................................... 63023.5.7 UCBxRXBUF Register ........................................................................................ 63123.5.8 UCBxTXBUF Register ......................................................................................... 63123.5.9 UCBxIE Register ............................................................................................... 63223.5.10 UCBxIFG Register ........................................................................................... 632




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23.5.11 UCBxIV Register ............................................................................................. 63324 Universal Serial Communication Interface I2C Mode .......................................................... 634

24.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 63524.2 USCI Introduction I2C Mode .......................................................................................... 63624.3 USCI Operation I2C Mode ............................................................................................ 637

24.3.1 USCI Initialization and Reset ................................................................................. 63824.3.2 I2C Serial Data .................................................................................................. 63824.3.3 I2C Addressing Modes ......................................................................................... 64024.3.4 I2C Module Operating Modes ................................................................................. 64124.3.5 I2C Clock Generation and Synchronization ................................................................. 65224.3.6 Using the USCI Module in I2C Mode With Low-Power Modes ........................................... 65324.3.7 USCI Interrupts in I2C Mode .................................................................................. 653

24.4 USCI_B I2C Mode Registers ........................................................................................... 65624.4.1 UCBxCTL0 Register ........................................................................................... 65724.4.2 UCBxCTL1 Register ........................................................................................... 65824.4.3 UCBxBR0 Register ............................................................................................ 65924.4.4 UCBxBR1 Register ............................................................................................ 65924.4.5 UCBxSTAT Register ........................................................................................... 66024.4.6 UCBxRXBUF Register ........................................................................................ 66124.4.7 UCBxTXBUF Register ......................................................................................... 66124.4.8 UCBxI2COA Register ......................................................................................... 66224.4.9 UCBxI2CSA Register .......................................................................................... 66224.4.10 UCBxIE Register ............................................................................................. 66324.4.11 UCBxIFG Register ........................................................................................... 66424.4.12 UCBxIV Register ............................................................................................. 665

25 CC1101-Based Radio Module (RF1A) .................................................................................. 66625.1 Radio Module Introduction .............................................................................................. 66725.2 Radio Interface Operation .............................................................................................. 668

25.2.1 Radio Interface ................................................................................................. 66825.2.2 Radio Interface Interrupts ..................................................................................... 67425.2.3 Radio Core Interrupts ......................................................................................... 67425.2.4 Using Radio With Low-Power Modes ....................................................................... 67525.2.5 Radio Interrupt Handling ...................................................................................... 67525.2.6 Software Considerations ...................................................................................... 678

25.3 CC1101-Based Radio Core ............................................................................................. 68025.3.1 Differences From CC1101 .................................................................................... 68025.3.2 Instruction Set for CC1101-Based Radio Core ............................................................ 68125.3.3 Radio-Core Operation ......................................................................................... 68425.3.4 System Considerations and Guidelines ..................................................................... 70525.3.5 Radio Core Registers ......................................................................................... 709

25.4 RF1A Registers .......................................................................................................... 73225.4.1 RF1AIFCTL0 Register ......................................................................................... 73425.4.2 RF1AIFCTL1 Register ......................................................................................... 73525.4.3 RF1AIFERR Register .......................................................................................... 73625.4.4 RF1AIFERRV Register ........................................................................................ 73725.4.5 RF1AIFIV Register ............................................................................................. 73725.4.6 RF1AIN Register ............................................................................................... 73825.4.7 RF1AIFG Register ............................................................................................. 73825.4.8 RF1AIES Register ............................................................................................. 73925.4.9 RF1AIE Register ............................................................................................... 73925.4.10 RF1AIV Register .............................................................................................. 740

26 LCD_B Controller ............................................................................................................. 74126.1 LCD_B Controller Introduction ......................................................................................... 742




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26.2 LCD_B Controller Operation ............................................................................................ 74426.2.1 LCD Memory ................................................................................................... 74426.2.2 LCD Timing Generation ....................................................................................... 74426.2.3 Blanking the LCD .............................................................................................. 74526.2.4 LCD Blinking .................................................................................................... 74526.2.5 LCD_B Voltage And Bias Generation ....................................................................... 74626.2.6 LCD Outputs .................................................................................................... 74826.2.7 LCD_B Interrupts .............................................................................................. 74826.2.8 Static Mode ..................................................................................................... 75026.2.9 2-Mux Mode .................................................................................................... 75326.2.10 3-Mux Mode ................................................................................................... 75626.2.11 4-Mux Mode ................................................................................................... 759

26.3 LCD_B Registers ......................................................................................................... 76226.3.1 LCDBCTL0 Register ........................................................................................... 76526.3.2 LCDBCTL1 Register ........................................................................................... 76626.3.3 LCDBBLKCTL Register ....................................................................................... 76726.3.4 LCDBMEMCTL Register ...................................................................................... 76826.3.5 LCDBVCTL Register .......................................................................................... 76926.3.6 LCDBPCTL0 Register ......................................................................................... 77126.3.7 LCDBPCTL1 Register ......................................................................................... 77126.3.8 LCDBPCTL2 Register ......................................................................................... 77226.3.9 LCDBPCTL3 Register ......................................................................................... 77226.3.10 LCDBCPCTL Register ....................................................................................... 77326.3.11 LCDBIV Register ............................................................................................. 774

27 Embedded Emulation Module (EEM) .................................................................................. 77527.1 Embedded Emulation Module (EEM) Introduction ................................................................... 77627.2 EEM Building Blocks .................................................................................................... 778

27.2.1 Triggers ......................................................................................................... 77827.2.2 Trigger Sequencer ............................................................................................. 77827.2.3 State Storage (Internal Trace Buffer) ........................................................................ 77827.2.4 Cycle Counter .................................................................................................. 77827.2.5 Clock Control ................................................................................................... 779

27.3 EEM Configurations ..................................................................................................... 779Revision History ....................................................................................................................... 780




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List of Figures1-1. BOR/POR/PUC Reset Circuit............................................................................................ 371-2. Interrupt Priority............................................................................................................ 391-3. NMIs With Reentrance Protection....................................................................................... 401-4. Interrupt Processing....................................................................................................... 411-5. Return From Interrupt ..................................................................................................... 421-6. Operation Modes .......................................................................................................... 451-7. Devices Descriptor Table................................................................................................. 561-8. SFRIE1 Register........................................................................................................... 661-9. SFRIFG1 Register......................................................................................................... 671-10. SFRRPCR Register ....................................................................................................... 691-11. SYSCTL Register.......................................................................................................... 711-12. SYSBSLC Register........................................................................................................ 721-13. SYSJMBC Register ....................................................................................................... 731-14. SYSJMBI0 Register ....................................................................................................... 741-15. SYSJMBI1 Register ....................................................................................................... 741-16. SYSJMBO0 Register...................................................................................................... 751-17. SYSJMBO1 Register...................................................................................................... 751-18. SYSUNIV Register ........................................................................................................ 761-19. SYSSNIV Register ........................................................................................................ 771-20. SYSRSTIV Register....................................................................................................... 781-21. SYSBERRIV Register..................................................................................................... 792-1. System Frequency, Supply Voltage, and Core Voltage See Device-Specific Data Sheet .................... 812-2. PMM Block Diagram ...................................................................................................... 822-3. Available SVMH Settings Versus VCORE Settings.................................................................... 852-4. High-Side and Low-Side Voltage Failure and Resulting PMM Actions............................................. 862-5. High-Side SVS and SVM ................................................................................................. 872-6. Low-Side SVS and SVM.................................................................................................. 882-7. PMM Action at Device Power-Up ....................................................................................... 892-8. Changing VCORE and SVML and SVSL Levels........................................................................... 902-9. PMMCTL0 Register ....................................................................................................... 972-10. PMMCTL1 Register ....................................................................................................... 982-11. SVSMHCTL Register ..................................................................................................... 992-12. SVSMLCTL Register .................................................................................................... 1002-13. SVSMIO Register ........................................................................................................ 1012-14. PMMIFG Register ........................................................................................................ 1022-15. PMMRIE Register ........................................................................................................ 1042-16. PM5CTL0 Register ...................................................................................................... 1053-1. UCS Block Diagram ..................................................................................................... 1083-2. Modulator Patterns....................................................................................................... 1123-3. Module Request Clock System ........................................................................................ 1143-4. Oscillator Fault Logic .................................................................................................... 1173-5. Switch MCLK from DCOCLK to XT1CLK ............................................................................. 1183-6. UCSCTL0 Register ...................................................................................................... 1213-7. UCSCTL1 Register ...................................................................................................... 1223-8. UCSCTL2 Register ...................................................................................................... 1233-9. UCSCTL3 Register ...................................................................................................... 1243-10. UCSCTL4 Register ...................................................................................................... 125

15SLAU259EMay 2009Revised January 2013 List of FiguresSubmit Documentation Feedback



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3-11. UCSCTL5 Register ...................................................................................................... 1263-12. UCSCTL6 Register ...................................................................................................... 1283-13. UCSCTL7 Register ...................................................................................................... 1293-14. UCSCTL8 Register ...................................................................................................... 1303-15. UCSCTL9 Register ...................................................................................................... 1314-1. MSP430X CPU Block Diagram ........................................................................................ 1344-2. PC Storage on the Stack for Interrupts ............................................................................... 1354-3. Program Counter......................................................................................................... 1364-4. PC Storage on the Stack for CALLA .................................................................................. 1364-5. Stack Pointer ............................................................................................................. 1374-6. Stack Usage .............................................................................................................. 1374-7. PUSHX.A Format on the Stack ........................................................................................ 1374-8. PUSH SP, POP SP Sequence ......................................................................................... 1374-9. SR Bits .................................................................................................................... 1384-10. Register-Byte and Byte-Register Operation .......................................................................... 1404-11. Register-Word Operation ............................................................................................... 1404-12. Word-Register Operation ............................................................................................... 1414-13. Register Address-Word Operation .................................................................................. 1414-14. Address-Word Register Operation .................................................................................. 1424-15. Indexed Mode in Lower 64 KB ......................................................................................... 1444-16. Indexed Mode in Upper Memory....................................................................................... 1454-17. Overflow and Underflow for Indexed Mode........................................................................... 1464-18. Example for Indexed Mode ............................................................................................. 1474-19. Symbolic Mode Running in Lower 64 KB ............................................................................. 1494-20. Symbolic Mode Running in Upper Memory .......................................................................... 1504-21. Overflow and Underflow for Symbolic Mode ......................................................................... 1514-22. MSP430 Double-Operand Instruction Format........................................................................ 1594-23. MSP430 Single-Operand Instructions ................................................................................. 1604-24. Format of Conditional Jump Instructions.............................................................................. 1614-25. Extension Word for Register Modes................................................................................... 1644-26. Extension Word for Non-Register Modes............................................................................. 1644-27. Example for Extended Register or Register Instruction............................................................. 1654-28. Example for Extended Immediate or Indexed Instruction........................................................... 1664-29. Extended Format I Instruction Formats ............................................................................... 1674-30. 20-Bit Addresses in Memory ........................................................................................... 1674-31. Extended Format II Instruction Format................................................................................ 1684-32. PUSHM and POPM Instruction Format ............................................................................... 1694-33. RRCM, RRAM, RRUM, and RLAM Instruction Format ............................................................. 1694-34. BRA Instruction Format ................................................................................................. 1694-35. CALLA Instruction Format .............................................................................................. 1694-36. Decrement Overlap ...................................................................................................... 1954-37. Stack After a RET Instruction .......................................................................................... 2144-38. Destination OperandArithmetic Shift Left .......................................................................... 2164-39. Destination OperandCarry Left Shift ................................................................................ 2174-40. Rotate Right Arithmetically RRA.B and RRA.W ..................................................................... 2184-41. Rotate Right Through Carry RRC.B and RRC.W.................................................................... 2194-42. Swap Bytes in Memory.................................................................................................. 2264-43. Swap Bytes in a Register ............................................................................................... 2264-44. Rotate Left ArithmeticallyRLAM[.W] and RLAM.A ................................................................ 253

16 List of Figures SLAU259EMay 2009Revised January 2013Submit Documentation Feedback


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