cc2530

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1FEATURES

APPLICATIONS

CC2530F32, CC2530F64, CC2530F128, CC2530F256

www.ti.com ................................................................................................................................................................................................. SWRS081–MARCH 2009

A True System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee Applications– Accurate Digital RSSI/LQI Support

2345• RF/Layout – Battery Monitor and Temperature Sensor– 2.4-GHz IEEE 802.15.4 Compliant RF – 12-Bit ADC with Eight Channels and

Transceiver Configurable Resolution– Excellent Receiver Sensitivity and – AES Security Coprocessor

Robustness to Interference – Two Powerful USARTs With Support for– Very Few External Components Several Serial Protocols– Only a Single Crystal Needed for Mesh – 21 General-Purpose I/O Pins (19x 4mA, 2x

Network Systems 20 mA)– 6-mm × 6-mm QFN40 Package – Watchdog Timer– Suitable for systems targeting compliance • Development Tools

with worldwide radio frequency – CC2530 Development Kitregulations: ETSI EN 300 328 and EN 300 – CC2530 ZigBee® Development Kit440 class 2 (Europe), FCC CFR47 Part 15

– CC2530 RemoTI™ Development Kit for(US) and ARIB STD-T66 (Japan)RF4CE

• Low Power– SmartRF™ Software

– Active Mode RX (CPU running at 32 MHz):– Packet Sniffer22 mA– IAR Embedded Workbench™ Available– Active Mode TX@0dBm (CPU running at 32

MHz): 29 mA– Power Mode 1 (3 µs wake-up): 105 µA • 2.4-GHz IEEE 802.15.4 Systems– Power Mode 2 (sleep timer running): 0.8 µA • RF4CE Remote Control Systems (64KB Flash– Power Mode 3 (external interrupts): 0.4 µA and Higher)– Wide Supply Voltage Range (2 V–3.6 V) • ZigBee Systems (256KB Flash)

• Home/Building Automation• Microcontroller• Lighting Systems– High-Performance and Low-Power 8051

Microcontroller Core with Code Prefetch • Industrial Control and Monitoring• Low-Power Wireless Sensor Networks– 32-, 64-, 128-, or 256-KB

In-System-Programmable Flash • Consumer Electronics• Health Care– 8-KB RAM with Retention in all Power

Modes– Hardware Debug Support

• Peripherals– Powerful Five-Channel DMA– IEEE 802.15.4 MAC Timer, General-Purpose

Timers (One 16-Bit, Two 8-Bit)– IR Generation Circuitry– 32-kHz Sleep Timer With Capture– CSMA/CA Hardware Support

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2RemoTI, SmartRF, Z-Stack are trademarks of Texas Instruments.3IAR Embedded Workbench is a trademark of IAR Systems AB.4ZigBee is a registered trademark of the ZigBee Alliance.5All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the Copyright © 2009, Texas Instruments Incorporatedformative or design phase of development. Characteristic data andother specifications are design goals. Texas Instruments reservesthe right to change or discontinue these products without notice.

http://focus.ti.com/docs/prod/folders/print/cc2530f32.html




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DESCRIPTION

RESETWATCHDOG

TIMER

IRQ CTRL FLASH WRITE

DEBUGINTERFACE

CLOCK MUX andCALIBRATION

MODULATORDEMODULATOR

DMA8051 CPU

COREMEMORY

ARBITRATOR

32-MHz

CRYSTAL OSC

32.768-kHz

CRYSTAL OSC

32-kHz

RC-OSC

HIGH-SPEED

RC-OSC

ON-CHIP VOLTAGE

REGULATOR

POWER ON RESET

BROWN OUT

DIGITAL

ANALOG

MIXED

SLEEP TIMER

SLEEP MODE CONTROLLER

CSMA/CA STROBEPROCESSOR

RADIO REGISTERS

RADIO DATA INTERFACE

FIF

O a

nd F

RA

ME

CO

NT

RO

LUSART 1

USART 2

TIMER 1 (16-Bit)

TIMER 3 (8-Bit)

TIMER 4 (8-Bit)

TIMER 2(IEEE 802.15.4 MAC TIMER)

32/64/128/256-KBFLASH

8-KB SRAM

ADC

AUDIO/DC

8 CHANNELS

RECEIVE

CHAIN

TRANSMIT

CHAIN

AESENCRYPTION

ANDDECRYPTION

FR

EQ

UE

NC

Y

SY

NT

HE

SIZ

ER

AGC

VDD (2 V–3.6 V)

DCOUPL

I/O

CO

NT

RO

LL

ER

RF_P RF_N

XOSC_Q2

RESET_N

XOSC_Q1

P2_4

P1_7

P0_7

P2_3

P1_6

P0_6

P2_2

P1_5

P0_5

P1_2

P0_2

P2_1

P1_4

P0_4

P1_1

P0_1

P2_0

P1_3

P0_3

P1_0

P0_0

B0300-02

CC2530F32, CC2530F64, CC2530F128, CC2530F256

SWRS081–MARCH 2009 ................................................................................................................................................................................................. www.ti.com

The CC2530 is a true system-on-chip (SoC) solution for IEEE 802.15.4, Zigbee and RF4CE applications. Itenables robust network nodes to be built with very low total bill-of-material costs. The CC2530 combines theexcellent performance of a leading RF transceiver with an industry-standard enhanced 8051 MCU, in-systemprogrammable flash memory, 8-KB RAM, and many other powerful features. The CC2530 comes in four differentflash versions: CC2530F32/64/128/256, with 32/64/128/256 KB of flash memory, respectively. The CC2530 ishighly suited for systems where ultralow power consumption is required. This is ensured by various operatingmodes. Short transition times between operating modes further ensure low power consumption.

Combined with the industry-leading ZigBee protocol stack (Z-Stack™) from Texas Instruments, the CC2530F256provides the market's most robust ZigBee solution.

Combined with the golden unit status RemoTI stack from Texas Instruments, the CC2530F64 and higher providethe market's most robust RF4CE remote control solution.

2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): CC2530F32 CC2530F64 CC2530F128 CC2530F256





http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SWRS081&partnum=CC2530F32





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ABSOLUTE MAXIMUM RATINGS (1)

RECOMMENDED OPERATING CONDITIONS

CC2530F32, CC2530F64, CC2530F128, CC2530F256


This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

MIN MAX UNITSupply voltage All supply pins must have the same voltage –0.3 3.9 V

–0.3 VDD + 0.3,Voltage on any digital pin V≤ 3.9

Input RF level 10 dBmStorage temperature range -40 125 °CReflow soldering temperature According to IPC/JEDEC J-STD-020C 260 °C

All pads, according to human-body model, JEDEC STD 22, method 2 kVA114ESD (2)

According to charged-device model, JEDEC STD 22, method C101 500 V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) CAUTION: ESD sensitive device. Precaution should be used when handing the devicein order to prevent permanent damage.

MIN MAX UNITOperating ambient temperature range, TA –40 125 °COperating supply voltage 2 3.6 V

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3











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ELECTRICAL CHARACTERISTICS

CC2530F32, CC2530F64, CC2530F128, CC2530F256


Measured on Texas Instruments CC2530 EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.Boldface limits apply over the entire operating range, TA = -40°C to +125°C, VDD = 2 V to 3 V and Fc = 2394 to 2507 MHz.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITDigital regulator on. 16-MHz RCOSC running. No radio,crystals, or peripherals active. 3.6 mAMedium MCU activity: normal flash access (1), no RAM access32-MHz XOSC running. No radio or peripherals active. 7.2 mAMedium MCU activity: normal flash access (1), no RAM accessMCU running at full speed (32 MHz), 32-MHz XOSC running, 22radio in RX mode, –50-dBm input power, no peripherals mAactive, low MCU activityMCU running at full speed (32 MHz), 32-MHz XOSC running, 25radio in RX mode, at sensitivity limit / waiting for signal, no mAperipherals active, low MCU activityMCU running at full speed (32 MHz), 32-MHz XOSC running, 29Ixxx Core current consumption radio in TX mode, 0 dBm output power, no peripherals active, mAlow MCU activityMCU running at full speed (32 MHz), 32-MHz XOSC running, 34radio in TX mode, +4 dBm output power, no peripherals mAactive, low MCU activityPower mode 1. Digital regulator on; 16-MHz RCOSC and 10532-MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD µAand sleep timer active; RAM and register retentionPower mode 2. Digital regulator off; 16-MHz RCOSC and 0.832-MHz crystal oscillator off; 32.768-kHz XOSC, POR, and µAsleep timer active; RAM and register retentionPower mode 3. Digital regulator off; No clocks; POR active; 0.4 µARAM and register retention

Peripheral Current Consumption (Adds to core current Ixxx for each peripheral unit activated)Timer 1 Timer running, 32-MHz XOSC used 150 µATimer 2 Timer running, 32-MHz XOSC used 230 µA

Iyyy Timer 3 Timer running, 32-MHz XOSC used 50 µATimer 4 Timer running, 32-MHz XOSC used 50 µASleep timer Including 32.753-kHz RCOSC 0.2 µAADC When converting 1.2 mA

(1) Normal flash access means that the code used exceeds the cache storage, so cache misses happen frequently.












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GENERAL CHARACTERISTICS

RF RECEIVE SECTION

CC2530F32, CC2530F64, CC2530F128, CC2530F256


Measured on Texas Instruments CC2530 EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITWAKE-UP AND TIMING

Digital regulator on, 16-MHz RCOSC and 32-MHz crystalPower mode 1 → Active 4 µsoscillator off. Start-up of 16-MHz RCOSC.Digital regulator off, 16-MHz RCOSC and 32-MHz crystalPower mode 2 or 3 → Active 120 µsoscillator off. Start-up of regulator and 16-MHz RCOSC.Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC, 0.5 mswith 32-MHz XOSC OFF.Active → TX or RXWith 32-MHz XOSC initially on. 192 µs

RX/TX turnaround 192 µsRADIO PART

Programmable in 1-MHz steps, 5 MHz between channelsRF frequency range 2394 2507 MHzfor compliance with [1]250 kbps

Radio chip rate As defined by [1]2 MChip/s

Measured on Texas Instruments CC2530 EM reference design with TA = 25°C, VDD = 3 V and Fc = 2440 MHz, unlessotherwise noted.Boldface limits apply over the entire operating range, TA = -40°C to +125°C, VDD = 2 V to 3 V and Fc = 2394 to 2507 MHz.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITPER = 1%, as specified by [1] –97Receiver sensitivity dBm[1] requires –85 dBmPER = 1%, as specified by [1]Saturation (maximum input level) 10 dBm[1] requires –20 dBmWanted signal –88 dBm, adjacent modulated channel atAdjacent-channel rejection, 5-MHz 5 MHz, PER = 1 %, as specified by [1]. 49 dBchannel spacing [1] requires 0 dBWanted signal –88 dBm, adjacent modulated channel atAdjacent-channel rejection, –5-MHz –5 MHz, PER = 1 %, as specified by [1]. 49 dBchannel spacing [1] requires 0 dBWanted signal –88 dBm, adjacent modulated channel atAlternate-channel rejection, 10-MHz 10 MHz, PER = 1%, as specified by [1] 54 dBchannel spacing [1] requires 30 dBWanted signal –88 dBm, adjacent modulated channel atAlternate-channel rejection, –10-MHz –10 MHz, PER = 1 %, as specified by [1] 54 dBchannel spacing [1] requires 30 dB

Channel rejection Wanted signal at –82 dBm. Undesired signal is an IEEE802.15.4 modulated channel, stepped through all channels≥ 20 MHz 55 dBfrom 2405 to 2480 MHz. Signal level for PER = 1%. Values≤ –20 MHz 55are estimated.

Co-channel rejection Wanted signal at –82 dBm. Undesired signal is 802.15.4 -5modulated at the same frequency as the desired signal. Signal dBlevel for PER = 1%.

Blocking/desensitization5 MHz from band edge Wanted signal 3 dB above the sensitivity level, CW jammer, -4210 MHz from band edge PER = 1%. Measured according to EN 300 440 class 2. -4220 MHz from band edge -42

dBm50 MHz from band edge -37–5 MHz from band edge -42–10 MHz from band edge -42–20 MHz from band edge -42–50 MHz from band edge -37












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RF TRANSMIT SECTION

CC2530F32, CC2530F64, CC2530F128, CC2530F256


RF RECEIVE SECTION (continued)Measured on Texas Instruments CC2530 EM reference design with TA = 25°C, VDD = 3 V and Fc = 2440 MHz, unlessotherwise noted.Boldface limits apply over the entire operating range, TA = -40°C to +125°C, VDD = 2 V to 3 V and Fc = 2394 to 2507 MHz.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITSpurious emission. Only largest spurious

Conducted measurement with a 50-Ω single-ended load.emission stated within each band.Complies with EN 300 328, EN 300 440 class 2, FCC CFR47, dBm

30 MHz–1000 MHz <-80Part 15 and ARIB STD-T-66.1 GHz–12.75 GHz -56Frequency error tolerance (1) [1] requires minimum 80 ppm +/-160 ppmSymbol rate error tolerance (2) [1] requires minimum 80 ppm +/-900 ppm

(1) Difference between center frequency of the received RF signal and local oscillator frequency.(2) Difference between incoming symbol rate and the internally generated symbol rate

Measured on Texas Instruments CC2530 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz, unlessotherwise noted.Boldface limits apply over the entire operating range, TA = –40°C to 125°C, VDD = 2 V to 3 V and Fc = 2394 MHz to 2507MHz.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITDelivered to a single-ended 50-Ω load through a balun using 4maximum recommended output power setting.Nominal output power dBm[1] requires minimum –3 dBm

Programmable output power 32 dBrangeSpurious emissions Max recommended output power setting (1)

Measured according to stated 25 MHz–1000 MHz (outside restricted bands) -60regulations. Only largest 25 MHz - 2400 MHz (within FCC restricted bands) -60spurious emission stated 25 MHz - 1000 MHz (within ETSI restricted bands) -60within each band. 1800 - 1900 MHz (ETSI restricted band) -56

5150 - 5300 MHz (ETSI restricted band) -54 dBmAt 2483.5MHz and above (FCC restricted band)Fc=2480 MHz, max recommended output power setting -44Fc=2480 MHz, 0dBm output power -48

At 2*Fc and 3*Fc (FCC restricted bands) -431 GHz - 12.75 GHz (outside restricted bands) -54Measured as defined by [1]Error vector magnitude (EVM) 2 %[1] requires maximum 35%.Differential impedance as seen from the RF-port (RF_P and RF_N) 69+j29Optimum load impedance Ωtowards the antenna (2)

(1) Texas Instruments CC2530 EM reference design complies with EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T-66.(2) This is for 2440 MHz.












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32-MHz CRYSTAL OSCILLATOR

32.768-kHz CRYSTAL OSCILLATOR

32-kHz RC OSCILLATOR

CC2530F32, CC2530F64, CC2530F128, CC2530F256



PARAMETER TEST CONDITIONS MIN TYP MAX UNITCrystal frequency 32 MHzCrystal frequency accuracy –40 40 ppmrequirement (1)

ESR Equivalent series resistance (2) 6 16 60 ΩC0

(2) 1 1.9 7 pFCL

(2) 10 13 16 pFStart-up time 0.3 msPower down guard time The crystal oscillator must be in power down for a 3 ms

guard time before it is used again. Thisrequirement is valid for all modes of operation. Theneed for power down guard time can vary withcrystal type and load.

(1) Including aging and temperature dependency, as specified by [1](2) Simulated over operating conditions


PARAMETER TEST CONDITIONS MIN TYP MAX UNITCrystal frequency 32.768 kHzCrystal frequency accuracy –40 40 ppmrequirement (1)

ESR Equivalent series resistance (2) 40 ΩC0

(2) 0.9 pFCL

(2) 12 pFStart-up time (3) 400 ms

(1) Including aging and temperature dependency, as specified by [1](2) Simulated over operating conditions(3) Value is simulated.


PARAMETER TEST CONDITIONS MIN TYP MAX UNITCalibrated frequency (1) 32.753 kHzFrequency accuracy after calibration ±0.2 (2) %Temperature coefficient (3) 0.4 (2) %/°CSupply-voltage coefficient (4) 3 (2) %/VInitial calibration time (5) 1.7 ms

(1) The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.(2) Value is estimated.(3) Frequency drift when temperature changes after calibration.(4) Frequency drift when supply voltage changes after calibration.(5) When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator

is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.












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16-MHz RC OSCILLATOR

RSSI/CCA CHARACTERISTICS

FREQEST CHARACTERISTICS

FREQUENCY SYNTHESIZER CHARACTERISTICS

ANALOG TEMPERATURE SENSOR

CC2530F32, CC2530F64, CC2530F128, CC2530F256



PARAMETER TEST CONDITIONS MIN TYP MAX UNITFrequency (1) 16 MHzUncalibrated frequency accuracy ±18 %Calibrated frequency accuracy ±0.6 ±1 %Start-up time 10 µsTemperature coefficient (2) –325 ppm/°CSupply voltage coefficient (3) 28 ppm/mVInitial calibration time (4) 50 µs

(1) The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.(2) Frequency drift when temperature changes after calibration.(3) Frequency drift when supply voltage changes after calibration.(4) When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator

is performed while SLEEPCMD.OSC_PD is set to 0.


PARAMETER TEST CONDITIONS MIN TYP MAX UNITRSSI Range 100 dBRSSI/CCA Accuracy +/-4 dBRSSI/CCA Offset (1) 76 dBStep size (LSB value) 1 dB

(1) Real RSSI = Register value - offset


PARAMETER TEST CONDITIONS MIN TYP MAX UNITFREQEST Range +/-300 kHzFREQEST Accuracy +/-10 kHzFREQEST Offset (1) 64 kHzStep size (LSB value) 7.8 kHz

(1) Real FREQEST = Register value - offset

Measured on Texas Instruments CC2530 EM reference design with TA = 25°C, VDD = 3 V and Fc = 2440 MHz, unlessotherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITAt ±1-MHz offset from carrier -110 dBc/Hz

Phase noise, unmodulated At ±3-MHz offset from carrier -118carrierAt ±5-MHz offset from carrier -128


PARAMETER TEST CONDITIONS MIN TYP MAX UNITOutput voltage at 25°C 0.8 VTemperature coefficient 25 mV/10°CVoltage coefficient 6 mV/VAcuracy without calibration At fixed voltage +/-12 °C












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ADC CHARACTERISTICS

CC2530F32, CC2530F64, CC2530F128, CC2530F256


ANALOG TEMPERATURE SENSOR (continued)Measured on Texas Instruments CC2530 EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITAccuracy using 1-point At fixed voltage +/-1 °CcalibrationCurrent consumption when 280 µAenabled

TA = 25°C and VDD = 3 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITInput voltage VDD is voltage on AVDD_SOC pin 0 VDD VExternal reference voltage VDD is voltage on AVDD_SOC pin 0 VDD VExternal reference voltage differential VDD is voltage on AVDD_SOC pin 0 VDD VInput resistance, signal Simulated using 4-MHz clock speed 197 kΩFull-scale signal (1) Peak-to-peak, defines 0 dBFS 2.97 V

Single-ended input, 7-bit setting 5.7 bitsSingle-ended input, 9-bit setting 7.5

ENOB (1) Effective number of bits Single-ended input, 10-bit setting 9.3Single-ended input, 12-bit setting 10.3Differential input, 7-bit setting 6.5Differential input, 9-bit setting 8.3Differential input, 10-bit setting 10Differential input, 12-bit setting 11.5

Useful power bandwidth 7-bit setting, both single and differential 0–20 kHzSingle ended input, 12-bit setting, –6 –75.2 dBdBFSTHD (1) Total harmonic distortionDifferential input, 12-bit setting, –6 dBFS –86.6Single-ended input, 12-bit setting 70.2 dBDifferential input, 12-bit setting 79.3

Signal to nonharmonic ratio (1) Single-ended input, 12-bit setting, –6 78.8dBFSDifferential input, 12-bit setting, –6 dBFS 88.9

CMRR Common-mode rejection ratio Differential input, 12-bit setting, 1-kHz ≤84 dBsine (0 dBFS), limited by ADC resolution

Crosstalk Single ended input, 12-bit setting, 1-kHz ≤84 dBsine (0 dBFS), limited by ADC resolution

Offset Midscale –3 mVGain error 0.68 %

12-bit setting, mean 0.05 LSBDNL (1) Differential nonlinearity

12-bit setting, maximum 0.912-bit setting, mean 4.5 LSB

INL (1) Integral nonlinearity12-bit setting, maximum 13.3

(1) Measured with 300-Hz sine-wave input and VDD as reference.












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CONTROL INPUT AC CHARACTERISTICS

RESET_N

Px.n

Px.n

1

2

2

T0299-01

CC2530F32, CC2530F64, CC2530F128, CC2530F256


ADC CHARACTERISTICS (continued)TA = 25°C and VDD = 3 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITSingle ended input, 7-bit setting 35.4 dBSingle ended input, 9-bit setting 46.8Single ended input, 10-bit setting 57.5Single ended input, 12-bit setting 66.6SINAD (1)

Signal-to-noise-and-distortion(–THD+N) Differential input, 7-bit setting 40.7Differential input, 9-bit setting 51.6Differential input, 10-bit setting 61.8Differential input, 12-bit setting 70.87-bit setting 20 µs9-bit setting 36

Conversion time10-bit setting 6812-bit setting 132

Power consumption 1.2 mA

TA = –40°C to 125°C, VDD = 2 V to 3.6 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITSystem clock, fSYSCLK System clock is 32 MHz when crystal oscillator is used. System clock 16 32 MHzis 16 MHz when calibrated 16-MHz RC oscillator is used.tSYSCLK = 1/ fSYSCLK

See item 1, Figure 1. This is the shortest pulse that is specifieded tobe recognized as a complete reset pin request. Note that shorterRESET_N low duration 1 uspulses may be recognized but do not lead to complete reset of allmodules within the chip.See item 2, Figure 1.This is the shortest pulse that is specified to berecognized as an interrupt request. In PM2/3, the internal 1.5 ×Interrupt pulse duration nssynchronizers are bypassed, so this requirement does not apply in tSYSCLKPM2/3.

Figure 1. Control Input AC Characteristics












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SPI AC CHARACTERISTICS

SCK

4

SSN

1

5

2

T0300-01

MISO/MOSI

MOSI/MISO

3

6

CC2530F32, CC2530F64, CC2530F128, CC2530F256



PARAMETER TEST CONDITIONS MIN TYP MAX UNITSCK period Master, See item 1 Figure 2 125 nsSCK duty cycle Master 50 %SSN low to SCK See item 5, Figure 2 2 × tSYSCLK

SCK to SSN high See item 6, Figure 2 30 nsMISO setup Master. See item 2, Figure 2 10 nsMISO hold Master. See item 3, Figure 2 10 nsSCK to MOSI Master. See item 4, Figure 2, load = 10 pF 25 nsSCK period Slave. See item 1, Figure 2 100 nsSCK duty cycle Slave 50 %MOSI setup Slave. See item 2, Figure 2 10 nsMOSI hold Slave. See item 3, Figure 2 10 nsSCK to MISO Slave. See item 4, Figure 2, load = 10 pF 25 ns

Figure 2. SPI AC Characteristics












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DEBUG INTERFACE AC CHARACTERISTICS

4

RESET_N

1

T0301-01

2

3

5

DEBUG CLKP2_2

DEBUG DATAP2_1

DEBUG DATAP2_1

TIMER INPUTS AC CHARACTERISTICS

CC2530F32, CC2530F64, CC2530F128, CC2530F256



PARAMETER TEST CONDITIONS MIN TYP MAX UNITDebug clock period See item 1 Figure 3 125 nsDebug data setup See item 2 Figure 3 5 nsDebug data hold See item 3 Figure 3 5 nsClock-to-data delay See item 4 Figure 3, load = 10 pF 10 nsRESET_N inactive after P2_2 rising See item 5 Figure 3 10 ns

Figure 3. Debug Interface AC Characteristics


PARAMETER TEST CONDITIONS MIN TYP MAX UNITInput capture pulse duration Synchronizers determine the shortest input pulse that can be 1.5 × ns

recognized. The synchronizers operate at the current system tSYSCLKclock rate (16 or 32 MHz).












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DC CHARACTERISTICS

TYPICAL PERFORMANCE TABLES AND CURVES

DEVICE INFORMATION

PIN DESCRIPTIONS

CC2530F32, CC2530F64, CC2530F128, CC2530F256


TA = 25°C, VDD = 3 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITLogic-0 input voltage 0.5 VLogic-1 input voltage VDD – 0.5 VLogic-0 input current Input equals 0 V NA –1 µALogic-1 input current Input equals VDD NA 1 µAI/O-pin pullup and pulldown resistors 20 kΩLogic-0 output voltage, 4- mA pins Output load 4 mA 0.5 VLogic-1 output voltage, 4-mA pins Output load 4 mA VDD-20% VLogic-0 output voltage, 20-mA pins Output load 20 mA 0.5 VLogic-1 output voltage, 20-mA pins Output load 20 mA VDD-20% V

Measured on Texas Instruments CC2530 EM reference design with TA = 25°C, VDD = 3 V and Fc = 2440 MHz, unlessotherwise noted.

TXPOWER Register Setting Typical Output Power (dBm) Typical Current Consumption (mA)0xF5 4 33.80xE5 2 30.50xD5 0 29.10xC5 -1 28.40xB5 -3 27.50xA5 -4 27.00x95 -6 26.00x85 -7 25.70x75 -9 25.40x65 -11 25.10x55 -13 24.90x45 -15 24.70x35 -17 24.60x25 -19 24.50x15 -21 24.50x05 -23 23.3

0x05 and TXCTRL = 0x09 -28 23.2

The CC2530 pinout is shown in Figure 4 and a short description of the pins follows.












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CC2530RHA Package

(Top View)

P0

_1

RE

SE

T_

N

P2

_3/X

OS

C3

2K

_Q

2

AV

DD

6

GND RBIAS301

292

283

274

265

256

24

22

7

9

23

21

8

1018 20

33 31

17 19

34 32

16

35

15

36

14

37

13

38

12

39

11

40

P0

_2

P0

_0

AVDD4

P0_

3

AVDD1

P0

_4

AVDD2

P0_

5RF_N

P0_

6

RF_P

P0_

7

AVDD3

XOSC_Q1

P1_

0

XOSC_Q2

AVDD5

GNDGround Pad

P2

_2

P2

_4/X

OS

C3

2K

_Q

1

GND

P2

_1

GND

P2

_0

GND

P1

_7

P1_5

P1

_6

P1_4

DV

DD

1

P1_3

P1_1

DC

OU

PL

P1_2

DVDD2

P0076-02

CC2530F32, CC2530F64, CC2530F128, CC2530F256


NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.

Figure 4. Pinout Top View

Pin DescriptionsPIN NAME PIN PIN TYPE DESCRIPTION

AVDD1 28 Power (analog) 2-V–3.6-V analog power-supply connectionAVDD2 27 Power (analog) 2-V–3.6-V analog power-supply connectionAVDD3 24 Power (analog) 2-V–3.6-V analog power-supply connectionAVDD4 29 Power (analog) 2-V–3.6-V analog power-supply connectionAVDD5 21 Power (analog) 2-V–3.6-V analog power-supply connectionAVDD6 31 Power (analog) 2-V–3.6-V analog power-supply connectionDCOUPL 40 Power (digital) 1.8-V digital power-supply decoupling. Do not use for supplying external circuits.DVDD1 39 Power (digital) 2-V–3.6-V digital power-supply connectionDVDD2 10 Power (digital) 2-V–3.6-V digital power-supply connectionGND — Ground The ground pad must be connected to a solid ground plane.GND 1, 2, Unused pins Connect to GND

3, 4P0_0 19 Digital I/O Port 0.0P0_1 18 Digital I/O Port 0.1P0_2 17 Digital I/O Port 0.2P0_3 16 Digital I/O Port 0.3P0_4 15 Digital I/O Port 0.4












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CC2530F32, CC2530F64, CC2530F128, CC2530F256


Pin Descriptions (continued)PIN NAME PIN PIN TYPE DESCRIPTION

P0_5 14 Digital I/O Port 0.5P0_6 13 Digital I/O Port 0.6P0_7 12 Digital I/O Port 0.7P1_0 11 Digital I/O Port 1.0 – 20-mA drive capabilityP1_1 9 Digital I/O Port 1.1 – 20-mA drive capabilityP1_2 8 Digital I/O Port 1.2P1_3 7 Digital I/O Port 1.3P1_4 6 Digital I/O Port 1.4P1_5 5 Digital I/O Port 1.5P1_6 38 Digital I/O Port 1.6P1_7 37 Digital I/O Port 1.7P2_0 36 Digital I/O Port 2.0P2_1 35 Digital I/O Port 2.1P2_2 34 Digital I/O Port 2.2P2_3/ 33 Digital I/O, Port 2.3/32.768 kHz XOSCXOSC32K_Q2 Analog I/OP2_4/ 32 Digital I/O, Port 2.4/32.768 kHz XOSCXOSC32K_Q1 Analog I/ORBIAS 30 Analog I/O External precision bias resistor for reference currentRESET_N 20 Digital input Reset, active-lowRF_N 26 RF I/O Negative RF input signal to LNA during RX

Negative RF output signal from PA during TXRF_P 25 RF I/O Positive RF input signal to LNA during RX

Positive RF output signal from PA during TXXOSC_Q1 22 Analog I/O 32-MHz crystal oscillator pin 1 or external-clock inputXOSC_Q2 23 Analog I/O 32-MHz crystal oscillator pin 2












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CIRCUIT DESCRIPTION

RESETWATCHDOG

TIMER

IRQ CTRL FLASH CTRL

DEBUGINTERFACE

CLOCK MUXand

CALIBRATION

DMA

8051 CPUCORE

32-MHz

CRYSTAL OSC

32.768-kHz

CRYSTAL OSC

HIGH-

SPEED

RC-OSCPOWER MANAGEMENT CONTROLLER

USART 0

USART 1

TIMER 1 (16-Bit)

TIMER 3 (8-Bit)

TIMER 4 (8-Bit)

TIMER 2(IEEE 802.15.4 MAC TIMER)

32/64/128/256-KBFLASH

8-KB SRAM

ON-CHIP VOLTAGE

REGULATOR

POWER ON RESET

BROWN OUT

VDD (2 V–3.6 V)

DCOUPLRESET_N

XOSC_Q2

XOSC_Q1

P2_4

P1_7

P0_7

P2_3

P1_6

P0_6

P2_2

P1_5

P0_5

P1_2

P0_2

P2_1

P1_4

P0_4

P1_1

P0_1

P2_0

P1_3

P0_3

P1_0

P0_0

MODULATORDEMODULATOR

RECEIVE

CHAIN

TRANSMIT

CHAIN

FR

EQ

UE

NC

Y

SY

NT

HE

SIZ

ER

SY

NT

H

AGC

RF_P RF_NB0301-02

RADIO DATA INTERFACE

CSMA/CA STROBE PROCESSOR

RADIO REGISTERS

FIF

O a

nd

FR

AM

E C

ON

TR

OL

SF

R B

us

SF

R B

us

ADC

AUDIO/DC

AESENCRYPTION

ANDDECRYPTION

MEMORYARBITRATOR

FLASH

RAM

UNIFIED

SFR

IRAM

XRAM

PDATA

SLEEP TIMER

32-kHz

RC-OSC

I/O

CO

NT

RO

LL

ER

DIGITAL

ANALOG

MIXED

CC2530F32, CC2530F64, CC2530F128, CC2530F256


Figure 5. CC2530 Block Diagram












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CPU and Memory

Peripherals

CC2530F32, CC2530F64, CC2530F128, CC2530F256


A block diagram of the CC2530 is shown in Figure 5. The modules can be roughly divided into one of threecategories: CPU-related modules; modules related to power, test, and clock distribution; and radio-relatedmodules. In the following subsections, a short description of each module that appears in Figure 5 is given.

The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access buses (SFR,DATA and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit. See User Guide for detailson the CPU.

The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physicalmemories and all peripherals through the SFR bus. The memory arbiter has four memory access points, accessof which can map to one of three physical memories: an 8-KB SRAM, flash memory, and XREG/SFR registers. Itis responsible for performing arbitration and sequencing between simultaneous memory accesses to the samephysical memory.

The SFR bus is drawn conceptually in Figure 5 as a common bus that connects all hardware peripherals to thememory arbitrator. The SFR bus in the block diagram also provides access to the radio registers in the radioregister bank, even though these are indeed mapped into XDATA memory space.

The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The 8-KBSRAM is an ultralow-power SRAM that retains its contents even when the digital part is powered off (powermodes 2 and 3).

The 32/64/128/256 KB flash block provides in-circuit programmable non-volatile program memory for thedevice, and maps into the CODE and XDATA memory spaces.

Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewiseprogramming. See User Guide for details on the flash controller.

A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memoryspace, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressingmode, source and destination pointers, and transfer count) is configured with DMA descriptors anywhere inmemory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers, ADC interface) rely onthe DMA controller for efficient operation by performing data transfers between a single SFR or XREG addressand flash/SRAM. See User Guide for details.

The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of whichis associated with one of four interrupt priorities. An interrupt request is serviced even if the device is in a sleepmode (power modes 1–3) by bringing the CC2530 back to the active mode (power mode 0).

The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.Through this debug interface, it is possible to perform an erasure of the entire flash memory, control whichoscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it ispossible to perform in-circuit debugging and external flash programming elegantly. See User Guide for details.

The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheralmodules control certain pins or whether they are under software control, and if so, whether each pin is configuredas an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connectsto the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications. SeeUser Guide for details.

The sleep timer is an ultralow-power timer that counts 32.768-kHz crystal oscillator or 32-kHz RC oscillatorperiods. The sleep timer runs continuously in all operating modes except power mode 3. Typical applications ofthis timer are as a real-time counter or as a wake-up timer to get out of power mode 1 or 2. See User Guide fordetails.

A built-in watchdog timer allows the CC2530 to reset itself in case the firmware hangs. When enabled bysoftware, the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out. SeeUser Guide for details.












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Radio

TYPICAL CHARACTERISTICS

CC2530F32, CC2530F64, CC2530F128, CC2530F256


Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit periodvalue, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each ofthe counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. Itcan also be configured in IR Generation Mode where it counts Timer3 periods and the output is and'ed with theoutput of Timer3 to generate modulated consumer IR signals with minimal CPU interaction. See User Guide fordetails.

The MAC timer (timer 2) is specially designed for supporting an IEEE 802.15.4 MAC or other time-slottedprotocol in software. The timer has a configurable timer period and an 8-bit overflow counter that can be used tokeep track of the number of periods that have transpired. A 16-bit capture register is also used to record theexact time at which a start-of-frame delimiter is received/transmitted or the exact time at which transmissionends, as well as a 16-bit output compare register that can produce various command strobes (start RX, start TX,etc.) at specific times to the radio modules. See User Guide for details.

Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counterchannels can be used as a PWM output. See User Guide for details.

USART 0 and USART 1 are each configurable as either a SPI master/slave or a UART. They provide doublebuffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplexapplications. Each has its own high-precision baud-rate generator, thus leaving the ordinary timers free for otheruses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly instead of usingsome oversampling scheme, and are thus well-suited to high data rates. See User Guide for details.

The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with128-bit keys. The core is able to support the AES operations required by IEEE 802.15.4 MAC security, theZigBee network layer, and the application layer. See User Guide for details.

The ADC supports 7 to 12 bits of resolution in a 30-kHz to 4-kHz bandwidth, respectively. DC and audioconversions with up to eight input channels (port 0) are possible. The inputs can be selected as single-ended ordifferential. The reference voltage can be internal, AVDD, or a single-ended or differential external signal. TheADC also has a temperature-sensor input channel. The ADC can automate the process of periodic sampling orconversion over a sequence of channels. See User Guide for details.

The CC2530 features an IEEE 802.15.4-compliant radio tranceiver. See User Guide for details.












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APPLICATION INFORMATION

Few external components are required for the operation of the CC2530. A typical application circuit is shown in

R301

C251

C261

C262

C252

C253

L252

L261

XTAL1

C221 C231

XTA

L2

C321

C331

C401

Optional 32-kHz Crystal

1 GND

2 GND

3 GND

4 GND

5 P1_5CC2530

DIE ATTACH PAD

10 DVDD2

9 P1_1

8 P1_2

7 P1_3

6 P1_4

RBIAS 30

AVDD4 29

AVDD1 28

AVDD2 27

RF_N 26

AVDD5 21

XOSC_Q1 22

XOSC_Q2 23

AVDD3 24

RF_P 25

11

P1

_0

12

P0

_7

13

P0

_6

14

P0

_5

15

P0

_4

20

RE

SE

T_

N

19

P0

_0

18

P0

_1

17

P0

_2

16

P0

_3

DC

OU

PL

40

DV

DD

139

P1_

63

8

P1_

73

7

P2_

03

6

AV

DD

631

P2

_4

/XO

SC

32K

_Q

13

2

P2

_3

/XO

SC

32K

_Q

23

3

P2_

23

4

P2_

13

5

2-V to 3.6-VPower Supply

Power Supply Decoupling Capacitors are Not ShownDigital I/O Not Connected

Antenna

(50 )W

S0383-01

CC2530F32, CC2530F64, CC2530F128, CC2530F256


Figure 6. Typical values and description of external components are shown in Table 1.

Figure 6. CC2530 Application Circuit

Table 1. Overview of External Components (Excluding Supply Decoupling Capacitors)Component Description Value

C251 Part of the RF matching network 18pFC261 Part of the RF matching network 18pFL252 Part of the RF matching network 2.0nHL261 Part of the RF matching network 2.0nHC262 Part of the RF matching network 1.0pFC252 Part of the RF matching network 1.0pFC253 Part of the RF matching network 2.2pFC331 32kHz xtal loading capacitor 15pFC321 32kHz xtal loading capacitor 15pFC231 32MHz xtal loading capacitor 27pFC221 32MHz xtal loading capacitor 27pFC401 Decoupling capacitor for the internal digital regulator 1uF












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Input/Output Matching

Crystal

L parasitic

221 231

1C C

1 1

C C

= +

+

(1)

L parasitic

321 331

1C C

1 1

C C

= +

+

(2)

On-chip 1.8V Voltage Regulator Decoupling

Power-Supply Decoupling and Filtering

References

Low-Power RF Online Community

CC2530F32, CC2530F64, CC2530F128, CC2530F256


Table 1. Overview of External Components (Excluding Supply Decoupling Capacitors) (continued)Component Description Value

R301 Resistor used for internal biasing 56kΩ

When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. Thebalun can be implemented using low-cost discrete inductors and capacitors. The recommended balun shownconsists of C262, L261, C252 and L252.

If a balanced antenna such as a folded dipole is used, the balun can be omitted.

An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystaloscillator. See Section 7 for details. The load capacitance seen by the 32-MHz crystal is given by:

XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHzcrystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-currentconsumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal isgiven by:

A series resistor may be used to comply with the ESR requirement.

The 1.8V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor(C401) for stable operation.

Proper power-supply decoupling must be used for optimum performance. The placement and size of thedecoupling capacitors and the power supply filtering are very important to achieve the best performance in anapplication. TI provides a compact reference design that should be followed very closely.

1. CC253X User Guide

SWRU1912. IEEE Std. 802.15.4-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications

for Low-Rate Wireless Personal Area Networks (LR-WPANs)

http://standards.ieee.org/getieee802/download/802.15.4-2006.pdf3. NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal Information Processing Standards

Publication 197, US Department of Commerce/N.I.S.T., November 26, 2001. Available from the NISTwebsite.

http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

• Forums, videos, and blogs• RF design help







http://www-s.ti.com/sc/techlit/SWRU191

http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf

http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf






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CC2530F32, CC2530F64, CC2530F128, CC2530F256


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PACKAGING INFORMATION

Orderable Device Status (1) PackageType

PackageDrawing

Pins PackageQty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

CC2530F128RHAR PREVIEW QFN RHA 40 2500 TBD Call TI Call TI

CC2530F128RHAT PREVIEW QFN RHA 40 250 TBD Call TI Call TI






(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 6-Apr-2009

Addendum-Page 1

http://www.ti.com/productcontent

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Documents

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