CBM at FAIR Walter F.J. Müller, GSI, Darmstadt XXXVI. Treffen "Kernphysik", Schleching/Obb., 17-24 February 2005 Vortrag zum Thema: Hochleistungsdatenverarbeitung in der Kern- und Teilchenphysik New challenges for Front-End Electronics, Data Acquisition and Trigger Systems
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CBM at FAIR Walter F.J. Müller, GSI, Darmstadt XXXVI. Treffen "Kernphysik", Schleching/Obb., 17-24 February 2005 Vortrag zum Thema: Hochleistungsdatenverarbeitung.
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CBM at FAIR
Walter F.J. Müller, GSI, Darmstadt
XXXVI. Treffen "Kernphysik", Schleching/Obb., 17-24 February 2005
Vortrag zum Thema: Hochleistungsdatenverarbeitung in der
Kern- und Teilchenphysik
New challenges for Front-End Electronics, Data Acquisition and Trigger Systems
17-24 February 2005
XXXVI. Treffen Kernphysik, Schleching/Obb., Walter F.J. Müller, GSI
Processing resources forfirst level event selectionstructured in small farms
Connection to'high level'
selection processing
17-24 February 2005
XXXVI. Treffen Kernphysik, Schleching/Obb., Walter F.J. Müller, GSI
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Bandwidth Requirements
Data flow:
~ 1 TB/sec
1st level selection:
~ 1014-15 operation/sec
Data flow:
few 10 GB/sec
to archive: few 1 GB/sec
Moore helps
Gilder helps
17-24 February 2005
XXXVI. Treffen Kernphysik, Schleching/Obb., Walter F.J. Müller, GSI
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L1 Event Selection Farm Layout
Current working hypothesis: CPU + FPGA hybrid system (proviso follows)
Use programmable logic for cores of algorithms Use CPU for the non-parallelizable parts Use serial connection fabric (links and switches) Modular design (only few board types)
17-24 February 2005
XXXVI. Treffen Kernphysik, Schleching/Obb., Walter F.J. Müller, GSI
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FPGA – Basic Building Block
CLK
F3
F2
F1
F0XQ
X
D
C
Q
LUT
CLB
Look-up Tablejust a 4x1 RAM
D Flip-FlopUniversallogic gate
Elementarystorage unit
CLB = Configurable Logic Block
17-24 February 2005
XXXVI. Treffen Kernphysik, Schleching/Obb., Walter F.J. Müller, GSI
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FPGA – Putting it together
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
PSM
PSM
PSM
PSM
PSM
PSM
PSM
PSM
PSM
ConfigurableLogic Block
Wiring
Programmableswitch matrix
I/O blocks
Modern FPGA's:>100.000 LUT 500 MHz
17-24 February 2005
XXXVI. Treffen Kernphysik, Schleching/Obb., Walter F.J. Müller, GSI
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Algorithms
Performance of L1 feature extraction algorithms is essential critical in CBM: STS tracking + vertex reconstruction
TRD tracking and Pid
Look for algorithms which allow massive parallel implementation e.g. Hough Transform Tracker
needs lots of bit level operations, well suited for FPGA Caveat: simulation on normal CPU quite time consuming....
Co-develop tracking detectors and analysis algorithms L1 tracking is necessarily speed optimized
→ more detector granularity and redundancy needed Aim for CBM:
Validate final hardware design with at least 2 trackers suitable for L1
17-24 February 2005
XXXVI. Treffen Kernphysik, Schleching/Obb., Walter F.J. Müller, GSI
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Interim Summary Event definition has changed:
now based on time stamps and time correlation
Role of DAQ has changed: DAQ is simply responsible to transport data from producers to consumers
Role of 'Trigger' has changed: filter events delivered by DAQ 'Online Event Selection' is better term
System aspects: 'online' – 'offline' boundary blurs more COTS (commercial off the shelf) components much more modular system much more adaptable system
This is emerging technology in HEP, though baseline for ILCHowever: being used since many years in nuclear structure
17-24 February 2005
XXXVI. Treffen Kernphysik, Schleching/Obb., Walter F.J. Müller, GSI
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Moore – quo vadis ?
Will price/performance of computing continue to improve ? What are limits of CMOS technology ? Where are the markets ? What are market forces ?
Technology most of the gain comes from architecture anyway conventional designs, especially x86, reach their limits
Markets end of the metal-box PC age
→ Laptops + PDA + all kind of dedicated boxes (Video, Games) end of the binary compatibility age
→ intermediate code + 'Just in Time' Compilers (JIT)
There is life after Intel x86A lot of architectural innovation ahead
17-24 February 2005
XXXVI. Treffen Kernphysik, Schleching/Obb., Walter F.J. Müller, GSI
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BlueGene vs Cell Processor
CPU
Cache
Mem
Mem
IO
IO
Mem SPEMemSPE
Mem SPEMemSPE
Mem SPEMemSPE
Mem SPEMemSPE
CPU CPU
Cache Cache
IO IO IO IO
Mem
BlueGene:121 mm2; 130 nm2.8/5.6 DP GFlop STI Cell:
Russia:CKBM, St. PetersburgIHEP ProtvinoINR TroitzkITEP MoscowKRI, St. PetersburgKurchatov Inst., MoscowLHE, JINR DubnaLPP, JINR DubnaLIT, JINR DubnaLTP, JINR DubnaMEPhi, MoskauObninsk State Univ.PNPI GatchinaSINP, Moscow State Univ. St. Petersburg Polytec. U.