CBM at FAIR Walter F.J. Müller, GSI, Darmstadt for the CBM collaboration 5 th International Conference on Physics and Astrophysics of Quark Gluon Plasma, Kolkata, India, 8-12 February 2005 New challenges for Front-End Electronics, Data Acquisition and Trigger Systems
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CBM at FAIR Walter F.J. Müller, GSI, Darmstadt for the CBM collaboration 5 th International Conference on Physics and Astrophysics of Quark Gluon Plasma,
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CBM at FAIR
Walter F.J. Müller, GSI, Darmstadtfor the CBM collaboration
5th International Conference on Physics andAstrophysics of Quark Gluon Plasma,
Kolkata, India, 8-12 February 2005
New challenges for Front-End Electronics, Data Acquisition and Trigger Systems
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 2
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 10
CBM DAQ Requirements Profile
D and J/Ψ signal drives the rate capability requirements D signal drives FEE and DAQ/Trigger requirements
Problem similar to B detection, see BTeV, LHCb Adopted approach:
displaced vertex 'trigger' in first level, like in BTeV Additional Problem:
DC beam → interactions at random times
→ time stamps with ns precision needed
→ explicit event association needed Current design for FEE and DAQ/Trigger:
Self-triggered FEE Data-push architecture
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 11
Conventional FEE-DAQ-Trigger Layout Detector
Cave
Shack
FEE
Buffer
L2 Trigger L1 Trigger
DAQ
L1 A
ccep
t
L0 Trigger
fbunch
Archive
Trigger
Primitives
Especially
instrumented
detectors
Dedicated
connections
Specialized
trigger
hardware
Limited
capacity
Limited
L1 trigger
latency
Modest
bandwidth
Standard
hardware
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 12
Limits of Conventional Architecture
Decision time for first
level trigger limited.
typ. max. latency 4 μs for LHC
Only especially instrumented
detectors can contribute to
first level trigger
Large variety of very
specific trigger hardware
Not suitable for complex
global triggers like secondary
vertex search
Limits future trigger
development
High development cost
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 13
L1 Trigger
Special
hardware
High
bandwidth
The way out .. use Data Push ArchitectureDetector
Cave
Shack
FEE
Buffer
L2 Trigger L1 Trigger
DAQ
L1 A
ccep
t
L0 Trigger
fbunch
Archive
Trigger
Primitives
Especially
instrumented
detectors
Dedicated
connections
Specialized
trigger
hardware
Limited
capacity
Limited
L1 trigger
latency
Modest
bandwidth
Standard
hardware
fclock
L2 Trigger
Timedistribution
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 14
L1 Trigger
Special
hardware
High
bandwidth
The way out ... use Data Push ArchitectureDetector
Cave
Shack
FEE
DAQ
Archive
fclock
L2 Trigger
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 15
L1 Select
Special
hardware
High
bandwidth
The way out ... use Data Push Architecture Detector
Cave
Shack
FEE
DAQ
Archive
fclock
L2 Select
Self-triggered front-end
Autonomous hit detection
No dedicated trigger connectivity
All detectors can contribute to L1
Large buffer depth available
System is throughput-limited
and not latency-limitedModular design:
Few multi-purpose rather
many special-purpose
modules
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 16
Toward Multi-Purpose FEE Chain
PreAmpPreAmp preFilter
preFilter ADCADC Hit
Finder
Hit
Finderdigital
Filter
digital
FilterBackend
& Driver
Backend
& Driver
Pad GEM's PMT APD's
Anti-Aliasing
Filter
Sample rate:
10-100 MHz
Dyn. range:
8...12 bit
'Shaping'
1/t Tailcancellation
Baselinerestorer
Hit
parameter
estimators:
Amplitude
Time
Clustering
Buffering
Link protocol
All potentially in one mixed-signal chip
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 17
CBM DAQ and Online Event Selection
Data flow:
~ 1 TB/sec
1st level selection:
~ 1015 operation/sec
Data flow:
few 10 GB/sec
to archive: few 1 GB/sec
Moore helps
Gilder helps
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 18
L1 Event Selection Farm Layout
Use programmable logic for cores of algorithms Use high-speed SoC processors (look beyond PC's) Use serial connection fabric (links and switches) Modular design (only few board types)
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 19
CPU and FPGA: Destined to Merge Example Stretch S5xxx
at first glance looks like yetanother CPU with a SIMD extension, like MMX
The innovation: configurable instruction set compiler generates new instructions
and the code which uses them
8-12 February 2005 ICPAQGP-05, Kolkata, Walter F.J. Müller, GSI 20
CBM FEE/DAQ Summary
Self-triggered FEE: autonomous hit detection, time-stamping with ns presision sparsification, hit buffering, high output bandwidth
High bandwidth event building network to cope with few 100 MHz interaction rate in p-p, p-A likely be done in time slices or event slices
L1 processor farm feasible with PC + FPGA + Moore (needed 2014) but look beyond todays PC's
Efficient algorithms (109 tracks/sec)
Quitedifferentfrom thecurrent
LHC styleelectronics
Substantial R&D
needed
Part of an EU FP6 project, togetherwith PANDAand COMPASS
Russia:CKBM, St. PetersburgIHEP ProtvinoINR TroitzkITEP MoscowKRI, St. PetersburgKurchatov Inst., MoscowLHE, JINR DubnaLPP, JINR DubnaLIT, JINR DubnaLTP, JINR DubnaMEPhi, MoskauObninsk State Univ.PNPI GatchinaSINP, Moscow State Univ. St. Petersburg Polytec. U.