CATS And The M3-DSP - TU DresdenCATS And The M3-DSP 5/6/99(5/5/99) CATS And The M3-DSP Frank Engel Mannesmann Mobilfunk Chair For Mobile Communications Systems Dresden

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SP

1 of 27CATS And The M3-DSP

CATS And The M3-DFrank Engel

Mannesmann Mobilfunk Chair ForMobile Communications Systems

Dresden University Of Technology

D-01062 Dresden

[email protected]

Mannesmann Mobilfunk Chair forMobile Communications Systems

<jork.fm> 5/6/99(5/5/99)


DresdenUniversi ty ofTechnology

Talk

- Motivation

- CATS

- M3-DSP


<jork.fm> 5/6/99(5/5/99)



Motivation


<jork.fm> 5/6/99(5/5/99)



Motivation

DSP: A Key Component

- Historic: Stand-alone DSP-IC

- Current: Embedded DSP

- Future: Macro cell DSP

=> Communications is the DSP technology driver

=> Embedded DSPs are becoming mainstream


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etitive advantage



Motivation

Achieving a Competitive Advantage

- DSPs are evolving further, by

• semiconductor technology developments: hardly any comp

• architecture developments: competitive advantage

- DSP market evolution:

• high growth

• innovation: fast generation cycles (speeding up)

=> Architecture development is becoming the key


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tion



Motivation

How to Get Ahold of The Technology?

- typical money maker ICs: competitive advantage

• power consumption

• die size/cost

• performance

• package, I/O, chip-set integration

=> architecture-application optimization

- licensing strategy

• licence architecture & software

=> competitive edge?

The licensing dilemma:

=> Licensing fixed DSP cores is no long-term solu

=> Architecture development is becoming the key


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Motivation

What Kind of DSP Are Needed?

- General Purpose DSP

• available solution

• generally applicable

• large software base

- Domain Specific DSP

• available solution allows for faster design cycle

• market volume allows for specialized solution

• specialized solution to gain market advantage

• small software base

- Application Specific DSP

• high-end application requires custom solution

• market volume allows for custom solution

• custom architecture/solution yields key market advantage

• time-to-market allows for long design cycle


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Motivation

Interim Summary

- DSP architecture is key to DSP technology

- licensing fixed DSP cores is no long-term solution

- communications is the DSP technology driver

- DSP technology is not one core only


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rocessors



CATS:Concept for Application Tailored Signal P


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are

P

Graphics

P ?...



CATS: Concept for Application Tailored Signal Processors

Problem: The Software & Hardware Nightm

=> Need: Integrated System

Processor Design

Software Design

Modem Speech Protocol Image

PPPP

SW

HW


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gonalization

t

t

DataProcessingClasses




ISA: Data Processing Classes

- Integrated ISA

- Generic software tools

=> Dataflow/arithmetic operation partitioning/ortho

yk ai xk i–i

∑=

yk maxi ai xk i–+( )=

yk ai xk i––i

∑=

RISC oc func src1 src2 des

oc func immediate

oc func src1 des


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User-Interface

HW-Interface




Processor Architecture

. . .DataPath

DataPath

DataPath

DataPath

I/O&Cntrl.

DataDataMem

ProgMem

Prog

‘GPP’

Bus

constant: conceptvariable

CntrlMemMgmt

Programming-Tools


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SWtestlibrary

SWtools

proto-type

SW

verif.&




Concept: The DSP Design Assistent

algorithm

Cossap

HW genericDSPlibrary

DSPdesigner

requirements- memory- data Processing Classes- operations


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Processor Synthesis Advantages

- One software design environment

- Software libraries

- Maintenance (HW & SW)

- Fast evaluation board turn-around

- Fast design turn-around

- Upgrades instead of redesigns


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M3-DSP:Multi Media Modem


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ISA

ode



M3-DSP: Multi Media Modem

Signal Processing

- M3: high parallel processor structure

• 16 identical datapth: DP

• memory bandwidth: 16x datawitdth -> group memory

• program control unit: PCU

• address generation unit: AGU

• block float unit (floating point on fixed point): BFU

=> Problem: Code size explosion on sequential c

FIW FIW FIW FIW...

AGU PCU DP BMU...

VLIW: Very Long Instruction Word


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ISA: TVLIW

W

TVLIW

VLIW




Signal Processing

- Approach: VLIW width only if required

• sequential code: short instructions

• loops: long instructions

=> VLIW bulit from shorter Instructions

=> Solution: Tagged VLIW (TVLIW)

IWC F# FIW F# FIW

...FIW FIW FIW FI

VLIW-Buffer


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ed Architecture

SIMDPCU

IOProcessor

CU

cu

gs




Signal Processing Slic

=> Expandable by dedicated slices

Slice

Normalizer for "virtual float"

MACALU

Accu

AddressGeneration

Wide Data Memory

Block FloatUnit

BitManipu-

lation

Inter Communication Unit

Regs

Loca

l Com

mun

icat

ion

MACALU

Accu

Regs

MAAL

Ac

ReLo

cal C

omm

unic

atio

n

Loca

l Com

mun

icat

ion


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Problem

loitable

rate 1/4

-loop I/O

ate 1/4




I/O Processing

- I/O transfer is time dependent: no parallelism exp

=> Swap out into special unit

0

20

40

60

80

100

120

140

Datenrate 1/10 Datenrate 1/4 Daten

Zyk

len

in-line in

Data Rate 1/10 Data Rate 1/4 Data R

140

120

100

80

60

40

20

0

Cyc

le B

udge

t (%

)


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Requirements




I/O Processing

- Data manipulation

• framing / deframing data streams

• arranging data sets for DSP-core

=> Bit manipulation

- Data flow control

• handling of communication-protocols

• handle parallel events (e.g. interrupts)

=> Multitasking capability


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xample: Z-ATM I

MHz sample rate

4 Bit)

...

Memory...

BCH Decode(144 / 52 / 25)

t-1ead Data & Flags fromemory, Correct Data,ove Data to ext. Device




I/O Processing E

- Input: 1 sample (16 Bit real & 16 Bit im) @ 25

- Output: data of 4 code words, uncorrected (4x12zero flags corresponding to data

Zero Remove DifferentialDemodulation

8 PSKDemodulation

t+1 tRMM

Move receivedSamples into Memory@ 25 MHz Samplerate

...Memory

FFT

6 OFDM-Symbols =6x 64 Samples

DACs

2 Zero-Flags/MAC = 2x16 Bit

4 CW: 4x{4x(2x16 Bit)}

Decoded, Uncorrected Data =4 CW: 4x(124 Bit)

-> 124 Bit Data = 4x(2x16 Bit)

1 Sample =16 Bit real & 16 Bit im


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xample: Z-ATM II

s (flags)




I/O Processing E

- XOR 4 code-words with corresponding error word

...

...

XOR

Scrambled CWs (3 bit of each CW every second element)

Error-words (2 bit of one CW in each element)


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Basic




I/O Processing

- RISC architecture

• fixed instruction length

• fixed cycles per instruction

- Bit wise processing

- Parallel processing via time-sharing

+1

PC PC+1

RAM OPC

R1

R2


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Data-Interface

IOPem

ALU




I/O Processing

- Access DSP-memory via I/O buffer

- 32-bit I/O bus (2x16)

Datapath

Memory

IO-Buffer

DSPAGU

IO-AR

...

RD

WR

Element

Element

M

Reg

PCU

ext. Ports


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Parameters




I/O Processing

- 3 stage pipeline

- 16 Bit data width (2 13 address space)

- 24 bit instruction width (2 12 instructions)

- Up to 32 tasks

- Ports (hand shake)

• 2x parallel IN, 2x 16 bit parallel OUT

• 2x serial, 2x serial OUT

• 1x parallel IN/OUT


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struction Types

@Reg0 Rx RxO@Rx

Adr Offset

} }

Rx RxO

@Rx

Adr Offset} }




I/O Processing In

- 3 Types of instructions

RxOfsRxRyOfsRyOPCodeArithmetic

Load/Store,

OPCodeSpecial Special/Unused

RxOfsRxRyOfsRyOPCode

Load/Store, @RxRyOfsRyOPCode

Register ⇔ Register

Memory ⇔ DSP

direct

indirectMemory ⇔ RegisterMemory ⇔ Ports

Register ⇔ DSPRegister ⇔ PortsPorts ⇔ DSP


<jork.fm> 5/6/99(5/5/99)



Summary

- CATS: concept to develop a DSP family

• different datapth

• same ISA

• same SW

- M3: one derivate of the concept

• signal processing core with 16 parallel datapth

• I/O core with bit wise- and multi processing capability

CATS And The M3-DSP - TU DresdenCATS And The M3-DSP 5/6/99(5/5/99) CATS And The M3-DSP Frank Engel Mannesmann Mobilfunk Chair For Mobile Communications Systems Dresden

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