CARD ON BOARD (COB) PACKAGING

1

G-Q. Lu, Lecture for CPES’s System Integration Course, Spring 2004. (1)

BASIC MATERIALS AND PROCESSES FOR ELECTRONIC PACKAGING

Dr. Guo-Quan Lu, ProfessorIntegratable Materials (IM) Thruster Leader

Center for Power Electronics ModulesDepartments of MSE and ECE

Virginia Tech

e-mail: [email protected]


I. Introduction

II. Performance Requirements

III. Thick and Thin Film Materials and Processes

IV. Materials and Processes for Plastic Packages

V. Chip-to-Package Interconnect Materials & Processes

LECTURE OUTLINE


ELECTRONIC PACKAGING OFA DESKTOP COMPUTER


CARD ON BOARD (COB) PACKAGING


DEFINITIONS

ELECTRONIC PACKAGING is an engineering field which encompasses the science and technology of interconnection and protection of electronic circuits, consisting of active as well as passive elements, for the purpose of performing complex functions cheaply and reliably .

FUNCTIONS OF A PACKAGE:• Signal Distribution• Power Distribution• Heat Dissipation• Circuit Protection


HIERARCHY OF ELECTRONICPACKAGING – BACK-END

• Level 1: chip is extracted from wafer and placed into an individual carrier or container.

• Level 2: mounting and interconnecting several carriers on a board (e.g. PWB).

• Level 3: assembly of an array of boards, interconnected by means of a mother board and configured into a subsystem.

• Level 4: assembly of a complete system.

2


Level-One :component packaging

Level-Two:board packaging

Level-Three: board-to-board packaging

Level-Four: equipment-to-equipment packaging

PACKAGE HIERARCHY OF POWER ELECTRONICS (a Customized Motor Drive)

Courtesy of CPES


GEOGIA TECH’S PRC PACKAGINGSTRATEGY: SLIM

Single-Level Integrated Module (SLIM) for IC Packaging SiP (System in a Package)

Package Efficiency Today 6-Y Goal 11-Y(Si Efficiency) 8% 40% 80%

Package Cost• Substrate/L/C 1.5¢• Board(6L)/in2 $1.00 5X 10X• Assembly 2.0¢• Test 1.0¢

Package Performance• Ckts Package/cm2 200kT• Interconn. Delay Al, Cu, lower εr 5X 10X• Memory Access 100 MHz• Wireless 900 MHz• Data Rate 100 MB/s

Courtesy of PRC


Integrated Soft-Switching

Integrated Communications, Sensors, Gate Drives, and Protection

Aux. Power Supplies

Optical Fiber andAuxiliary Power

Connector

Thermal conductive encapsulate AdvancedPower Devices

CPES PACKAGING STRATEGY: IPEM

Integrated Power Electronics Module (IPEM) for Power Electronics Packaging


CHALLENGES FROM DISCRETE TO INTEGRATED PACKAGING

CHALLENGES:• highly coupled chemical-thermal-electrical-mechanical problems.• limited materials and processing options.

Discrete to Integrated Packaging

better performance; shorter design cycle; lower cost.ADVANTAGES:


I. Introduction





Lecture Outline



Consequences of Parasitic Capacitance & Inductances:

intel

Pentium

chip

1

2

3

+

-

Since,

=dtdi large

,dtdiLV =

large voltage spikes can be generated.

1000

200

MHzProcessor Speed

Year1995 2000 2005A

BC

DA — 3.3 V @ 6 A

B — 2.6 ~ 3.3 V @ 12 A

C — 1.2 ~ 1.8 V @ 50 A

D — < 1 V

POWER SUPPLY TO MICROPROCESSOR

3


ProcessorCore Die GHz Linear Regulator

Ceramic

Capacitors

Inductors

Silicon

DevicesSocket

Interposer

MHz Switching

Regulator

Motherboard

FUTURE INTEGRATED POWER SUPPLY WITH µ−PROCESSOR?

CPES Proprietary.


HEAT FLUX vs. TEMPERATURE LEVEL


HEAT TRANSFER BY CONDUCTION

Heat Transfer Mechanisms: Conduction, Convection, and Radiation

Fourier’s Law

∆∆

−=xTkAQ

T1 T2

Solid orLiquid

QArea

Heat flow(W=J/s)

Thermal Conductivity(W oC-1 m-1)

Electrical/Thermal Analog

AL

IVR ρ

=≡

Let I Q and V (-∆T),

Ohm’s law,

Ax

kAx

QTR th

th∆

≡∆

=∆−

≡∆ρ


THERMAL RESISTANCE NETWORK OF A PACKAGE


2000513500Diamond

30012919300Gold

3903808800Copper

1207702330Silicon

1509002700Aluminum

22.08343864Alumina

1.10------Thermal Grease

0.5942001000Water

0.3010001500FR4

0.3311001413Polyimide

0.35119510500Epoxy (conductive)

0.2310001500Epoxy (dielectric)

0.02410051.16Air

Thermal Conductivity (Wm-1K-1)

Specific Heat(J kg-1K-1)

Density (kg/m3)Material

THERMAL PROPERTIES OF COMMONLY USED ELECTRONIC PACKAGING MATERIALS

Source: “Fundamentals of Microsystems Packaging,” Edited by R.R. Tummala, 2001.


Support Plate

DeviceDBC

TS

TfluidRfluid

HEAT TRANSFER BY CONVECTION

Newton’s Law of Cooling:

)( fj TThAQ −=

4,5002,000 to 6,000BoilingFC Liquid

1,000200 to 2000Forced ConvectionFC Liquid

200100 to 300Free ConvectionFC* Liquid

4,5003,000 to 7,000Forced ConvectionWater

5010 to 100Forced ConvectionAir

53 to 12Free ConvectionAir

TypicalRangeModeFluidHeat Transfer Coefficient (Wm-2K-1)

* Fluorocarbon Source: “Microelectronics Packaging Handbook,” Edited by R.R. Tummala and E.J. Rymaszewski, 1989.

4


COOLING DESIGN OF IBM’S THERMAL CONDUCTION MODULE (TCM)


TOTAL THERMAL RESISTANCE FOR IC MCMS


MECHANICAL FUNCTION OF ELECTRONIC PACKAGING

Xσ

ε

load

unload

εu

σu

ceramic, glass

Xσ

ε

load

unload

rubber

Xσ

load

unload

ε

yield point

steel

plastic

elastic region

σ

no well defined yield point

0.2% for Cu;0.05% for solder.

Deformation Behavior of Solids:


THERMAL EXPANSION OF MATERIALS

l0, V0

T0 T > T0

l, V

V r

Linear thermal coefficientof expansion 00

0

)(/

Tll

TTll

∆∆

=−

∆=α

Volume thermal coefficientof expansion

αα 3)(

/

00

0 ≈∆∆

=−

∆=

TVV

TTVV

V


Substrate

THERMO-MECHANICAL STRESSES

Example: (no bending)

Substrate

Chip Die-attachAdhesive

Substrate

Chip Solderjoints

Chip

2d

2l

t1

t2t0

x ∆x

F2

F1F1

F2

∆x

α2; E2; t2

α1; E1; t1

τ

τ

τ

τ

G; t0


THERMO-MECHANICAL STRESSES

Shear stress in the adhesive layer, τ(x),

[ ][ ])(sinh)(cosh

)(cosh)(sinh)()(0

21

dlddltdxddxTGx

−+−−+−∆−

=ββββ

βββαατ

where

+≡

22110

11tEtEt

Gβ

τ(x) is maximum at x = l.

0

21max

)(tTG

βαατ ∆−

→

τmax0

21max

)(t

TlG ∆⋅⋅−→

αατ

)( dl −β

If d = 0, i.e. the die-attach case,

0

21max

)tanh()()0;(t

lTGdlxβ

βαατ ∆−===

5


BENDING AS RESULT OF THERMO-MECHANICAL STRESSES

Bending of a Flexible Circuit:

FilmSubstrate

(α1; E1;ν1; t1)

(α2; E2; ν2; t2)

∆T >0α1 < α2 α1 > α2

+ F1F2

F1

F2

+ F1F2

F1

F2


cycles

σamplitude x

σultimate

Constant strain

board

card

card or carrier

module or chip

Coffin-Manson Equation:

logγp

logΝf

zfp MN=γ

where, γp is plastic strain;Nf is # of cycles to failure.

(z ≈ –0.5)

CONSEQUENCE OF CYCLIC STRESSES/STRAININ PACKAGES – FATIGUE FAILURE


Possible Failures:(1) Silicon Failure;(2) Wirebond Failure;(3) Solder/Attachment Failure;(4) Encapsulant Failure;(5) Substrate Failure.

PRIMARY FAILURE MODES IN IGBT POWER MODULES

Power Terminal

Base Plate

DBC Substrate

WireBond

Si Device

Solder

M.C. Shaw of Rockwell Science Center, Tutorial at CPES Annual Meeting, 2000.


ACOUSTIC IMAGES OF SOLDER BUMP/DEVICE INTERFACE AFTER TEMPERATURE CYCLING

To temperature chamber cycling

between 0 – 100oC

Power Chip Al Pad Passivation FilmUBM

Solder Bump Flex Underfill

Victor Liu, Ph.D. candidate, Virginia Tech.

(After 3,400 cycles)

(After 5,600 cycles)(After 7,600 cycles) cracks


Interconnection Materials• High electrical conductivity

• High resistance to electromigration

• High thermal conductivity

• Low thermal coefficient of expansion

• High strength and ductility

• Less fatigue problem

• Ease of processing for low-cost

Metals (Cu, Ag, Au, W, Mo, ...)

Protection Materials• Low electrical conductivity

• Low dielectric constant

• High thermal conductivity

• Low thermal coefficient of expansion

• High strength and toughness

• High dimensional stability and low density

• Ease of processing for low-cost

Ceramics and polymers

Need strong adhesion and compatible processing.

PROPERTY REQUIREMENTS


PROPERTIES OF INTERCONNECTION MATERIALS (METALS):

19

63

19

310

Pb-5% Sn

159

57

16

280

Au-20% Sn

13.34.559111714.219.7αL (10-6 /oC)

90.72011467171397297418κ (W/m K)

6.995.55.210.610.81.72.21.6ρ (10-6 Ωcm)

1453341526251774155210831063960Tm (oC)

NiWMoPtPdCuAuAgMetalProperty

6


PROPERTIES OF PROTECTION MATERIALS (CERAMICS):

5.74 - 88.86.89.3DielectricConstant

3.51.6 – 2.53.33.04.0Density (g/cm3)

high150 - 240300200300Bending Strength (MPa)

1.5

2,000

> 1010

> 3500oC

Diamond(C)

2.5 – 6.55.07.56.5 - 8αL (10-6 /oC)

0.8 - 2100 - 26026022κ (W/m K)

> 1013> 1014> 1014> 1014ρ (Ω cm)

> 2000oC> 2202oC2550oC2045oCTm (oC)

Glass-Ceramics (e.g. 2MgO .

2Al2O3 . 5SiO2)

Aluminum Nitride (AlN)

Beryllia(BeO)

Alumina (Al2O3)

Material Property


Property Polyimide Typical Value Epoxy Typical Value

Dielectric Constant 1 MHz 4.3 4.5

Dissipation Factor 1MHz 0.016 0.020

Dielectric strength, V/mil > 5,000 >3,000 (?)

CTE, X Y axis, ppm/°C 15 18

CTE, Z axis, ppm/°C 50 70

Thermal Conductivity, W/mk 0.4 0.4

Flexural Strength, psi 95,000 65,000

Maximum Operating Temp, °C 250 120-150

Thermal Decomposition Temp 380°C 290°C

Tg, °C 250°C 115-130°C

Water absorption 0.1 - 1 % 0.1 – 1 %

PROPERTIES OF PROTECTION MATERIALS (POLYMERS):


I. Introduction





Lecture Outline



CERAMIC CHIP CARRIERS- Examples

Single-chip Package Multi-chip Package

Pin-Grid Array (PGA)

Ball-Grid Array (BGA)

Dual in-line Package (DIP)

Alumina/W MCM

Glass-ceramic/Cu MCM

TCM


Tape Casting

PROCESSING OF COFIRED METAL/CERAMIC SUBSTRATES


CPES FIRST GENERATION IPEM

DPS Front-end IPEMDesigned by DPS testbed (VT);

built by the Packaging Team (VT).

1”

Hybrid Gate Drive Circuit

THICK-FILM HYBRID SUBSTRATES

7


THICK-FILM HYBRID PROCESING

Screen Printing onCeramic Substrates

Drying and Firing

Device Attachment andInterconnection


SCREEN PRINTING & DRYING/FIRING

• Sequential deposition• Alignment is critical

• 100-150 oC, Drying• 850-1000 oC, Firing


THICK FILM INKS/PASTES(conductor, resistor, capacitor, dielectric, and magnetic)

Conductor Inks (Au, Ag, Cu, Mo, W, Pt-Au, Ag-Pd, Pt-Pd-Ag …):

• Shrinkage matching;• Adhesion to substrate; • Solderability;

+Inorganic Powder Organic Vehicle

Metal Glass or ceramic ModifierSolventsPolymerresin

• Wire bondability;• Resistivity;• Processing atmosphere (Cu needs N2;• Cost.

Selection Considerations:

Mo & W pastes are used for cofiring with Al2O3, BeO, or AlN;Ag, Ag-Pd, Cu inks are often used for cofiring with glass-ceramics.

To improve adhesion, sometimes glasses containing B2O3 (borosilicate) or PbO B2O3 (lead borosilicate) or Bi2O3 PbO B2O3 (bismuth-lead borosilicate) are added to the conductor pastes to form reaction (chemical) bonding between the conductor and substrate.


THICK FILM INKS/PASTES(conductor, resistor, capacitor, dielectric, and magnetic)

Dielectric Pastes:

Glasses like borosilicate, lead borosilicate are used for low k dielectrics and passivation;

Barium titanate (BaTiO3) pastes are used for capacitors. Glass powder modifiers are often added to BaTiO3 to vary its Curie point and also act as a binder phase. But, they significantly reduce the permittivity of the material system.

Inductor (Ferrite) Paste:

Ferrites are ferrimagnets, a class of ionic oxide crystals with composition of the form XFe2O4 where X (Ni, Fe, Co, Mn) is divalent metal. They have high relative magnetic permeability, µr, and high electrical resistivity.


THIN-FILM PROCESSES FOR PACKAGING

A coarser version of the processes compared with those used for IC manufacturing. (thickness ~ µm; line definition ~ mil)

Examples:

AT&T’s Advanced VLSI Packaging IBM’s MCM-D on MCM-C

MCM-D


THIN-FILM BASED PROCESSES FOR PACKAGING POWER ELECTRONICS

Example:

GE’s High Density Interconnect / Power Overlay Technology

SolderIGBT

DBC Substrate

IGBT Diode Diode

Cap

Cu Post

Via

Emitter Bond Pad

Dielectric Layer

Cu Metallization

Silica Filled EpoxyCu Shim

8


THIN-FILM DEPOSITION TECHNIQUES

By way of a melt or solution By way of the gas phase

Electroplating

Liquid phase growth

Dipping in solution

Sol-gel processing

Spin-coating

…

Physical vapor deposition (thermal evaporation, sputtering, …)

Chemical vapor deposition

…


PROCESSING OF POLYIMIDE THIN FILMS

Polyimide form (PMDA-ODA)

Heat at 200oC – 300oC

Poly(amide acid) from Oxydianiline (ODA) and Pyromellitic dianhydride (PMDA) -soluble in an organic solvent


DRY ETCH (REACTIVE-ION OR PLASMA ETCH) OF POLYMER FILMS

Substrate atNegative electrode

Vacuum pump(exhaust)

Etch gas inletReactive plasmaO2 + CF4

(F-, O=)

F- O=O=

O=O=

O=

F-F-

F-

F-

C - C

H HHydrogen

abstraction

C - C. H

HF +

Oxygenation

Fluorination

C - CHO

C - CHF

Retard etchingO2/CF4 needs optimized.


Processing of Metal Thin Films


PROCESSING OF METAL THIN FILMS

Copper is the preferred metal; but, Cu does not adhere well to polyimide. Use of Cr or Ti as an adhesion layer.

Physical vapor deposition techniques (vacuum evaporation or sputtering) are often used for the metal thin films.

Vacuum Evaporation:

metal

Resistive or e-beam heating

p

T

SV

L

p = vapor pressureRTHepp /

0∆−=

∆H – heat of vaporization


DEPOSITION RATE OF EVAPORATED METAL THIN FILMS

MRTpNJ Atimpingemen

substrate π2=

J – atomic flux, atoms per area per time;NA – Avogadro number;M – atomic mass;p – pressure; T – absolute temperature.

Film growth rate,

MNMRT

pNdA

As

ρπα 12

⋅

≈

•

(αs – sticking coef.)

Impurity concentration due to residual gas (H2O, CO2, O2, N2 ..):

Xi – fraction of residual gas in the film

⋅

≈

g

film

film

gi M

Mpp

X

9


METAL DEPOSITION BY EVAPORATION

Example:

copper

sec/200o

Cu Ad =•

torp OH510

2

−=T = 25oC

What is CuO in the film assuming 10% of H2O impinging on the film form CuO?

)sec(108.1 1217 −−•

⋅⋅×≈⋅⋅= cmatomsMNdJCu

ACu

impingCu ρ

)sec(107.42

1215

2

2

2

−− ⋅⋅×== cmatomsRTM

NpJ

OH

AOHimpingOH π

%.25.0%10

2 == impingCu

impingOH

CuO JJ

X


PROCESSING OF METAL THIN FILMS -Sputtering

target

to vacuumpumpground

V > kV

Ti, Cu, Cr, ..

substrate

gasinlet

vacuumseal

substrate

Anode (+)

Cathode (-)

Aston dark space

Plasma

Cathode glow

Positive column

Faraday dark space

Crook’s dark space

Negative glow

ground


Multi-TargetSputtering System

Titanium

Nickel

Copper

substrate

Ti, Cu, Cr, ..

substrate

Anode (+)

Cathode (-)

e-

Ar+

Ar+Ar+Ar+

Ar+

Ar+e- e- e-

PROCESSING OF METAL THIN FILMS

Sputtering and Deposition Processes:

e- emission fromthe target (cathode)

Acceleration of Ar+to the target

Removal of targetatoms by the impinge-

ment of Ar+;

Deposition of targetatoms on the substrate


D. C. Source

Anode(copper)

Cathode

Cu Plating bath

Mask

Cu++

Electrolytic Metal Plating:

ELECTROCHEMICAL DEPOSITION OFTHIN METAL FILMS

Cu++ + 2e- Cu0Cu0 Cu++ + 2e-

Reduction:Oxidation:

Cu

Cu

++

++

Faraday’s law of electrolysis:

FnItAW w=

W – weight of deposit in grams;I – current flow in amps; t – time; F – Faraday constant (eNA);n – number of electrons transferred;Aw – atomic weight (grams/mole).

⋅

≈•

pAJd w

ρη 1.0

ρ – film density (gm/cc);J – current density (A/cm2); η – plating efficiency;p – oxidation state.

Film growth rate (µm/s):

V > V0


ELECTROCHEMICAL DEPOSITION OFTHIN METAL FILMS

Electroless Metal Plating:

Non-conductingActivation

Non-conducting

Oxidation (Anodic):HCHO + H2O HCOOH + 2H+ + 2e-

Reduction (Cathodic):

Mn+ + ne- M0

conducting

Formaldehyde

Electroless plating

Thickness limit ~ 1 µm


I. Introduction





Lecture Outline


10


PLASTIC PACKAGES - examples


TYPICAL PLASTIC PACKAGE ACRONYMS


HERMETIC VS. NON-HERMETIC PACKAGES

Hermetic packages are typically made of inorganic materials, metals for interconnect and ceramics for protection.

Non- hermetic packages -plastic encapsulate packages -are made of metals for interconnect and organic materials or polymers for protection.

Diffusion of moisture is much faster in polymersthan in metals and ceramics.

Atomic flux by diffusion: x

cDJ∂∂

−= D ≡ diffusion coefficient;

Diffusion distance, DtlD ~small in inorganics;large in organics.

Moisture causes corrosion in chip interconnects failure.


PLASTIC PACKAGES

Dual-in-line Package

Low-cost, over 70% packaging market.

Major Components


TWO COMMON TYPES OF POWER CHIP PACKAGES

Through-hole Surface-mount&


PLASTIC PACKAGES – Lead Frame

(1). A holding fixture for automated operation;(manufacturing)

(2). A dam that presents plastic from rushing out between the leads during the molding operation; (manufacturing)

(3). Chip attach substrate; (mechanical/thermal)

(4). Support back-bone for the plastic; (mechanical)

(5). Electrical and thermal conductor from chip to board. (electrical/thermal)

Functions:

11



Materials:(i) Nickel-Iron (42% Ni – 58% Fe) Alloy – Alloy 42:

Tm (melting) = 1425oC; E (Young’s modulus) = 144.83 GPa;α (linear CTE) = 4.3 ppm/oC; αSi = 3.0 ppm/oC;κ (thermal conductivity) = 0.16 W cm -1 oC-1.

Advantages:• Excellent CTE match to Si;• Easily electroplated or solder-dipped;• Compatible with gold-silicon eutectic chip-attach

(forming a strong bond).

Disadvantages:• Low thermal conductivity (0.16 vs. 8 of Cu).But pure Cu is mechanically too soft for processing.



Materials:(ii) Copper-Clad Stainless Steel (emulating the mechanical

properties of Alloy 42 while increasing thermal conductivity:

α(linear CTE) = 11 – 17 ppm/oC;κ (thermal conductivity) = 3.6 W cm -1 oC-1.

Stainless SteelCopper Formed by rolling and annealing.

Solid-state weld.

(iii) Copper Alloys (Cu + few % of Fe, Zr, Zn, Sn, P) to improve the mechanical properties of pure Cu.

Since αCu alloys >> αsi, can not use Au-Si eutectic for die attach; have to use Ag-filled adhesives (epoxy or polyimides).

(iv) Direct-bond Copper (DBC). Al2O3 or AlNCopper

Copper


CHIP BONDING ADHESIVES


ELECTRICAL AND THERMAL PROPERTIES OF SOME PLASTIC PACKAGES



Lead Frame Fabrication

Fast turn-around;

Ideal for package under development;

Expensive.

Long lead time;

Expensive initial investment on progressive stamping dies;

Fast and cheap if dies are in place.

Mechanical StampingChemical Etching(photolithographic process)


PLASTIC PACKAGES - Encapsulation Materials

Widely used in 1st level (chip carrier) and 2nd level (board/card).

Polymers (synthetic)

Thermoplastics(e.g. polyethylene, polystyrene,

polypropylene, …)

Thermosets(e.g. epoxies, polyimides, …)

Thermosetting polymers are typicallylow-molecular weight polymers

(oligomers) that undergo large chemicaland physical changes during processing.

Thermoplastics are processible by theapplication of heat and pressure,and in the absence of degradation,no chemical reaction takes placeduring processing.

12


PLASTIC PACKAGES - Encapsulation Materials

Typical Formulation:1. Cresol Novolac epoxy resin (25.5 – 29.5%);

2. Inert filler – SiO2 (68 – 72%);

3. Curing agent;

4. Accelerator;

5. Flame retarder (2%);

6. Mold-release agent;

7. Colorant (0.5%).


Printed Circuit or Wiring Board (PCB or PWB) Materials and Processes

SECOND-LEVEL PACKAGING


CONSTITUENTS OF EPOXY RESINS USED IN PCB


PROCESS FLOW FOR EPOXY-GLASS PCB

(a) Silane coated glass cloth impregnation and core lamination of copper and epoxy glass;

(b) Power core and signal core photoprint and etching;

(c) Composite lamination of internal signal and power cores;


PROCESS FLOW FOR EPOXY-GLASS PCBcontinued

(d) Composite lay-up cores + copper-epoxy glass and composite drill;

(e) Composite photoprint;

(f) Composite plate holes and circuitizing.


PCB TECHNOLOGY TREND

13


I. Introduction





Lecture Outline



Single-chip Package of a Power Device Multichip Package of a Power Module

Dual-in-line Package of an IC Chip

WIRING BONDING


WIRING BONDING -Materials

• Aluminum (Al + 1% Si, Al+0.5 – 1% Mg) wires (diameter > 25 µm);

• Gold (Au + ppm Be, Pd, ..) wires (diameter ~ 25 µm);

• Copper (Cu + % Fe, Zn, ..) wires (diameter > 25 µm).

Wire Types:

Reason for alloying:Ease of drawing and handling the wires at small diameters. Pure Al, Au, and Cu are too soft mechanically to draw and handle.


First Bond With Tail

Second Bond

WIRE-BONDING PROCESSES –Wedge Bonding (use of ultrasonic welding method)


Ball and Crescent Bonds

Ball and Wedge Bonds

WIRE-BONDING PROCESSES –Ball Bonding (use of thermosonic welding)


IC PACKAGE TECHNOLOGY ROADMAP

14


FLIP-CHIP INTERCONNECT TECHNIQUE

IBM’s C4 – Controlled-Collapse-Chip-Connection

Solder balls


Al

UBM (Cr/CrCu or Ti/Ni)

Chip Passivation

Cu

AuSolder Ball

Device

UNDER BUMP METALLIZATION

UBM can be processed by sputtering/Evaporation/electroplating.


LIST OF LOW-MELTING SOLDER ALLOYS


LEAD-TIN BINARY PHASE DIAGRAM


BINARY PHASE DIAGRAMS OF OTHERSOLDER MATERIALS


EVAPORATION OF SOLDER BALLS

Metal Mask Set

15


SOLDER-BALL REFLOW PROCESS

Self-alignment restoring forces and oscillationsduring dynamics of solder wetting.


Ball-Grid Array (BGA) Package, < 1.2 of the chip size.

(Courtesy Motorola Inc.)

CHIP-SCALE PACKAGING


RELIABILITY OF SOLDER JOINTS

Substrate

Chip Solderjoints

2l

Substrate

Chip

2d

t1

t2t0

x ∆x

F2

F1F1

F2

∆x

α2; E2; t2

α1; E1; t1

τ

τ

τ

τ

G;. t0.

0

21max

)(tTG

βαατ ∆−

→

τmax0

21max

)(t

TGl∆−→

αατ

)( dl −β

+≡

22110

11tEtEt

Gβ


Power ChipAl Pad Passivation FilmUBM

Inner Solder BumpMiddle Solder Bump

External Solder BumpFlex Underfill

Schematic structure of the triple-stacked solder bump

Schematic structure of the conventional solder bump

RELIABILITY OF SOLDER JOINTS –Shape Effect


SubstrateUnderfillSolder bump

Barrel Type Hourglass TypeSymmetric Asymmetric Symmetric Asymmetric


RELIABILITY IMPROVEMENT USING UNDERFILL

Schematic Structure of a Solder Joint:


Solder Bump Flex Underfill

Underfill adhesives improve package reliability by:

• distributing and reducing thermo-mechanical load on the solder joints.• sharing and reducing the solder joint strain;• preventing the attacks of moisture, dust, and any corrosive chemicals

on solder joints and the chip.

A factor of 10 to 100 increase in the fatigue life of solder joints.


EFFECT OF UNDERFILL CTE ON JOINT LIFE

16


OTHER METHODS TO IMPROVEJOINT RELIABILITY

Stacked Solder Bumps

Solder Columns


SELF-STRETCHING SOLDERING TECHNOLOGY


DOUBLE-PLATE THREE-DIMENSIONAL POWER MODULE

MetalPosts

Metal Layers

Dielectric orCoolant

Multilayer Hybrid Substrate for Gate Drives, Control, etc.Dielectric (AlN, Alumina, etc.)

Dielectric (AlN, Alumina, etc.)

Heat Sink (MMC, Al, etc)

Device Device

Metal-Post Interconnect Parallel Plate Structure (MPIPPS):

Positive

Negative

Out


REFERENCES

“Microelectronics Packaging Handbook,” edited by R.R. Tummala, E. J. Rymaszewski, and A.G. Klopfenstein, Chapman & Hall, 1997.

“Fundamentals of Microsystems Packaging,” by R.R. Tummala, McGraw Hill, 2001.

CARD ON BOARD (COB) PACKAGING

Documents