1 Capstone Design Course Lecture-9: ANALOG-TO-DIGITAL CONVERTER SYSTEM By Syed Masud Mahmud, Ph.D. Copyright 2002 by Syed Masud Mahmud
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Capstone Design Course
Lecture-9: ANALOG-TO-DIGITAL CONVERTER SYSTEM
By
Syed Masud Mahmud, Ph.D.
Copyright 2002 by Syed Masud Mahmud
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A/D Conversion Theory• Here, an example is shown for a 3-bit A/D converter.
Four capacitors are used for a 3-bit A/D converter.
• An N-bit A/D converter is built using N+1 capacitors
and an analog comparator.
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A/D Conversion Theory (contd.)Sample Mode
• In this mode the bottom plates of the capacitors are
connected to the unknown voltage Vx and the top plates
are connected to the lower reference voltage VL.
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A/D Conversion Theory (contd.)
Charge Stored During the Sample Mode
• The charge in all the capacitors, stored during the
sample mode, can be computed as QS = 8(Vx - VL). If we
assume VL= 0, then QS = 8Vx.
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A/D Conversion Theory (contd.)
Hold Mode : In this mode the bottom plates are
switched to VL. Since the charge is conserved, we
still have the same amount of charge, i.e. QS = 8(VL -
Vi) = -8Vi. From the previous slide we know that QS =
8Vx. Hence, Vx = -Vi.
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A/D Conversion Theory (contd.)
Conversion Mode : In this mode, each capacitor,
beginning with the largest one, which corresponds to
the most significant bit (MSB) of the digital result, is
switched from VL to VH.
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A/D Conversion Theory (contd.)Determine the MSB of Digital Output : Let’s assume that,
VX=3.2v, VH=5.0v and VL=0.0v. Our goal is to determine
the digital output. QS = 8VX = 8*3.2 = 25.6
• If the largest capacitor is connected to VH then QS = 4(VH - Vi) + 4(VL - Vi) = 4*5 – 8* Vi = 25.6. Hence, Vi = -0.7v.
• Since Vi is negative, Vout is logic-1, i.e. MSB = 1.
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A/D Conversion Theory (contd.)Determine the Next Bit of Digital Output: Now the
capacitor with value 2 is also switched to VH.
• This time, QS = 6(VH - Vi) + 2(VL - Vi) = 6*5 – 8* Vi = 25.6.
Hence, Vi = 0.55v.
• Since Vi is positive, Vout is logic-0, i.e. the next bit of
digital output is a 0.
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A/D Conversion Theory (contd.)Determine the LSB of Digital Output: Since the middle bit
of digital output is a 0, the capacitor with value 2 will be
switched back to VL and the capacitor with value 1 will
be switched to VH. This time, QS = 5(VH - Vi) + 3(VL - Vi) =
5*5 – 8* Vi = 25.6. Hence, Vi = -0.075v. Since Vi is
negative, LSB=1. Thus, DIGITAL OUTPUT = 101.
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A/D Converter Channels
• Each one of Port-E line is an A/D converter
channel. Thus, altogether there are 8 channels.
• As a result, signals from 8 analog sources can
be collected by the 68HC11 microcontroller.
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A/D Converter Channels
• Normally VRH and VRL are 5v and 0v lines,
respectively.
• Different voltage signals, in the range 0v to 5v,
can be connected to these pin with VRL< VRH.
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Analog Input & Digital Output
• If analog input is equal to VRH, then digital output is
equal to $FF.
• If analog input is equal to VRL, then digital output is
equal to $00.
• The conversion curve is linear for other voltages in
the range VRL to VRH.
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ProblemsProblem-1: What is the value of digital output for an
analog input of 3.2v (assume that VRL = 0v and VRH = 5v) ?
• The slope of the analog to digital conversion line is 255/(VRH - VRL) = 255/5v = 51units/volt.
• Hence, the digital output for an analog input of 3.2v is = 3.2v*255/5v = 163.
Problem-2: If the digital output is 198, then what is the corresponding analog input (VRL = 0v, VRH = 5v) ?
• Since the slope of the conversion line is 51units/volt, the analog input = 198/51 v = 3.88v.
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More Problems• For the following two problems assume that VRL = 1v
and VRH = 4v.
Problem-3: What is value of digital output for an analog
input of 3.2v ?
• The slope of the conversion line is 255/(VRH - VRL) =
255/3v = 85 units/volt. Hence, the digital output for an
analog input of 3.2v is = (3.2v - VRL)*85/v = 2.2*85 =
187.
Problem-4: If the digital output is 198, then what is the
corresponding analog input ?
• Since the slope of the conversion line is 85 units/volt,
the analog input = VRL + 198/85 v = 3.33v.
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Registers of 68HC11 A/D Converter System
• Bit-7 of OPTION register is used to activate the charge
pump of the A/D converter.
• Bit-6 of OPTION register is used to select the A/D
converter clock.
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Registers of 68HC11 A/D Converter System
CSEL = 0 : E clock is selected for A/D the converter
CSEL = 1 : An internal R/C clock is selected for the A/D
converter
• If the frequency of E clock is less than 750 KHz, then the
internal R/C clock should be used for the A/D converter.
• After setting the ADPU bit (Bit-7) of the OPTION register
we should wait for at least 105 micro-seconds before we
can ask the A/D converter to start conversion.
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ADCTL – A/D Control/Status Register
• The A/D conversion is started by writing a bit-pattern
into ADCTL register.
Modes of A/D Converter:
MULT (Bit-4) = 0 : Single channel mode
Only one channel is selected in this mode.
MULT (Bit-4) = 1 : Multi-channel mode
Four channels are selected in this mode.
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Non-Scan and Single Channel ModeSCAN (Bit-5) = 0 and MULT (Bit-4)=0
• The A/D converter collects four samples from one
channel and then stops.
• These four samples are saved in the following
registers:
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Non-Scan and Multi-Channel Mode
SCAN (Bit-5) = 0 and MULT (Bit-4)=1
• The A/D converter collects four samples from four
channels, one from each channel and then stops.
• These four samples are saved in the following registers:
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Channel Selection
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CCF: Conversions Complete Flag
• This read-only status bit (Bit-7 of ADCTL) is set when all four A/D result registers contain valid conversion results.
• Each time the ADCTL register is written, this bit is automatically cleared, and a new conversion sequence is started immediately.
• In the continuous scan modes, conversions continue in round-robin fashion, and the result registers are updated with current data even though the CCF bit remains set.
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Programs-1: A2DPROG1.txt
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A2DPROG1.txt (contd.)
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A2DPROG1.txt (contd.)
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A2DPROG1.txt (contd.)
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Program-2: A2DPROG2.txt
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A2DPROG2.txt (contd.)
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A2DPROG2.txt (contd.)
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A2DPROG2.txt (contd.)
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A2DPROG2.txt (contd.)
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Program-3: A2DPROG3.txt
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A2DPROG3.txt (contd.)
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A2DPROG3.txt (contd.)
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A2DPROG3.txt (contd.)
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A2DPROG3.txt (contd.)