CAMBRIDGE UNIVERSITY NAPOLI UNIVERSITY ISPSD, Santa Barbara, May 2005 A compact model for thin SOI LIGBTs: description, experimental verification and system.

ISPSD, Santa Barbara, May 2005CAMBRIDGEUNIVERSITY

NAPOLI

UNIVERSITY

A compact model for thin SOI LIGBTs:description, experimental verification

and system application

Ettore Napoli1,2, Vasantha Pathirana1, Florin Udrea1,3,Guillaumme Bonnet3,Tanja Trajkovic3,Gehan Amaratunga3

1 Dept. of Engineering, University of Cambridge, UK2 Dept. Electronic and Telecom. Univ. of Napoli, Italy3 Cambridge Semiconductor (CamSemi), UK

EU research program ROBUSPIC


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Outline

Motivation Thin SOI LIGBT Differences with Vertical IGBT Spice sub-circuit model for LIGBT

Model equations Model behavior

Half bridge circuit using lateral IGBT Experimental results on flyback circuit Conclusion


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Motivation

• Available IGBT circuit models are not suited to Lateral IGBT

• Need for– a reliable physical based model for Lateral IGBT– usable in various circuit simulators

• Extension to different LIGBT technologies

• Important for smart power design


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Thin SOI Lateral IGBT

• 600V PT• Transparent buffer• Source and Drain up to the BOX• Current flow is horizontal and 1D


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Differences with Vertical IGBT (1)

• Not zero carrier concentration at the collector edge for LIGBT


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IGBT models not suited for LIGBT (1)

• Total charge and charge profile

LIGBT

Vertical IGBT

LW

LxPLxWPxp W

sinh

sinhsinh0

LWqALPPQ W 2tanh0

LW

LxWPxp

sinh

sinh0

LWqALPQ 2tanh0


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Differences with Vertical IGBT (2)

• Depletion width vs. reverse voltage is influenced by 2D effects


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• Voltage rise at turn-off is faster due to lower charge in the epilayer and slower depletion width expansion


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• Important effects such as the voltage bump, resulting in a delay in the turn-off, are not considered


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Spice sub-circuit model for LIGBT

Currents and voltages Epilayer charge equation


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Cox

Cgs

I (W)N

IPC_TRNI (0)NI (W)NI (W)P

Cdep

Cds

Q

Vdrift

Drain

Source

Gate

Vj

Vmos

N+

G DS

NN-

BOX

Substrate

P+

P+

I (0)N

VjVdriftVmos

I (W)N

I (W)P

• Vj : Emitter junction• Vdrift:Depends on the injected carriers

– analytic solution• Vmos: Mosfet (level 1)


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Cox

Cgs

I (W)N


Cdep

Cds

Q

Vdrift

Drain

Source

Gate

Vj

Vmos

N+

G DS

NN-

BOX

Substrate

P+

P+

I (0)N

VjVdriftVmos

I (W)N

I (W)P

• IN(W) : Electron current through the level 1 Mosfet


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Cox

Cgs

I (W)N


Cdep

Cds

Q

Vdrift

Drain

Source

Gate

Vj

Vmos

N+

G DS

NN-

BOX

Substrate

P+

P+

I (0)N

VjVdriftVmos

I (W)N

I (W)P

• IP(W) : Bipolar hole current

(W/L)b(W/L)P

(W/L)b

(W/L)P

L

qADI

bn

PWI

w

sne

i

P

sinh

1coth

sinh

1coth

)(0

2

20


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Cox

Cgs

I (W)N


Cdep

Cds

Q

Vdrift

Drain

Source

Gate

Vj

Vmos

N+

G DS

NN-

BOX

Substrate

P+

P+

I (0)N

VjVdriftVmos

I (W)N

I (W)P

• IN(0) : Electron current through the emitter junction

2

20

200)0(

i

sne

i

BsneN

n

PI

n

)P(NPII


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Cox

Cgs

I (W)N


Cdep

Cds

Q

Vdrift

Drain

Source

Gate

Vj

Vmos

• IPC_TRN : Transient current due to charge sweep-out

t

tWtWqApI TRNPC

_

Increasing Anode Voltage

Stable Anode Voltage

P

0

PW

Wt Wt+δt Wt+2δt

Time is increasing

0


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Base charge equation

IN(W) is the MOSFET current

IN(0) is the emitter edge electron current

IPC_TRN is the charge sweep out current

The last term is for the recombination in the base

Q

IIWIt

QTRNPCNN

_0


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Other model features

Carrier concentration dependent mobility model

Gate-Source Drain-Source and Gate-Drain capacitances are implemented

Physical based model with 13 parameters


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Model behavior

Inductive Turn-off

Expanded for I=1A, V=200V

VoltageCurrentPower


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Model behavior

• Toff Energy vs. Von as a function of lifetime


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Half bridge circuit

• Output characteristics

200V; 2A; 100kHz


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Experimental results on flyback circuit

E xpe rim en ta l re su lts V g = 5V

V g = 4V

V g = 3V

V g = 2V

D ra in v o lta g e [V ]0

0 .5Dra

in c

urre

nt [

A]

1 4 5

O u r m o de l

0

1 .5

1

2

2 3


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Experimental results on flyback circuit

Dra

in V

olta

ge [

V]

Dra

in C

urre

nt [

A]

Pow

er [

kW]

0

0

0 .2

0 .2

0 .4

0 .1

0 .6

0 .3

0 .8

1 .0

1 .2

Tim e [n s]5 0 1 0 00 2 0 0 2 5 01 5 0 3 0 0

0

8 0

1 6 0

2 4 0

3 2 0

4 0 0

4 8 0

E x p e rim e n ta l re s u ltO u r m o d e l

E x p e rim e n ta l re s u ltO u r m o d e l


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Flyback circuit simulation1K

20

47pF

D22 F

1mF

100V

LIGBT

Complete flyback circuit

The simulated waveforms are for the primary winding voltage (green) and the load voltage (red)

Time [ s]

Vol

tage

[V

]

0 20 40 60 80 100

0

100

200

-100

-200

-300


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Conclusion

• A physical based circuit model for Lateral IGBT• Implemented in Spice• Compared against

– Device numerical simulation– Complex SMPS simulation– Experimental results

• Extendable to Thick SOI and JI-LIGBT

CAMBRIDGE UNIVERSITY NAPOLI UNIVERSITY ISPSD, Santa Barbara, May 2005 A compact model for thin SOI LIGBTs: description, experimental verification and system.

Documents

university of cambridge

santa barbara

ligbt slide

mosfet slide

d slide

igbt models

vertical igbt spice

ligbt currents