DESIGN IP BROCHURE Version 2.2 Cadence IP Factory Get on the Fast Track to SoC Design Innovation
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Design iP Brochure
Version 2.2
cadence iP Factoryget on the Fast Track to soc Design innovation
ip.cadence.com2 Design IP Brochure Version 2.2
Cadence Design IP Overview
Cadence® IP Factory provides integration-focused IP and IP subsystems that are proven to reduce risk and accelerate the development of leading-edge SoCs. Our interface IP for key memory, storage, and interconnect standards—in addition to our core building-block IP—help you design and integrate the highest quality SoCs with optimal performance and power.
We Always Listen to You
We always listen to our customers and want to meet their needs. Prior to its realization, every SoC project is discussed with you and examined in detail.
“...we respond quickly, and we listen to the customer very closely. I spend most of my time in front of customers. I want to be their trusted partner, to provide the best tools and solutions, and to help them work through some of the most challenging designs they have.”
Lip-Bu Tan interviewed by Richard Goering on August 27, 2013
standards-Driven Design iP Targeted to Your needs
Supporting advanced capabilities Cadence Design IP offers superior performance and power-optimized solutions. Our extensive support for new standards, such as TSMC 28HPC, ensures power- and cost-efficient design. No matter if the application is a high-performance datacenter or a power-sipping mobile device, we provide you with IP which is targeted to your specific needs.
“By delivering our interface, memory, analog and systems/peripheral IP to this 28HPC process, our customers in the smartphone, tablet, and other high-volume consumer markets can take advantage of the 10 percent smaller die size and 30 percent power reduction benefits of this new process.”
Martin Lund, September, 2014
integration-Focused for reduced risk
Integration of IP has traditionally been a challenge for SoC designers. By building our IP from the ground up, and by focusing on integration, we help you significantly reduce both integration effort and risk. In addition, our ability to deliver fully integrated controller, PHY, and firmware solutions at both the interface and subsystem level further reduces your integration effort.
unique customization infrastructure
We can deliver IP configured to your specific SoC design requirements, providing only those features and performance levels needed for your particular application.
Using our customization infrastructure eliminates the need to compromise—you can specify the IP around your design rather than building your design around the IP. Furthermore, each of our customized IP solutions is fully verified and delivered with complete documentation plus an integration and verification environment that is perfectly matched to the IP.
Proven Partner You can count on
Cadence Design IP is silicon proven and has been extensively validated. We offer comprehensive IP solutions that are in volume production and have been successfully implemented in more than 400 applications. With 13 years of experience delivering winning IP solutions, Cadence is a proven partner you can count on.
“You have to rely on partners, you have to rely on experts, whether that’s hardware/software codesign, analog-mixed signal, analysis tools, signoff, DFT.”
Martin Lund being interviewed at MemCon 2013 by ChipEstimate.tv’s Sean O’Kane
ip.cadence.com Design IP Brochure Version 2.2 3
interface iP solutions
We offer various complete, configurable, and production-proven interface protocols, such as Ethernet, MIPI®, PCI EXPRESS®, and USB. All these solutions are designed with your SoC in mind, so that there is no need for you to design around our IP. Pre-verified solutions help you save time and effort and allow you to focus on your own design priorities. Moreover, our highly configurable architecture provides you with numerous customization options, including software and prototyping solutions.
iP Protocols Performance controller Pcs
PhY
TsMc
65nm 55nm 40nm 28nm 16nm
LP LPe LPe LP hPL hPM hPc LP FF
eth
ern
et
MAC
10M/100M 10M/100M* • •
10M/100M/1G 10M/100M/1G* • •
10/40G 10/40G • • • • •
40/100G 40/100G • •
PCS
10G 10/40G • • • •
10/40G 10/40G • • • •
40/100G 40/100G • • • •
XAUI/XAUI20 10/20G • • • •
Converter QSGMII R1.2 5G •
MiP
i
DSI DSI TX 1.5Gbps/lane • † † † † † †
CSICSI-2 RX 1.5Gbps/lane • † † † † † †
CSI-2 TX 1.5Gbps/lane • † † † † † †
DigRFSM DigRF v4, v1.10 3Gbps/lane • ‡ ‡ ‡ ‡ ‡ ‡
UniProSM UniPro 1.6 3 or 6Gbps/lane • ‡ ‡ ‡ ‡ ‡ ‡
SLIMbus®Device v1.1 Audio/Data •
Manager v1.1 Audio/Data •
SoundWire Master Audio •
Pci e
XPr
ess
PCIe®
Gen 1 2.5Gbps • • • •
Gen 2 5Gbps • • • •
Gen 3 8Gbps • • • •
Gen 4 16Gbps • •
M-PCIe™M-PCIe ECN, SL HS-G2/HS-G3 • • • •
M-PCIe ECN, ML HS-G2/HS-G3 • • • •
usB
HostUSB 2.0 480/12/1.5Mbps • • • • • • • • •
USB 3.0 5Gbps and legacy • • • •
Device
USB 1.1 12/1.5Mbps • • • • •
USB 2.0 480/12Mbps • • • • • • • • •
USB 3.0 5Gbps and legacy • • • •
OTG USB 2.0 480/12/1.5Mbps • • • • • • • • •
Hub USB 2.0 480/12/1.5Mbps • • • • • • • • •
HSIC Interface USB 2.0 HSIC 480Mbps • • • •
SSIC Interface USB 3.0 SSIC 5/2.5/1.25Gbps • • • • • • •
Table 1: Interface IP Solutions * Soft PHY available † – D-PHY‡ – M-PHY
ip.cadence.com4 Design IP Brochure Version 2.2
Denali Memory iP solutions
We offer the broadest and most configurable portfolio of the industry’s widely used memory and storage protocols.
Our Denali® Memory IP gives you the added value of multi-standard DDR support by providing controller IP that supports DDR4, DDR3, DDR3L, LPDDR2, and LPDDR3 as a single IP solution. In order to address a wide range of applications, our DDR PHY IP includes two families of DDR solutions, High-Speed (HS) and Low-Power (LP). Delivery options include soft, firm, hard, and full custom IP.
We also offer advanced memory IP solutions created by the best experts in the field to provide you with the controller, PHY, and verification IP you need for your design.
ProtocolsMaximum
speedcontroller
PhY
soft
TsMc gF sT
40nm 28nm 16nm 28nm 28nm
LP g hPM hPc LP FF sLP hPP FDsoi
DDR DDR400 • •
DDR2 DDR800 • • •
DDR2/DDR DDR800 • •
DDR3*/DDR2 DDR800 • • •
DDR3*
DDR1333 • • • • • • • • • •
DDR1600 • • • • • • • • •
DDR2133 • • • • • •
DDR4
DDR1600 • • • • • • •
DDR2400 • • • • • •
DDR2667 • • • •
DDR3200 • •
DDR4/DDR3*
DDR1600 • • • • • • •
DDR2400 • • • • • •
DDR2667 • • • •
DDR3200 • •
LPDDR DDR400 • •
LPDDR2 DDR800 • •
LPDDR2/LPDDR DDR800 • •
LPDDR2/DDR3* DDR800 • •
LPDDR2 DDR1066 • • • • • •
LPDDR2/DDR3*DDR1333 • • • • • •
DDR1600 • • • •
LPDDR3DDR1333 • • • • • •
DDR1600 • • • •
LPDDR3/LPDDR2DDR1333 • • • • • •
DDR1600 • • • •
LPDDR3/LPDDR2/DDR3*DDR1333 • • • • • •
DDR1600 • • • •
LPDDR4/LPDDR3
DDR2400 • •
DDR2667 • •
DDR3200 • •
LPDDR4/LPDDR3/DDR4/DDR3
DDR2400 • •
DDR2667 • •
DDR3200 • •
Wide I/O 200MHz • •
Table 2: Denali Memory IP Solutions * DDR3 includes DDR3L support
ip.cadence.com Design IP Brochure Version 2.2 5
storage iP solutions
Cadence storage IP solutions consist of two popular technologies, NAND Flash and SD/SDIO/eMMC. These memory technologies address the needs of a broad range of market requirements.
The Cadence NAND Flash Controller IP supports all major NAND Flash manufacturers handling asynchronous devices and also meeting standards such as ONFI 1, ONFI 2, ONFI 3, ONFI 3.2, Toggle 1, or Toggle 2. The Cadence NAND Flash PHY IP supports speeds up to DDR800 for most process nodes, and is available as soft IP with a delay-locked loop (DLL) for your specific process and library.
The Cadence SD/SDIO/eMMC IP is compliant with the latest versions of Secure Digital and Embedded Multimedia Memory Card standards, which makes our IP the perfect choice for both high-performance and low-power solutions.
iP Performance controllerPhY
soft
nA
nD
Fla
sh
NAND Flash Async, ONFI 3.2/2/1, Toggle 1/2 Controller 533MTps •
NAND Flash ONFI 4/3/2/1, Toggle 1/2 DLL PHY 800MTps •
NAND Flash ClearNAND Controller 200MTps • •
NAND Flash PHY for FPGA 200MTps •
sD/s
Dio
/eM
Mc
SD 4.0 Host 312MBps • •
Combo SD/SDIO-3.0/eMMC 4.41 Host 104MBps • •
Combo SD 4.0/eMMC5.0 Host 400MBps • •
Combo SD 3.0/eMMC 5.0 PHY 400MBps •
Flash QSPI Controller 52MBps •
Table 3: Storage IP Solutions
high-Definition Display iP solutions
The saying that a picture is worth a thousand words has never been as true as it is today. High-definition display has become an integral part of any consumer device, with each product having specific display requirements, as well as needing to support industry-standard interfaces and protocols.
Recognizing this fact, the newest addition to our IP portfolio includes solutions for HDMI®, DisplayPort™, MHL™, MyDP™, DP++™, and eDP™. Our High-Definition Display IP supports the latest standard features such as 4Kx2K resolution, multiple streams, 3D video, enhanced audio, content protection, and mobility.
iP Protocols Performance
PhY
TsMc sMic
65nm 40nm 28nm 65nm
LP gP LP hPM hPc LL
co
ntr
olle
r/so
luti
on MHDP TX
HDMI1.4 3Gb per lane • • •
MHL 2.1 3Gbps •
MHDP RX
HDMI1.4 3Gb per lane • • •
MHL 2.1 3Gbps •
DP1.2 HBR , SST • • •
HDCPHDCP 1.4
HDCP 2.26Gbps per stream • • • • • •
PhY
MHDP TX
MHDP TX 6Gbps per lane •
HDP TX 3Gbps per lane • • • •
MHL TX 3Gbps per lane •
MHDP RXMHDP RX 3Gbps per lane •
HDP RX 3Gbps per lane • • •
Table 4: High-Definition Display IP Solutions
ip.cadence.com6 Design IP Brochure Version 2.2
Analog iP solutions
As an established industry leader in analog design tools, we offer some of the world’s fastest and lowest power analog IP solutions.
iP
TsMc gF sMic uMc
65nm 40nm 28nm 16nm 65nm 55nm 40nm 28nm 28nm 40nm
LP g LP g hPL hPM hPc LP FF LP g LPe LPe LP sLP hK LP
AFe
General AFE • • •
Wi-Fi AFE • • • • • • • •
LTE AFE • •
TriBand (802.11n/ac/ad) AFE • •
LTE/Advanced LTE AFE • •
AD
c a
nd
DA
c
High-speed ADC (250MSps to 3.52GSps) • • • • •
Medium-speed ADC (20 to 250MSps) • • • • • • • • •
Low-speed ADC (<10MSps) • • • • • • •
High-speed DAC (250MHz to 3.52GHz) • • •
Medium-speed DAC (20 to 250MHz) • • • • •
Low-speed DAC (<10MHz) • • • • •
Audio • •
12b 80M ADC • •
12b 160M ADC • •
12b 320M ADC • •
7b 3.52G WiGiG ADC • •
Mo
nit
or
Temp Monitoring IP • • • • • • •
Voltage Monitoring IP • • •
Pow
er/
Tim
ing LDO • • • • •
POR • • • • •
PLL/DLL • • • • • • • • • • • •
hig
h-s
pee
d s
erD
es
QSGMII/XAUI/Double XAUI • • •
PCIe3/2/1 PHY • • •
PCIe3/2/1 + SRIS + L1 sub-states PHY • • •
PCIe4 + SRIS + L1 sub-states PHY •
16G
Mut
li-
prot
oco
l PCIe2/3, USB3 •
10GKR, PCIe3, XAUI, CEI-6G •
PCIe4, USB3.1, HMC-15G-SR •
10G
Mul
ti-
prot
oco
l
PCIe2/3, USB3 • •
10GKR, PCIe3, XAUI, CEI-6G • •
6G M
utli-
prot
oco
l
PCIe2, SATA 3.1,USB3.0, MIPI M-PHY •
DisplayPort TX 1.2a, SGMII •
12.5G Chip-to-Chip PHY •
10G-KR PHY • • •
10G EPON/GPON PMA • •
SATA 3.1 PHY •
usB
USB 1.1 PHY (USB 2.0 Full Speed) • • • • • •
USB 2.0 PHY • • • • • • •
USB 3.0 PHY • • •
USB 3.0 SSIC ( M-PHY) • • • • • •
USB 2.0 HSIC PHY • • •
MiP
i M-PHY (HS-G2) • • • • •
M-PHY (HS-G3) • • •
D-PHY • • • • • • • •
Table 5: Analog IP Solutions
ip.cadence.com Design IP Brochure Version 2.2 7
systems and Peripherals iP solutions
Peripheral building blocks and efficient microprocessors have become an essential part of almost every SoC design. We offer peripheral, 8051 processor, and legacy processor IP. Our Systems and Peripherals IP solutions are architected to quickly and easily integrate into your design, with configurability and compatibility being important features. All of our peripheral IP is compatible with the ARM® AMBA® Specification, Revision 2.0.
compatibility iP Description
Peri
ph
eral
Timer
AMBA Rev. 2.0 PWM Pulse Width Modulator
AMBA Rev. 2.0 WDT Watchdog Timer
AMBA Rev. 2.0 RTC Real-Time Clock
AMBA Rev. 2.0 TTC Triple Timer Counter
Bus
AMBA Rev. 2.0 AHBC Arbiter for ARM AMBA AHB interface
AMBA Rev. 2.0 AHB2APB Bridge ARM AMBA AHB to APB Bridge IP
AMBA Rev. 2.0 APIC Advanced Peripheral Interrupt Controller
AMBA Rev. 2.0 SMC Static Memory Controller
AMBA Rev. 2.0 GPIO General Purpose I/O, provides up to 32 programmable ports
Serial Interfaces
AMBA Rev 2.0, I2C bus specification version 2.0 (100kHz and 400kHz)
I2CInter-Integrated Circuit Bus, functions as a master or slave in a multi-master, two-wire serial I2C bus
AMBA Rev 2.0, I2C bus specification version 2.0 (100kHz and 400kHz)
I2C HS Inter-Integrated Circuit Bus, High-Speed version
AMBA Rev. 2.0 SPI Serial Peripheral Interface Bus
AMBA Rev. 2.0 UART Universal Async Receiver Transmitter
Audio Connectivity
AMBA Rev. 2.0, Philips Inter-IC Sound Bus Specification (1986, revised in 1996)
I2SConfigurable single- or multi-channel Inter-IC Sound (I2S) bus interface controller
AMBA Rev. 2.0 S/PDIFUnidirectional and self-clocking interface for connecting digital audio equipment
805
1 Pr
oce
sso
r
8051 Microcontroller
Compatible with Intel® MCS® 51 instruction set
R8051XC2 Intel 8051-compatible µC, fully configurable
Compatible with Intel MCS 51 instruction set
T8051 Tiny 8051-compatible µC, very small gate count
Compatible with Intel MCS 251 instruction set
80251XCIntel 80251-compatible µC, over 12 times faster than the 80C51 from Intel
Leg
acy
Pro
cess
or
Obsolete Parts Replacement
Compatible with M68000 instruction set C68000 MC68000-compatible microprocessor
Fully compatible with TMS320C25 TMS320C25 TI TMS320C25-compatible Digital Signal Processor
Compatible with Intel 80C86 or 80C186 instruction set
C80186Series of high-performance, 16-bit microcontrollers compatible with Intel 80C186EC, Intel 80C186XL, Intel 80C186EA, with extended versions of peripherals
Compatible with i387SX instruction set C387L Intel i387SX-compatible 80-bit math co-processor
Compatible with Z80 instruction set Z80 Zilog Z80-compatible microprocessor
Improved Zilog® Z80-compatible CPU S80 Zilog Z80-compatible microprocessor, speed improved
Table 6: Systems and Peripherals IP Solutions
cadence Design systems enables global electronic design innovation and plays an essential role in the creation of today’s electronics. customers use cadence software, hardware, iP, and expertise to design and verify today’s mobile, cloud, and connectivity applications. www.cadence.com
© 2014 cadence Design systems, inc. All rights reserved worldwide. cadence, the cadence, and Denali are registered trademarks of cadence Design systems, inc. AMBA and ArM are registered trademarks of ArM Limited (or its subsidiaries) in the eu and/or elsewhere. All rights reserved. MiPi® is a registered mark of MiPi Alliance, inc. The terms hDMi and hDMi high-Definition Multimedia interface, and the hDMi Logo are trademarks or registered trademarks of hDMi Licensing LLc in the united states and other countries. MhL, Mobile high-Definition Link and the MhL Logo are trademarks or registered trademarks of the MhL, LLc. Pci-sig®, Pcie®, and Pci eXPress® are registered trademarks of Pci-sig. JeDec® and the JeDec logo are registered trademarks of JeDec solid state Technology Association. intel and Mcs are trademarks of intel corporation in the u.s. and/or other countries. ZiLog is a registered trademark of ZiLog inc. in the united states and in other countries. All others are the property of their respective holders.
cadence iP Factory Version 2.2
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