Cad Asic Extra Question

PART A

a)Explain overview of IC design.

Integrated circuit design, or IC design, is a subset of electrical engineering,

encompassing the particularlogic and circuit design techniques required to design

integrated circuits, or ICs. ICs consist of miniaturized electronic components built

into an electrical networkon a monolithic semiconductor substrate by

photolithography.

b)Explain, how far you understand how to use L-edit in the exercises.

- In the exercises to used L-Edit, I understand the user interface software of L-Edit

- Besides that, I able to identify the drawing tools available for drawing

- Also, I can understand the use of Design Rile Check in Layout verification

- Furthermore, I understand the basic steps in drawing layout in L-Edit

c)What is the Moore’s Law?

- The maximum number of transistors on a chip doubles every 18 months. As a

result the on-chip transistor count has increased one million times in three decades

and has reached 30 million transistors (in microprocessors).

Sketch the graph for the Moore’s Law.

d)Sketch the cross-section diagram for PMOS and NMOS transistor.

e)Name TWO types of packaging.

1. bare die

2. DIP

3. PGA

4. Small-outline IC

5. Quad flat pack

6. PLCC

7. Leadless carrier

f)What is the definition of the oxidation?

Heating the silicon surface in the presence of oxygen (O2) creates a layer of

Silicon Dioxide SiO2 (oxide for short) which is a very good insulator.

g)Name TWO types of oxidation and write the chemical response reaction for both

types.

h) What is the purpose of deposition?

Deposition is used to create a layer of a conducting material usually on the top of

the silicon dioxide layer. Two conducting materials are used are metal, usually

aluminum and polysilicon which is a polycrystalline silicon modified with some

metal impurities to obtain a relatively good conductance.Two common deposition

methods are Chemical Vapor Deposition (CVD) and Physical Vapor Deposition

i)State the technology (full name) and the number of transistor starting with SSI

until ULSI for the microelectric evolution.

SSI - Small Scale Integration <100 SSI 1963

MSI - Medium Scale Integration 100-3000 MSI 1970

LSI - Large Scale Integration 3000-30,000 LSI 1975

VLSI - Very Large Scale Integration 30,000-1,000000 VLSI 1980

ULSI - Ultra Large Scale Integration >1,000000 ULSI 1990

j) What is layout?

A process where engineering schematics are transposed into graphic symbols that

will be used to make a mask.

k)State FOUR governing rules in CMOS design for all logic gates.

1.For each input node, there must be 2 transistors, one P-MOS and one N-MOS.

The gate nodes of each must be electrically common. Example: Inverter – one

input, two transistor, one P-mos and one N-mos.

2. The Nmos transistors always match the logical function of the gate.

3. The Pmos transistors will always be in a complementary configuration to the

Nmos.

LayoutSchematicSymbol

4. The ordering dot on the logic symbol determine which transistor is placed

closest to the output node.

l)State TWO advantages of node sharing.

1)Minimizes cell area

Diffusion/Node sharing between two devices allows them to be placed closer

together. This plays a critical role in minimizing cell area.

2)Reduces routing congestion

Each instance of diffusion/node sharing eliminates the need for a wire to connect

the two diffusion terminals. Therefore, it plays a role in reducing routing

congestion in a cell.

3) Improves parasitics

As a result of the cell size and routing minimization, there is a parasitic (RC)

reduction. This is beneficial from an electrical standpoint.

m)What is the definition of stick diagram?

A short-hand technique for generating a free form, topological plan of a circuit

layout, without regard to actual geometry sizing or design rules. Graphical symbols

(sticks) are drawn relative to each other and are connected together by symbols

(sticks) representing interconnects mask layers.

PART B

1)Explain the contact guidelines.

There are 2 contact guidelines that is partially covered and fully covered.

Partially covered- cannot carry as much current as fully covered contact. A partially covered

contact has 0.0 metal coverage past the edge of the contact

Fully covered- A fully covered contacts has at least 0.16u coverage on all sides.

2)What are the elements of quality layout?

-meet circuit performance requirements

-efficient area usage

-manufacture-able Layout(FDM)

-Debug-able Layout(DFD)

-Fulfill Reliability guidelines.

3)State TWO rules for good quality layout.

-Poly Guidelines

-Contact Guidelines

-Diffusion guidelines

-Metal and Vias Guideliness

4)State TWO problems that occur in the layout and explain one of them.

The problem is

EM-Electromigration is a problem that occurs when current only moves in one direction and

pulls the atoms of the metal along with it.

SH-Self hear is a problem that occurs when current is alternating or not just flowing in the same

direction all the time.

5)Draw the examples to show multiple cell instances placed with the same orientation, with

flipping and no stepping.

6)State the basic hierarchies planning.

Understand constraints

Basic Wire Planning

Block sizing fundamentals

Block Placement fundamentals

Datapaths definition

Basic Datapath pitch planning

Estimating time

7)What is array and stepped cells

Array - ordered instantiation (placement) of same cell or objects in a design

Object can be a cell, group of cells, or other structure

Objects are related, physically and logically

Array can extend in X and/or Y direction

Stepped cells

-The example below shows multiple cell instances placed with the same orientation (no flipping)

and same distance between neighbors.

The origin of the instantiated cell is determined by the small triangle in the lower left

corner.

Origin at X:0, Y:0 of child cell

8)State THREE methodologies for designing and planning.

Top down

Bottom-up

Middle-out

9)Explain about the bottom up planning.

In bottom-up planning the area of focus is on leaf cells or cell studies (layouts done early

in the project).

This planning is used after the cluster level planning is finished.

Repeated structures such as datapath, memory arrays and decoders are sized to help with

the final sizing of each block.

10)List down the steps for block planning.

1. How does this block fit into the unit relative to other blocks?

2. What direction should metal levels run?

3. Is there a pitch that must be followed? Almost all datapath blocks will have a fixed pitch.

4. Is there a template cell or pin ring from the top level plan available?

5. Is there a pre-determined cell size that is expected to be met?

6. What is the layout of the power network?

7. Clock network - gate alignment requirements/widths/shielding

8. Are there any feedthroughs going through the block?

9. Where are the outputs going to and where are the inputs coming from?

10. Draw a stick plan of the cell, using all the above information that has been acquired.

11) What are the advantages of signal planning?

Proper signal planning is essential in minimizing area. It is also important from an

engineering perspective, as certain critical signals will require special considerations for

speedpath reasons.

Parasitic information

Metal Layers

Metal Widths/spacings

Shielding

12) Explain about the shielding and draw the example if the signal is fully shielded.

Shielding is accomplished by surrounding the signal with power (therefore non-switching)

signals (VCC/VSS), either on the same layer as the signal (lateral shielding) or adjacent layers

(vertical shielding).

Noise-sensitive signals may also be protected from electrical coupling by shielding.

Example: Signal is fully shielded.

13) Give THREE advantages of auto place and route.

Ability to handle digital designs of 10+ million gates flat

Extremely fast turnaround time in achieving design closure

Integrated power planning, analysis, and routing for full-chip power structure

Easy-to-use clock tree synthesis handles multiple and reconvergent clocks

14) State the steps for standard routing flow and explain one of them.

Detail Route

Run time is longer.

Performed DR correction. DR might reduced 50% or more but will not clean DR for the

design.

Search and Repair

Performed DR correction to the tool limitation.

15) Explain about ESD?

ESD is like a miniature lightning bolt. When lightning strikes, it is because charge

concentrations in the clouds create strong electric fields with respect to earth. When the potential

is high enough, lightning occurs.

A similar situation exists with ESD, albeit on a much smaller scale. When a person

becomes triboelectrically charged (i.e., through friction), a difference in potential exists between

that person and nearby conductive objects. When that potential exceeds the breakdown voltage

of the intervening air, an electrostatic discharge results.

16) What are the solution of ESD protection and sketch the circuit to show them.

A typical solution of the ESD protection problem is to use clamping diodes implemented

using MOS transistors with gates tied up to either GND for nMOS transistors, or to VDD for

MOS transistors as shown in figure below.

17)What is the effect of latch up?

Large MOS transistor are susceptible to the latch-up effect. In the chip substrate, at the

junctions of the p and n material, parasitic pnp and npn bipolar transistors are formed as in the

following cross-sectional view:

18)State THREE guidelines for avoiding latch up.

Use p+ guard rings connected to ground around nMOS transistors and n+ guard rings

connected to VDD around pMOS transistors to reduce Rw and Rsub and to capture injected

minority carriers before they reach the base of the parasitic BJTs.

Place substrate and well contacts as close as possible to the source connections of MOS

transistors to reduce the values of Rw and Rsub.

Use minimum area p-wells (in case of twin-tub technology or n-type substrate) so that the

p-well photocurrent can be minimized during transient pulses.

Source diffusion regions of pMOS transistors should be placed so that they lie along

equipotential lines when currents flow between

19)Draw the full chip in development cycle.

20)What are the full chip components?

The actual product design is done. All layout work completed. Design timing/power

requirements etc. met. Full chip layout assembled and verified. Database sent for fracturing.

Circuit layout is translated into Electron Beam (E-beam) readable data for process of mask

generation by Fab

Release of Fracture data to Mask vendors, this is the start of manufacturing of the product

21)Explain THREE types of tape out?

New Product: A-stepping. (first time, brand new: A0)

New Stepping: B0, C0, A full set with design change to an existing product. All layers

are taped out.

Retrofit (Dash stepping):A1, A2, B1, B2 ... Some layers are modified on an existing

product. Only those layers that are changed are taped out.

22)Draw the flow for tape out process.

1. Create Golden DB

2. Run Fullchip Verification jobs in parallel (e.g. 22 jobs)

3. FC verification results analyzed, debugged and fixed.

4. Send Stream file (GDSII) to Tapeout Team for fracturing and release to Mask Shop for mask

generation.

5. Archive the Whole Data-Base and tools.

23)State TWO Optical Proximity Corrections (OPC) guidelines.

Minimize the total number of jog segments

Device layout

Dummification

Avoid small jog segments

Interior corners on opposite sides of same line

Avoid interior diffusion corners next to gates

Minimize such occurrences

Avoid “horseshoe” layouts

Increase spacing between end of line segment and opposite feature

PART C

1) Given the Boolean equation below:

Z=( A+B ).(C .D )

Sketch the transistor level circuit usiing CMOS static logic.

Answer:

Z = (A + B) (CD)

= (A + B) + (CD)

2) Sketch the stick diagram for the logic gates below:

Answer:

3)How many nodes in the schematic below?

Answer:

5 nodes:

Vout

Vin

Vout2

Vdd

Vss