C3 / MAPLD2004 Lake 1 Radiation Effects on the Aeroflex RadHard Eclipse FPGA Ronald Lake Aeroflex Colorado Springs
Dec 22, 2015
C3 / MAPLD2004Lake 1
Radiation Effects on the Aeroflex RadHard Eclipse FPGA
Ronald Lake
Aeroflex Colorado Springs
C3 / MAPLD2004Lake 2
RadHard Eclipse Radiation Effects Overview
• Test Techniques
• Single Event Effects Results
– Single Event Upset
– Single Event Latch-up
• Total Ionizing Dose
– DC Characteristics
– AC Characteristics
• TMR Effects on SEU
• Summary
C3 / MAPLD2004Lake 3
Hardness Testing Conditions - SEE
• SEU - 25oC, 2.25V core and 3.0V I/O, in accordance with EIA/JESD57
• SEU - FPGA programmed (configured) with three data storage components
– Dynamic Shift Registers - Two at 560 bits
– Static Register File - 64 x 16 bits
– Static RAM - 55,296 bits
• SEL - 125oC, 2.7V core and 3.6V I/O, in accordance with EIA/JESD57
• 208-lead ceramic quad flat-pack (CQFP)
C3 / MAPLD2004Lake 4
Hardness Testing Conditions - SEU
• Alternating ones and zeros data used for all three storage components of the FPGA
• National Instruments tester at 1MHz frequency
– Write/read shift register
– Read only register file and RAM
– After a cell upsets, the correct data is re-written to the cell
• Texas A&M University Cyclotron Institute
– Au, Kr, and Ar from 0o (normal incidence) to 60o
C3 / MAPLD2004Lake 6
Hardness Testing Conditions - SEL
• Devices statically biased during irradiation
– Supply currents monitored for latch-up
• Lawrence Berkeley National Laboratory
– Au at 41o
– Effective fluence at 1E7 ions/cm2
– Effective LET = 120 MeV-cm2/mg
• Devices functionally re-verified after irradiation
C3 / MAPLD2004Lake 8
Hardness Testing Conditions - TID
• Irradiated under worst case temperature (25oC) and static bias conditions (max VDD) per MIL-STD-883E Method 1019
• FPGA programmed with 60 AC paths
• J.L. Shepherd model 81-22 Cobalt 60 gamma cell
C3 / MAPLD2004Lake 10
Single Event Upset Data Plot
1.0E-10
1.0E-09
1.0E-08
1.0E-07
1.0E-06
0 20 40 60 80 100
LET (MeV-cm2/mg)
Cro
ss-s
ecti
on
(cm
2/b
it)
Register File
RegF Weibull
Shift Reg
ShiftR Weibull
RAM
RAM Weibull
C3 / MAPLD2004Lake 11
Hardness Results - SEE
SEU - Error-rates - GEO orbit, Adam’s 90% WC
FPGAComponent
Temp(C)
VDDCore & I/O
(V)
Numberof storage
cells
WeibullShape
WeibullWidth
SaturatedX-section
(cm2/bit)
Onset LET
MeV-cm2/mgError-rate
(errors/bit-day)
RegF 25 2.25/3.00 1,024 1.4 90 2.0E-07 20 4.7E-09ShiftR 25 2.25/3.00 1,120 1.4 55 4.0E-07 14 3.6E-08RAM 25 2.25/3.00 55,296 1.95 125 9.0E-08 17.5 6.3E-10
SEL - No latch-up to 120 MeV-cm2/mgConditionsVDD I/O, VDD
Core, TempSN Ion
Normal LET, MeV-cm²/mg
Angledegrees
Flux
ions/cm2-sLatchup
Fluence (normal)
ions/cm2
Effective Fluence
ions/cm2
Effective LET MeV-cm²/mg
3.6, 2.7, 125C 24 Au 90.3 41 7.8E+04 0 1.3E+7 1.0E+7 1203.6, 2.7, 125C 10 Au 90.3 41 6.9E+04 0 1.3E+8 1.0E+8 1203.6, 2.7, 125C 22 Au 90.3 41 6.0E+04 0 1.3E+7 1.0E+7 1203.6, 2.7, 125C 2 Au 90.3 41 6.3E+04 0 1.3E+7 1.0E+7 120
TID - 113 rads(Si)/s
FPGA meets datasheet ACs and DCs post 300 krad(Si)
C3 / MAPLD2004Lake 12
Hardness Results - TID - Supply Current DCs
Temp(C)
Test ConditionVDD
Core (V)VDD
I/O (V)Units Pre-rad
Post100k rad
Post300k rad
Delta100k - Pre
Delta300k - Pre
25 QIDD 2.7 3.6 mA 0.19 0.2 3.5 0.01 3.3125 AIDD 1 MHz 2.7 3.6 mA 198 203 631 5 43325 AIDD 5 MHz 2.7 3.6 mA 304 309 732 5 42825 AIDD 10 MHz 2.7 3.6 mA 437 442 860 5 42325 AIDD 20 MHz 2.7 3.6 mA 688 688 1110 0 42225 AIDD 50 MHz 2.7 3.6 mA 1393 1402 1770 9 37725 AIDD 100 MHz 2.7 3.6 mA 1660 1643 1813 -17 153
Most Shifted DCs - Post radiation minus Pre-rad
C3 / MAPLD2004Lake 13
Hardness Results - 100 krad(Si) TID - ACs
5 most shifted ACs on each of 2 devicesPost 100 krad(Si) minus Pre irradiation
SN Temp TestVDD
Core (V)VDD
I/O (V)Units Pre-rad
Post100 krad
Post-Pre%
Change25 25 TPLH_sr_16_2_a21 2.5 3 ns 7.73 7.66 -0.07 -0.9625 25 TPHL_sr_16_2_a21 2.5 3 ns 9.08 8.98 -0.09 -1.0225 25 TPLH_sr_16_2_f21 2.5 3 ns 7.47 7.38 -0.09 -1.2425 25 TPHL_sr_16_2_qb2 2.5 3 ns 5.62 5.54 -0.07 -1.3225 25 TPHL_sr_16_2_qa2 2.5 3 ns 5.57 5.50 -0.07 -1.3326 25 TPHL_sr_16_2_qa2 2.7 3.6 ns 5.14 5.13 -0.07 -1.2526 25 TPHL_sr_16_2_a21 2.5 3 ns 9.08 9.17 -0.12 -1.3026 25 TPHL_sr_16_2_f21 2.5 3 ns 8.55 8.71 -0.14 -1.5726 25 TPHL_sr_16_2_qb2 2.5 3 ns 5.62 5.67 -0.10 -1.7726 25 TPHL_sr_16_2_qa2 2.5 3 ns 5.57 5.56 -0.10 -1.80
C3 / MAPLD2004Lake 14
Hardness Results - 300 krad(Si) TID - ACs
SN Temp TestVDD
Core (V)VDD
I/O (V)Units Pre-rad
Post300 krad
Post-Pre%
Change25 25 TPLH_inv_ch_i3_t 2.5 3 ns 152.1 160.8 8.7 5.725 25 TPLH_inv_ch_i2_t 2.5 3 ns 155.4 164.3 8.9 5.725 25 TPHL_inv_ch_i1_t 2.5 3 ns 154.6 163.4 8.8 5.725 25 TPHL_nand16_o2 2.5 3 ns 52.8 55.7 2.9 5.525 25 TPHL_nand16_o0 2.5 3 ns 52.2 55.1 2.9 5.526 25 TPLH_inv_ch_i2_t 2.5 3 ns 156.7 163.8 7.1 4.526 25 TPHL_inv_ch_i1_t 2.5 3 ns 155.8 162.8 7.0 4.526 25 TPHL_sr_d_so 2.5 3 ns 5.9 6.1 0.3 4.426 25 TPLH_inv_ch_i3_t 2.5 3 ns 153.3 160.0 6.7 4.426 25 TPLH_inv_ch_i2_t 2.7 3.6 ns 144.4 150.0 5.7 3.9
5 most shifted ACs on 2 devicesPost 300 krad(Si) minus Pre irradiation
C3 / MAPLD2004Lake 15
RadHard Eclipse Single Voter TMR
MUX4x0
S0S1
I722
I723
I724
I725
I726
I727
I728
I729
I730
I731
I732
I733
I734
I735
I736
I737
I738
I739
DFFPC
I713
CLR
D
PRE
Q
DFFPC
I714
CLR
D
PRE
Q
DFFPC
I715
CLR
D
PRE
Q
DFFPC
I51
CLR
D
PRE
Q
DFFPC
I61
CLR
D
PRE
Q
DFFPC
I71
CLR
D
PRE
Q
SHIFT_REG_TMR_200
6/19/2004 10:35:40 AM
UT6325_SEE_TOP
UT6325_SEE_TOP.I183
w_set w_set w_set w_setw_reset w_reset w_reset w_reset
N_1
w_dedclk w_dedclk w_dedclk w_dedclkw_set w_set w_set w_set
w_reset w_reset w_reset w_reset
N_1 .I183-q4
w_dedclk w_dedclk w_dedclk w_dedclkw_set w_set w_set w_set
w_reset w_reset w_reset w_reset
N_1
w_dedclk w_dedclk w_dedclk w_dedclk
C3 / MAPLD2004Lake 16
RadHard Eclipse Single Voter Data
123ABMUX4x0S0S1I722I723I724I725I726I727I728I729I730I731I732I733I734I735I736I737I738I739DFFPCI713CLRDPREQDFFPCI714CLRDPREQDFFPCI715CLRDPREQDFFPCI51CLRDPREQDFFPCI61CLRDPREQDFFPCI71CLRDPREQSHIFT_REG_TMR_2006/19/200410:35:40 AMUT6325_SEE_TOPUT6325_SEE_TOP.I183w_setw_setw_setw_setw_resetw_resetw_resetw_resetN_1w_dedclkw_dedclkw_dedclkw_dedclkw_setw_setw_setw_setw_resetw_resetw_resetw_resetN_1 .I183-q4w_dedclkw_dedclkw_dedclkw_dedclkw_setw_setw_setw_setw_resetw_resetw_resetw_resetN_1w_dedclkw_dedclkw_dedclkw_dedclk
* Estimate based on assumed onset LET of 100 and saturated x-section of 7E-9
FPGAComponent
Temp(C)
VDDCore & I/O
(V)
WeibullShape
WeibullWidth
SaturatedX-section
(cm2/bit)
Onset LET
MeV-cm2/mgError-rate
(errors/bit-day)
No TMR 25 2.25/3.00 1.4 55 4.0E-07 14 3.6E-08TMR Single Voter 25 2.25/3.00 1.8 25 7.0E-08 64 2.3E-10TMR Triple Voter * 25 2.25/3.00 1.8 25 7.0E-09 100 5.3E-15
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
0 20 40 60 80 100
LET (MeV-cm 2/mg)
Cro
ss S
ecti
on
(cm
2 /
bit
)
No TMR Shift Register
No TMR Weibull
TMR Single Voter
TMR SV Weibull
No errors at LET of 64
MeV-cm2/mg. Not tested between LET of 64 and 90 MeV-cm2/mg
Error-rates based on SpaceRadiation 4.0 Weibull analysis, Geo orbit, Adam’s 90% WC environment
C3 / MAPLD2004Lake 17
RadHard Eclipse Single Voter Data
123ABMUX4x0S0S1I722I723I724I725I726I727I728I729I730I731I732I733I734I735I736I737I738I739DFFPCI713CLRDPREQDFFPCI714CLRDPREQDFFPCI715CLRDPREQDFFPCI51CLRDPREQDFFPCI61CLRDPREQDFFPCI71CLRDPREQSHIFT_REG_TMR_2006/19/200410:35:40 AMUT6325_SEE_TOPUT6325_SEE_TOP.I183w_setw_setw_setw_setw_resetw_resetw_resetw_resetN_1w_dedclkw_dedclkw_dedclkw_dedclkw_setw_setw_setw_setw_resetw_resetw_resetw_resetN_1 .I183-q4w_dedclkw_dedclkw_dedclkw_dedclkw_setw_setw_setw_setw_resetw_resetw_resetw_resetN_1w_dedclkw_dedclkw_dedclkw_dedclk
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
0 20 40 60 80 100 120
LET (MeV-cm2/mg)
Cro
ss S
ecti
on
(cm
2 / b
it)
030927 BNL
Weibull
030927 QL BNL
031106 LBNL
031212 LBNL
040629 SN A
040629 SN B
040629 SN C
040629 SN D
040219 BNL
BNL QL FPGA
8/17/4 TMR2 Data : TAMU
C3 / MAPLD2004Lake 18
Summary
• Completed RadHard Eclipse FPGA pre-qualification evaluation of radiation performance– Low Single Event Upset error rate (geosynchronous orbit,
Adams 90% worst case environment)– Single Event Latch-up immune to > 108 MeV-cm2/mg– Passes datasheet parameters to > 300 krad(Si) Total
Ionizing Dose– TMR design maps well to logic cell architecture
• Offered as a flight qualified QML Q & V RadHard Standard Microcircuit Drawing device