C2000 Digital Power Supply Workshop - epc.com.cn Controller (Compensator) ... CNTL_Fdbk1 = &Vout; ADC_Rslt1 = &Vout; Dual Buck Example. ... • CBu trigger for ADC SOC RUN-time

C2000 Digital Power Supply Workshop

Texas Instruments

Technical Training

Copyright © 2008 Texas Instruments. All rights reserved.

D SPTEXAS INSTRUMENTS

TECHNOLOGY

Introduction to Digital Power Supply Design

What is a Digital Power Supply?

Why use Digital Control Techniques?

Peripherals used for Digital Power Supply Design

Development Tools and Software

What is Digital Power?Generic Power System Block Diagram

The controller block is what differentiates between a digital power system and a conventional analog power system

Switches(FETs)

LCNetwork

Controller(Compensator)

VoutPWM

Vin

Why Digital Control Techniques?

ControllerAnalog

orDigital ??

PWM

Sensor(s)

Bandwidth limitations (sampling loop)

PWM frequency and resolution limits

Numerical problems (quantization, rounding,…)

AD / DA boundary (resolution, speed, cost)

CPU performance limitations

Bias supplies, interface requirements

Component drift and aging / unstable

Component tolerances

Hardwired / not flexible

Limited to classical control theory only

Large parts count for complex systems

Insensitive to environment (temp, drift,…)

High reliability

S/w programmable / flexible solution

Precise / predictable behavior

Advanced control possible (non-linear, multi-variable)

Can perform multiple loops and “other” functions

High bandwidth

High resolution

Easy to understand / use

Historically lower cost

+

Digital ControllerAnalog Controller

Power Elec.

Benefits of Digital Control

Eliminate Components

PFCFilter Bridge

VV DC/DC

Aux P/S

Output

Multiple chips for control

Micro-controller for supervisory

Dedicated design

Traditional Analog Power Supply

V PFCFilter Bridge

VV

Aux P/S

V

DC/DCConverterControl

Multi-modePower control

MCUSupervisoryHousekeeping

Circuits

Current/LoadSharingControl

DC/DC V

To Host

PFC Control

InterfaceCircuit

Monitor(MCU?)

Inrush/Hot-plug Control

I I I I Output

PFC Control

InterfaceCircuit

Monitor(MCU)

Inrush/Hot-plug Control

DC/DCConverterControl

Multi-modePower control

MCUSupervisoryHousekeeping

Circuits

Current/LoadSharingControl

Reduce Manufacturing Cost

Variable DC Output

Better Performance Across Corners

Failure Prediction

One Device, Multiple DC Outputs

One Design, Multiple Supplies

Digital controller enables multi-threaded applications

8 4

5 1

Analog Control System

+

+=

sCR

sCR

R

RsC

22

11

1

2

1

1)(

)()()()()(

012

2

23

3

tftykdt

tdyk

dt

tydk

dt

tyd=+++

Differential equations1st, 2nd, 3rd,…order

Need to find:R1, R2, C1, C2

Laplace Transform

“Analog Computation”Differential equations

Digital Control System

)()1()2(

)1()2()(

012

12

nEbnEbnEb

nUanUanU

⋅+−⋅+−⋅

+−⋅+−⋅=

)()()( nWnRnEwhere −=Κ

)()()()()(

012

2

23

3

tftykdt

tdyk

dt

tydk

dt

tyd=+++

Differential equations1st, 2nd, 3rd,…order

Difference equation

Need to find:a1, a2, b0, b1, b2

Laplace Transform

Z TransformOR

Time Sampled Systems

Processor Bandwidth

Sample Freq (=PWM) Sample Period

(kHz) (ns)

100 10000

300 3333

500 2000

700 1429

1000 1000

1500 667

2000 500

Time Division Multiplexing (TDM)

Control Code (C2)Processor 2 ControlControl Code

y(n)

x(n)



Single CPU C1 C2 C3 C1 C2 C3 C1 C2 C3

TSAMPLE

Digitally Controlled Power Supply

DAC(PWM)

ADC

DSC

0110101100

1011011101

0010100111

“Plant”

“High fidelity”

Translation boundary

System Mapping

Fast program execution out of both RAM and Flash memory

85 MIPS with Flash Acceleration Technology

100 MIPS out of RAM for time-critical code

Memory Sub-System

Up to 6 ePWM, 4 eCAP, and 2 eQEP

Ultra-Fast 12-bit ADC

6.25 MSPS throughput

Dual sample&holds enable simultaneous sampling

Auto Sequencer, up to 16 conversions w/o CPU

Control Peripherals

Multiple standard communication ports provide simple interfaces to other components

Communications Ports

100MIPS performance Single cycle 32 x32-bit MAC (or dual 16 x16 MAC) Very Fast Interrupt Response Single cycle read-modified-write

High Performance DSP (C28xTM

Core)

Memory Bus

64Kw Flash+ 1Kw OTP

4Kw Boot ROM

18Kw RAM

Code security

32-bit

Register

FileReal-Time

JTAG

32-bitTimers (3)

100 MIPs C28xTM 32-bit DSP

32x32-bitMultiplier

RMW

Atomic

ALU

Interrupt Management

ePWM

eCAP

eQEP

12-bit ADC

Watchdog

CAN 2.0 B

I2C

SCI

SPI

GPIO

Perip

hera

l Bu

s

Datasheet available at: http://www-s.ti.com/sc/ds/tms320f2808.pdf

TMS320F280x

Single-cycle 32-bit multiplier makes computationally intensive control algorithms more efficient

Three 32-bit timers support multiple control loops / time bases

Single cycle read-modified-write in any memory location and 32-bit registers improve control algorithm efficiency

Real-time JTAG debug shortens development cycle

Fast & flexible interrupt management significantly reduce interrupt latency

C28xTM DSP Core

C28xTM

32-bit DSP


32-bit

Register

FileReal-Time

JTAG

32-bitTimers (3)

32x32 bitMultiplier

RMW

Atomic

ALU

Efficient 32-bit Processor Capability

# Instructions vs PWM

MIPS = Million Instruction Per Second

PWM freq. PWM per. Processor MIPS(kHz) (µµµµs) 100 150

50 20.0 2000 3000100 10.0 1000 1500200 5.0 500 750250 4.0 400 600300 3.3 333 500500 2.0 200 300750 1.3 133 200

1000 1.0 100 150

Control Code spare

TPWM

CPU Control

PWM

Control Code spare

ePWM “DAC” Capability

Control PeripheralsePWM

ePWM

Number of channels scalable and resources allocated per channel

Two independent PWM outputs per module

Dedicated time-base timer Two independent compare

registers Multi-event driven waveform Trip zones and event interrupts F2808 offers 6 modules Provides ePWM DAC capability

for DPS Switching can be programmed

as Asymmetric or Symmetric PWM

High-Resolution PWM mode

Time-Base

CounterCompare

Acti

on

Qu

alifi

er

DeadBand

PWMChop

TripZone

EventTrig.& Int.

EPWMxA

EPWMxB

PWM effective resolution (CPU=100MHz)

PWM Standard PWM

(kHz) bits % bits %

50 11.0 0.05 17.0 0.0007

100 10.0 0.10 16.0 0.0015

150 9.4 0.15 15.4 0.0022

250 8.6 0.25 14.7 0.0037

500 7.6 0.50 13.7 0.0075

750 7.1 0.75 13.1 0.0112

1000 6.6 1.00 12.7 0.0150

HR-PWM

Control Peripherals

Fast & Flexible 12-bit 16-Channel ADC


Dual sample/hold enable simultaneous sampling or sequencing sampling modes

Analog input: 0V to 3V

16 channel, multiplexed inputs

Auto Sequencer supports up to 16 conversions without CPU intervention

Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer

Sixteen result registers (individually addressable) to store conversion values

12-bit ADC Capability

8 ADCInputs

ResultRegisters

16 words

AnalogMUX

Prescaler

S/HA

12-bitADC

Module8 ADC Inputs

SYSCLK

Start of Conversion Auto Sequencer

ADC

S/HB

AnalogMUX

ADC Utilization:# Channels (“Loops”) vs. PWM frequency

MSPS = 3 MSPS = 6.25

PWM # Channels PWM # Channels

(kHz) (kHz)

125 24 125 50

250 12 250 25

500 6 500 13

750 4 750 8

1000 3 1000 6

Code Composer Studio

Project Manager:

Source & object files

File dependenciesCompiler, Assembler &

Linker build options

Full C/C++ & Assembly Debugging:

C & ASM Source

Mixed modeDisassembly (patch)Set Break Points

Set Probe Points

Editor:

Structure Expansion

HelpCPU

Window

Memory WindowGraph Window

Status Window

Watch Window

Menus or Icons

Software Library Approach

DPS software libraries available at: www.ti.com/dpslib

Modular Software Architecture

“Signal Net” based module connectivity

// pointer & Net declarations

Int *In1A, *In1B, *Out1, *In2A,...

Int Net1, Net2, Net3, Net4,...

// “connect” the modules

In1A=&Net1; In1B=&Net2; In2A=&Net3; In3A=&Net4; // inputs

Out4=&Net8; Out5=&Net9; // outputs

Out1=&Net5; In4A=&Net5; // Net5

Out2=&Net6; In4B=&Net6; // Net6

Out3=&Net7; In4C=&Net7; In5A=&Net7; // Net7

; Execute the code

f1

f2

f3

f4

f5

Initialization timeRun time - ISR

Peripheral Drivers

Depends on:

• PWM frequency

• System clock frequency

Depends on:

• # ADC bits (10 / 12 ?)

• Unipolar, Bipolar ?

• Offset ?

CPU dependency only:

• Math / algorithms

• Per-Unit math (0-100%)

• Independent of Hardware

// pointer & Net declarations

int *CNTL_Ref1, *CNTL_Fdbk1, *CNTL_Out1;

int *BUCK_In1, *ADC_Rslt1;

int Vref, Duty, Vout;

// “connect” the modules

CNTL_Ref1 = &Vref;

CNTL_Out1 = &Duty; BUCK_In1 = &Duty;

CNTL_Fdbk1 = &Vout; ADC_Rslt1 = &Vout;

Dual Buck Example

Software Block Execution

Lab1: Exploring the Development Environment

Navigate CCS features

Understand DPS library structure

Generate and visualize PWM waveforms

ActiveLoad

VoltMeter

TI PowerTrainPTD08A010W10A module

Current meas. Temp meas Over Current Prot. Over Current Flag No Heat-sink needed

Phase LinksLEDs

controlCard 2808

Simple Open-Loop Diagram

Each peripheral module has the same structure

Scaleable PWM Peripherals

Resources allocated on a per channel basis

Each channel (module) supports 2

independent PWM outputs (A&B)

# Channels easily scaleable – software reuse

Time-base synch feature for all channels

6 modules (12 PWM outputs) on F2808

Key features:

Phase & edge control

New counting modes

Independent deadband

Flexible trip-zones

High frequency chopper mode

ePWM Module Block Diagram

Module Sync and Phase Control

0000

FFFFh

TBPRD

TBCTR

time

CTR=Zero

(SycnOut)

Master Module

Phase = 120o

0000

FFFFh

TBPRD

time

SyncIn

Slave Module

TBPHS

600 600

600 600

200 200

TBCTR

Action Qualifier Module (AQM)

Multi event driven waveform generator

Events drive outputs A and B independently.

Full control on waveform polarity

Full transparency on waveform construction

S/W forcing events supported

All events can generate interrupts & ADC SOC

Key Features

TBCTR

Period

CMPB

CMPA

Zero

PRD

CBu CBd

CAu CAd

ZRO

Simple Waveform Construction

EPWM1A

EPWM2A

EPWM1B

EPWM2B

TZ1

TZ2

TZ3

ECAP1

‘2808

I1

I2

Iin

IsetSD

IsetCL1

IsetCL2

CL1

CL2

ShutDown

Fault Management Support

Trip Zones:

6 independent zones (TZ1~TZ6)

Force High, Low or HiZ on trip

One-time trip catastrophic failure

Cycle-by-cycle current limit mode

TZ1~TZ6 can trigger interrupt

Multi-Phase Interleaved (MPI)

Switching Requirements – MPI

INIT-time

• Period (1,2,3)

• CAu Action (1,2,3)

• PRD Action (1,2,3)

• Phase (2,3)

• PRD Interrupt (1)

• CBu ADC SOC (1,2,3)

• Dead-band

RUN-time

• CMPA (1,2,3)

• CMPB (1,2,3)

• Asymmetrical PWM case

• Complementary output

generated by dead-band unit

• CMPB triggers ADC SOC

Half H-Bridge (HHB)

Switching Requirements – HHB

• Up/Down Count

• Asymmetrical PWM

• dead-band on A only

• 50 % max Modulation

(controlled by CMPA)

INIT-time

• ZRO Action (A,B)

• CAd Action

• CAu Action

• CBd ADC trigger

• CBd ADC trigger

• DBRED

RUN-time

• CMPA

• CMPB (optional)

Compare A modulation range:

0 < CMPA < ( PRD – ½ x DBRED )

Phase Shifted Full Bridge (PSFB)

Switching Requirements – PSFB

• Asymmetrical PWM

• Using dead-band module

• Phase (Φ) is the control variable

• Duty fixed at ~ 50%

• RED / FED control ZVS trans.

i.e. via resonance

• CMPB can trigger ADC SOC

INIT-time

• Period (1,2)

• CMPA (1,2) ~ 50%

• CAu action (1,2)

• ZRO action (1,2)

• CBu trigger for ADC SOC

RUN-time

• Phase (2) – every cycle

• FED / RED (1,2) – slow loop

Software Driver Module – ZVSFB

Software Driver Module – PFC2PHIL

Lab2: PWM Generation / Open-Loop Control

Control Buck output voltage using simple PWM duty cycle adjustment without feedback

Use CCS watch window and slider button features to conveniently adjust PWM duty cycle

Workshop Outline

1. Introduction to Digital Power Supply Design Lab: Exploring the Development Environment

2. Driving the Power Stage with PWM Waveforms Lab: PWM Generation / Open-Loop Control

3. Controlling the Power Stage with Feedback Lab: Closed-Loop Control

4. Tuning the Loop for Good Transient Response Lab: Tuning the Loop

5. Summary and Conclusion

Controlling the Power Stage with Feedback

Closed-Loop System Block Diagram

Analog-to-Digital Converter Module

Digital Buck Controller

High Resolution PWM Benefits

Soft Start – Starting the Loop

The “Closed-Loop”

UoutRef

FB

Control

“2P2Z” Vin

Vout

Power

Stage

Vset

“Loop”

Duty

Feedback

A

D

C

H

WRslt

“ADC”

DRV

E

P

W

M

H

WIn

“PWM”

DRV

ADC Module Block Diagram

12-bit A/D

Converter

Result

Select

Result MUX

RESULT0

. .

.

RESULT1

RESULT2

RESULT15

Ch Sel (CONV00)

Ch Sel (CONV01)

Ch Sel (CONV02)

Ch Sel (CONV03)

Ch Sel (CONV15)

...

MAX_CONV1

Autosequencer

Start Sequence

Trigger

SOC EOC

Software

ePWM_SOC_A

ePWM_SOC_B

External Pin(GPIO/XINT2_ADCSOC)

Analog MUX

MUX

A

ADCINA0ADCINA1

ADCINA7

...

MUX

B

ADCINB0ADCINB1

ADCINB7

...

S/H

A

S/HMUX

S/H

B

C RLVin

Vo

PWM ADC

Vr

Digital

Controller

+Gc(z) +

Kd

U(n) E(n)

Digital Control of Power Converter

2

2

1

1

2

2

1

10

1)(

−−

−−

−−

++=

zAzA

zBzBBzGc

∆Vs

∆Vc

∆D

Power Converter

KdVo

adcVref

⋅= max

_

)2()1()2()1()()( 21210 −+−+−+−+= nUAnUAnEBnEBnEBnU

∆Vc

∆Vc

Vo levels (DPWM duty

ratio steps)

steady state output,

limit cycle

Vref

∆Vs∆Vs

0000-0001

+0001+0010

error binsADC levels

Volt

time

Steady State Limit Cycle

steady state output,

no limit cycle

Vref

∆Vc

∆Vs∆Vs

0000-0001

+0001+0010

error binsADC levels

Volt

time

Vo levels (DPWM duty

ratio steps)

Digital Control of Power Converter

High Frequency PWM

t

V

F2808 – SysClk = 100 MHz

VSTEP

PWM resolution = Log2 ( TPWM / TSysClk )

TSysclk

PWM Freq Regular resolution High resolution

(kHz) (bits) (%) (bits) (%)

200 9.0 0.2 14.8 0.004

250 8.6 0.3 14.4 0.005

300 8.4 0.3 14.2 0.005

500 7.6 0.5 13.4 0.009

750 7.1 0.8 12.9 0.014

1000 6.6 1.0 12.4 0.018

1500 6.1 1.5 11.9 0.027

2000 5.6 2.0 11.4 0.036

High Resolution PWM (HRPWM)

Significantly increases the resolution of conventionally derived digital PWM

Uses 8-bit extensions to Compare registers (CMPxHR) and Phase register (TBPHSHR) for edge positioning control

Typically used when PWM resolution falls below ~9-10 bits which occurs at frequencies greater than ~200 kHz (with system clock of 100 MHz)

Not all ePWM outputs support HRPWM feature (see device data manual)

PWM Period

Device Clock(i.e. 100MHz)

Regular

PWM Step

(i.e. 10ns)

HRPWM

Micro Step (~150ps)

HRPWM divides a clock cycle into smaller steps

called Micro Steps

(Step Size ~= 150ps)

ms ms ms ms ms ms

Calibration Logic

Calibration Logic tracks the number of Micro Steps per

clock to account for variations caused by Temp/Volt/Process

Resolution Loss – Low Duty Utilization

V out0.8 1 1.2 1.8 2.5 3.3 5

Vin14 4.1 3.8 3.5 3.0 2.5 2.1 1.5

12 3.9 3.6 3.3 2.7 2.3 1.9 1.3

10 3.6 3.3 3.1 2.5 2.0 1.6 1.0

9 3.5 3.2 2.9 2.3 1.8 1.4 0.8

8 3.3 3.0 2.7 2.2 1.7 1.3 0.7

7 3.1 2.8 2.5 2.0 1.5 1.1 0.5

6 2.9 2.6 2.3 1.7 1.3 0.9 0.3

Resolution loss in bits

Benefit of High Resolution PWM

HiRes PWM (150ps) Regular PWM (10ns)

Edge control is precise Edge jumps around

Limit cycle problemNo Limit cycle

Managing the “Closed-Loop”

Coeff - B2

Coeff - B1

Coeff - B0

Coeff - A2

Coeff - A1

Coeff set 3

Coeff - B2

Coeff - B1

Coeff - B0

Coeff - A2

Coeff - A1

Coeff set 2

UoutRef

FB

Control

“2P2Z”

Vset

Duty

Feedback

Open/Closed

Loop

SSartSEQ

Delay

OutSlope

Target

Duty

Clamp

Dead

Band

Fault

Trip

Coeff - B2

Coeff - B1

Coeff - B0

Coeff - A2

Coeff - A1

Coeff set 1

A

D

C

H

WRslt

“ADC”

DRV

E

P

W

M

H

WIn

“PWM”

DRV

Simple User Interface Control

Soft-Start and Sequencing Multi Vout

Example: Closed-Loop Control

Regulate the Buck output by using Voltage Mode Control (VMC) with closed-loop feedback

Soft-start and sequencing function used to ensure an “orderly”voltage ramp-up/down

Soft-start profile and target voltage is conveniently adjusted by using the CCS watch window and slider buttons feature

Workshop Outline






Tuning the Loop for Good Transient Response

Digital Power Supply Control Theory

Intuitive Loop Tuning – “Visually without Math”

Active Load Feature of the Power EVM

Multi-Loop Control

The Digital Control System

e(kt)r(t) c(t)

G(s)

ADC

+ DAC

D(z)

Controller

Sensor

Actuator Process

Advantages Considerations

• Sample rate• Quantization• Ease of programming• Controller design• Cost• Processor selection• Requires data converters• Numeric issues

• Immunity from environmental effects• Advanced control strategies possible• Immunity from component errors• Improved noise immunity• Ability to modify and store control parameters• Ability to implement digital communications• System fault monitoring and diagnosis• Data logging capability• Ability to perform automated calibration

Digital Processor

PID Control Review

Proportional term controls loop gain

Integral action increases low frequency gain and reduces/eliminates steady state errors

Derivative action adds phase lead which improves stability and increases system bandwidth

∫ ++=dt

tdeD

KdtteI

KteP

Kty)(

).()()(

∫ dte.

dt

de

KP = Proportional gainKI = Integral gainKD = Derivative gain

+

KP

KI

KD

e(t) y(t)

Gc(s)

sD

KsI

K

PKs

CG ++=)(

++= s

dT

si

TCKs

CG

11)(

Usually written in “parallel” form:

KP = KC

KI = KC/Ti

KD = KCTd

Tuning the Step Response

Peak overshoot

Time to settle to within specified error band

Performance of the control loop can be determined from the output response to a change in load

Acceptable response might be specified in terms of...

We will adjust PID coefficients to optimise our digital controller

Loop Tuning – Good First Step


PID – Intuitive / InteractiveWe can also write the controller in transfer function form: U(z) B0 + B1*z-1 + B2*z-2 B0z

2 + B1*z + B2 ------ = ------------------------- = ---------------------- E(z) 1 - z-1 z2 – z Compare with the General 2P2Z transfer function: U(z) B0 + B1*z-1 + B2*z-2 B0z

2 + B1*z + B2 ------ = --------------------------- = ---------------------- E(z) 1 + A1*z-1 + A2*z-2 z2 + A1*z + A2 We can see that PID is nothing but a special case of 2P2Z control where: A1 = -1 and A2 = 0

// Coefficient init

Coef2P2Z_1[0] = Dgain * 67108; // B2

Coef2P2Z_1[1] = (Igain - Pgain - Dgain - Dgain)*67108; // B1

Coef2P2Z_1[2] = (Pgain + Igain + Dgain)*67108; // B0

Coef2P2Z_1[3] = 0; // A2

Coef2P2Z_1[4] = 67108864; // A1

Coef2P2Z_1[5] = Dmax[1] * 67108; // Clamp Hi limit (Q26)

Coef2P2Z_1[6] = 0x00000000; // Clamp Lo

Change PID coeff. “on fly” in back-ground loop

Control Law Computation

A1

A2

B0

B1

B2


; e(n)=Vref-Vout

MOVU ACC,@Vref

SUBU ACC,*XAR2++

LSL ACC,#8 ; ACC=e(n) (Q24)

MOVL @VCNTL_DBUFF+4,ACC

ZAPA

; Voltage control law

MOVL XT,@VCNTL_DBUFF+8 ; XT=e(n-2)

QMPYAL P,XT,*XAR7++ ; b2*e(n-2)

MOVDL XT,@VCNTL_DBUFF+6 ; XT=e(n-1), e(n-2)=e(n-1)

QMPYAL P,XT,*XAR7++ ; ACC=b2*e(n-2), P=b1*e(n-1)

MOVDL XT,@VCNTL_DBUFF+4 ; XT=e(n), e(n-1)=e(n)

QMPYAL P,XT,*XAR7++ ; ACC+=b1*e(n-1), P=b0*e(n)

MOVL XT,@VCNTL_DBUFF+2 ; XT=u(n-2)

QMPYAL P,XT,*XAR7++ ; P=a2*u(n-2)

MOVDL XT,@VCNTL_DBUFF ; XT=u(n-1), u(n-2)=u(n-1)

QMPYAL P,XT,*XAR7++ ; ACC=a2*u(n-2)

ADDL ACC,P ; ACC=a2*u(n-2)+a1*u(n-1)

LSL ACC,#(23-VCNTL_QF+8) ; (Q23)

ADDL ACC,ACC ; (Q24)

MOVL @VCNTL_DBUFF,ACC ; ACC=u(n)

; Saturate the result [min,max]

MINL ACC,*XAR7++

MAXL ACC,*XAR7++

; Duty Cycle Modulation

MOVL XT,ACC

QMPYL P,XT,*XAR7++ ;(Q0)

MOV *XAR3++,P

XAR7

min

max

duty

U(n)

U(n-1)

U(n-2)

E(n)

E(n-1)

E(n-2)

DBUFF

Type II Controller

++

+

=

212

21

22

11

1

1)(

CCR

CCss

CRs

CRsGc

nFC

pFC

kR

kR

2.2

2.8

124

12.4

2

1

2

1

=

=

Ω=

Ω=

- 2 0

- 1 0

0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

Magnitu

de (

dB

)

1 02

1 03

1 04

1 05

1 06

1 07

1 08

- 9 0

- 4 5

0

Phase (

deg)

B o d e D ia g r a m

F r e q u e n c y ( r a d / s e c )

Digital Type II Controller

DRIVER

Lo

Vin

CONTROLLER

DoCo

Vout

DIGITAL

PROCESSOR

2

0

1

1

1

0

1

12

1)(

−−

−−

++

++=

zAzA

zBzBBzGc

3391.0

339.1

891.9

03632.0

927.9

0

1

0

1

2

=

=

=

=

=

A

A

B

B

B

(Tustin’s transform, Ts = 1 us)

- 2 0

0

2 0

4 0

6 0

8 0

1 0 0

Magnitu

de (

dB

)

1 02

1 03

1 04

1 05

1 06

1 07

1 08

- 9 0

- 4 5

0

4 5

9 0

Phase (

deg)


Fr e q u e n c y ( r a d /s e c )

Type III Controller

( )

+

++

++

+

+=

33212

21

33122

131

31

1

11

)(

CRs

CCR

CCss

CRRs

CRs

CRR

RRsGc

nFC

nFC

nFC

R

kR

kR

8.6

7.2

22.0

150

5.20

12.4

3

2

1

3

2

1

=

=

=

Ω=

Ω=

Ω=

C1

C2 R2

R1

REF

DRIVER

+

-

COMPARATOR

Lo

Vin

CONTROLLER

DoCo

Vout

+

-

C3 R3

0

1 0

2 0

3 0

4 0

Magnitu

de (

dB

)

1 03

1 04

1 05

1 06

1 07

- 9 0

- 4 5

0

4 5

Phase (

deg)


F r e q u e n c y ( r a d / s e c )

Digital Type III Controller

DRIVER

Lo

Vin

CONTROLLER

DoCo

Vout

DIGITAL

PROCESSOR

2

0

1

1

2

2

1

0

1

1

2

2

3

3

1)(

−−−

−−−−

+++

+++=

zAzAzA

zBzBzBzBzGc

2689.0

397.1

128.2

164.9

652.9

158.9

658.9

0

1

2

0

1

2

3

=

=

=

=

=

=

=

A

A

A

B

B

B

B

(Tustin’s transform, Ts = 1 us)

0

2 0

4 0

6 0

8 0

1 0 0

Magnitu

de (

dB

)

1 03

1 04

1 05

1 06

1 07

- 9 0

- 4 5

0

4 5

9 0

Phase

(deg)


Fr e q u e n c y ( r a d /s e c )

2-Channel Buck EVM

ActiveLoad

VoltMeter

Current meas. Temp meas Over Current Prot. Over Current Flag No Heat-sink needed

Phase LinksLEDs

TI PowerTrainPTD08A010W10A module

2-Channel Buck EVM Schematic

Lab4: Tuning the Loop Tune closed-loop Buck power stage for improved transient performance

using visual “trial and error” (rather than mathematical approach)

The 2-channel Buck EVM has an active load circuit when enabled by software provides a repetitive step change in load

CCS graph window feature used to view the transient in real-time

Transient response can be modified directly until the desired improvement is achieved by adjusting P, I, D sliders

Multi-Loop Control

PFC (2PHIL) Software Control Flow

DC-DC (ZVSFB) Software Control Flow

MIPS = 100 # inst / us = 100 PWM (kHz) = 200

# TS = 4 # inst / time slice = 500 PWM (bits) = 9.0

S. rate = 200 Sampling period = 5.0

ISR Rate Function / Activity # Cyc Tot. Cyc. Stats

All 200 kHz Context Save / Restore 32 292 %Util

200 kHz ISR Call / Return / Ack 24 58%

200 kHz Time slice Mgmt 12

200 kHz ADCSEQ2_DRV 14

200 kHz CNTL_2P2Z 1 (V loop) 36

200 kHz CNTL_2P2Z 2 ( I loop) 36

200 kHz I_FOLD_BACK 25

200 kHz ZVSFB_DRV 14

200 kHz ADCSEQ1_DRV 57

200 kHz FILT_2P2Z 35

200 kHz AC_LINE_RECT 7

TS1 100 kHz PFC_OVP 25 117 %Util

100 kHz PFC_ICMD 30 82%100 kHz CNTL_2P2Z 4 (I loop) 36 #Cyc. Rem.

100 kHz PFC2PHIL_DRV 26 91

TS2 50 kHz BOXCAR_AVG 1 42 145 %Util

50 kHz BOXCAR_AVG 2 42 87%100 Hz PFC_ISHARE 15 #Cyc. Rem.

50 kHz Execution Pre-scaler(1:50) 10 63

1 kHz CNTL_2P2Z 3 (V loop) 36

TS3 100 kHz PFC_OVP 25 117 %Util

100 kHz PFC_ICMD 30 82%100 kHz CNTL_2P2Z 4 (I loop) 36 #Cyc. Rem.

100 kHz PFC2PHIL_DRV 26 91

TS4 50 kHz FILT_BIQUAD 46 124 %Util

50 kHz INV_SQR 78 83%#Cyc. Rem.

84

BG Function / Activity # inst. Tot.Cyc. Stats

Comms + Supervisory 400 434 + Soft-Start + Other ?

SLEW_LIMIT 1 17

SLEW_LIMIT 2 17

87%12.6

29.0 34.4

% ISR utilization =

Spare ISR MIPS =

BG loop rate (kHz) / (us) =

CPU Bandwidth Utilization

Workshop Outline






Summary and Conclusion

Review of Workshop Topics and Exercises

TI Digital Power Products

C2000 Digital Signal Controller Family

UCD9xxx Digital Power Controller Family

Where to Find More Information

Workshop Topics and Exercises Review

C28x DSC family provides ideal controller for Digital Power Supply design

Scalable ePWM peripherals, ADC and fault management support

Code Composer Studio, DPS Library and TI Buck EVM

Controlled Buck output voltage using PWM waveform and duty cycle without feedback

Controlled Buck output using Voltage Mode Control with feedback

Tuned closed-loop Buck power stage visually using CCS features

Fle

xib

ilit

y

System Complexity

Power-Optimized Controllers

Fully-Programmable / Control Focused

TI’s Digital Power Controller Portfolioof Solutions

UCD911x

UCD922x

UCD924x

UCD9080

F281x

F283xx

F282xx

F280xx

TI’s Digital Power Solutions Span the Industry

DC/AC Inverters• TMS320C28x 32-bit controller solutions for green energy (solar, wind, fuel cells), UPS, and battery management

AC/DC Rectifiers • Primary:

• Single/Multi-phase, interleaved: C2000 • Single Phase: UCD3xxx

• Secondary: • C2000 Voltage mode & current mode control

• UCD3x Voltage mode control

• Primary plus Secondary: C2000

Non-Isolated DC/DC• UCD9xxx GUI configurable controllers voltage-mode control up to 4 rails and 8 phases• TMS320C28x programmable controllers voltage and current control up to 16 rails or phases• UCD9080 Power Supply Sequencer and Monitor

C2000 Family Roadmap

FutureC28xxx

Performance

F281x150 MHz8 Devices

F280xx60 MHz

150ps PWM

Integration

F282xx150 MHz

DMA

F283xx300 MFLOPS

FPU, DMA

FutureC28xxx

F280xx100MHz

150ps PWM

F281x150 MHz8 Devices

F282xx150 MHz

DMA

F283xx300 MFLOPS

FPU, DMA

FutureC28xxx

F280xx60 MHz

150ps PWM

F280xx100 MHz

150ps PWM

FutureC28xxx

TMS320F280xx

Fast program execution out of both RAM and Flash memory

80 MIPS with Flash Acceleration Technology

100 MIPS out of RAM for time-critical code

Memory Sub-System

Up to 6 ePWM, 4 eCAP, and 2 eQEP

150 ps High-Resolution PWM

Ultra-Fast 12-bit ADC


Dual sample&holds enable simultaneous sampling

Auto Sequencer, up to 16 conversions w/o CPU

Control Peripherals

Multiple standard communication ports provide simple interfaces to other components

Communications Ports

100 MIPS performance Single cycle 32 x32-bit MAC (or dual 16 x16 MAC) Very Fast Interrupt Response Single cycle read-modified-write

High Performance DSP (C28xTM

Core)

Memory Bus

32-256KB

Flash8KB Boot ROM

4-16KB

RAM

Code security

32-bit

Register

FileReal-Time

JTAG

32-bitTimers (3)

100 MIPs C28xTM 32-bit DSP

32x32-bitMultiplier

RMW

Atomic

ALU


ePWM

eCAP

eQEP

12-bit ADC

Watchdog

CAN 2.0 B

I2C

SCI

SPI

GPIO

Perip

hera

l Bu

s

Datasheet available at: http://www-s.ti.com/sc/ds/tms320f2808.pdf

The First Floating-Point DSCs

Processor Performance 300 MFLOPS at 150MHz Single-cycle 32-bit MAC 6-channel DMA support for EMIF,

ADC, McBSP

Memory Three memory options with up to

512KB flash and 68KB RAM Configurable 16- or 32-bit EMIF

Control Peripherals PWM outputs interfaces for three

3-phase motors 6 High-resolution PWM outputs Highest-speed on-chip ADC

Communications Ports Each McBSP configurable as SPI CAN 2.0b with 32 mailboxes I2C at 400 Kbps

TMS320F28335

Real-TimeJTAG

32-bitTimers (3)

C28xTM 32-bit DSC

32x32-bitMultiplier

RMWAtomic

ALU


Memory Bus

Code security

12-bit ADC

SPI

2 CAN

3 SCI

2 McBSP

512 KBFlash

68 KB RAM

6 CAP

18 PWM(6 HRPWM)

DMA

32-bitFloating-Point Unit

88 GPIO

I²C

Boot ROM

16/32-bitEMIF

2 QEP

Perip

hera

l Bu

s

C2000 Digital Power Tools

• 8-rail DC/DC EVM using TI PowerTrain™ modules (10A)• Configurable as multi-phase• Available for $295(TBD) • Low-power AC/DC EVM

• 12VAC input• 2-phase interleaved PFC & PSFB DC/DC• Available for $395(TBD)

• 2-rail DC/DC EVM using TI PowerTrain™modules (10A)• Active load and DMM on board•Available for $199(TBD)

• F28x-based DIMM controller cards• Standard 100-pin interface to all I/Os• Compatible with all Power EVMS• Available for $50-$79(TBD)

VisSim Graphical Programmingfor C2000

Model based design for simulation, code generation, and interactive debugging

Efficient code generation near hand code quality

Automatic code generation for F28xx peripherals: ADC, SCI, SPI, I2C, CAN, ePWM, GPIO

High speed target acquisition for wave form display on PC

Watch ‘how to’ tutorials on Visual Solutions web site

www.vissol.com

UCD9xxx Digital Power Controller Family

4 ind outputs64 & 80 pin

3 ind outputs48 pin

2 ind outputs32 pin

1 output, 2 phase32 pin

1 output, 1 phase32 pin

Performance

Integration

UCD92xx

UCD91xx

UCD9112

UCD9111

UCD9240

UCD9230

UCD9220

Recommended Next Step:One-day Training Course

TMS320C28x 1-Day Workshop Outline

- Workshop Introduction

- Architecture Overview

- Programming Development Environment

- Peripheral Register Header Files

- Reset, Interrupts and System Initialization

- Control Peripherals

- IQ Math Library and DSP/BIOS

- Flash Programming

- The Next Step…Introduction to TMS320F2808

Design and Peripheral Training

Recommended Next Step:Multi-day Training Course

TMS320C28x Multi-day Workshop Outline

- Architectural Overview

- Programming Development Environment

- Peripheral Register Header Files

- Reset and Interrupts

- System Initialization

- Analog-to-Digital Converter

- Control Peripherals

- Numerical Concepts and IQmath

- Using DSP/BIOS

- System Design

- Communications

- Support Resources

In-depth TMS320F2808

Design and Peripheral Training

For More Information . . .

Phone: 800-477-8924 or 972-644-5580

Email: [email protected]

Information and support for all TI Semiconductor products/tools Submit suggestions and errata for tools, silicon and documents

USA - Product Information Center ( PIC )

Website: http://www.ti.com

FAQ: http://www-k.ext.ti.com/sc/technical_support/knowledgebase.htm

Device information my.ti.com Application notes News and events Technical documentation Training

Enroll in Technical Training: http://www.ti.com/sc/training

Internet

Web: http://www-k.ext.ti.com/sc/technical_support/pic/euro.htm

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France +33 (0) 1 30 70 11 64Germany +49 (0) 8161 80 33 11Israel (English) 1800 949 0107 (free phone)Italy 800 79 11 37 (free phone)Netherlands (English) +31 (0) 546 87 95 45Spain +34 902 35 40 28Sweden (English) +46 (0) 8587 555 22United Kingdom +44 (0) 1604 66 33 99Finland (English) +358(0) 9 25 17 39 48

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Email: [email protected]

Literature, Sample Requests and Analog EVM Ordering Information, Technical and Design support for all Catalog TI

Semiconductor products/tools Submit suggestions and errata for tools, silicon and documents

European Product Information Center (EPIC)

C2000 Digital Power Supply Workshop - epc.com.cn Controller (Compensator) ... CNTL_Fdbk1 = &Vout; ADC_Rslt1 = &Vout; Dual Buck Example. ... • CBu trigger for ADC SOC RUN-time

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