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8-bit Microcontroller with 16/32/64K Bytes In-SystemProgrammable Flash
– 131 Powerful Instructions – Most Single-clock Cycle Execution– 32 x 8 General Purpose Working Registers– Fully Static Operation– Up to 20 MIPS Throughput at 20 MHz– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments– 16/32/64K Bytes of In-System Self-programmable Flash program memory– 512B/1K/2K Bytes EEPROM– 1/2/4K Bytes Internal SRAM– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation
– Boundary-scan Capabilities According to the JTAG Standard– Extensive On-chip Debug Support– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode– Real Time Counter with Separate Oscillator– Six PWM Channels– 8-channel, 10-bit ADC
Differential mode with selectable gain at 1x, 10x or 200x– Byte-oriented Two-wire Serial Interface– Two Programmable Serial USART– Master/Slave SPI Serial Interface– Programmable Watchdog Timer with Separate On-chip Oscillator– On-chip Analog Comparator– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features– Power-on Reset and Programmable Brown-out Detection– Internal Calibrated RC Oscillator– External and Internal Interrupt Sources– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and
The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVRenhanced RISC architecture. By executing powerful instructions in a single clock cycle, theATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the sys-tem designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independentregisters to be accessed in one single instruction executed in one clock cycle. The resultingarchitecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.
CPU
GND
VCC
RESET
PowerSupervision
POR / BOD &RESET
WatchdogOscillator
WatchdogTimer
OscillatorCircuits /
ClockGeneration
XTAL1
XTAL2
PORT A (8)
PORT D (8)
PD7..0
PORT C (8)
PC5..0
TWI
SPIEEPROM
JTAG/OCD 16bit T/C 1
8bit T/C 2
8bit T/C 0
SRAMFLASH
USART 0
Internal Bandgap reference
Analog Comparator
A/DConverter
PA7..0
PORT B (8)
PB7..0
USART 1
TOSC1/PC6TOSC2/PC7
48011MS–AVR–08/09
ATmega164P/324P/644P
ATmega164P/324P/644P
The ATmega164P/324P/644P provides the following features: 16/32/64K bytes of In-SystemProgrammable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1/2/4Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real TimeCounter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byteoriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stagewith programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serialport, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chipDebug system and programming and six software selectable power saving modes. The Idlemode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt systemto continue functioning. The Power-down mode saves the register contents but freezes theOscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer basewhile the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and allI/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADCconversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of thedevice is sleeping. This allows very fast start-up combined with low power consumption. InExtended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serialinterface, by a conventional nonvolatile memory programmer, or by an On-chip Boot programrunning on the AVR core. The boot program can use any interface to download the applicationprogram in the application Flash memory. Software in the Boot Flash section will continue to runwhile the Application Flash section is updated, providing true Read-While-Write operation. Bycombining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,the Atmel ATmega164P/324P/644P is a powerful microcontroller that provides a highly flexibleand cost effective solution to many embedded control applications.
The ATmega164P/324P/644P AVR is supported with a full suite of program and system devel-opment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuitemulators, and evaluation kits.
2.2 Comparison Between ATmega164P, ATmega324P and ATmega644P
Table 2-1. Differences between ATmega164P and ATmega644P
Device Flash EEPROM RAM
ATmega164P 16 Kbyte 512 Bytes 1 Kbyte
ATmega324P 32 Kbyte 1 Kbyte 2 Kbyte
ATmega644P 64 Kbyte 2 Kbyte 4 Kbyte
58011MS–AVR–08/09
2.3 Pin Descriptions
2.3.1 VCC
Digital supply voltage.
2.3.2 GND
Ground.
2.3.3 Port A (PA7:PA0)
Port A serves as analog inputs to the Analog-to-digital Converter.
Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected foreach bit). The Port A output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port A pins that are externally pulled low will source current ifthe pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomesactive, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega164P/324P/644P aslisted on page 81.
2.3.4 Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort B output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port B pins that are externally pulled low will source current if the pull-upresistors are activated. The Port B pins are tri-stated when a reset condition becomes active,even if the clock is not running.
Port B also serves the functions of various special features of the ATmega164P/324P/644P aslisted on page 83.
2.3.5 Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort C output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port C pins that are externally pulled low will source current if the pull-upresistors are activated. The Port C pins are tri-stated when a reset condition becomes active,even if the clock is not running.
Port C also serves the functions of the JTAG interface, along with special features of theATmega164P/324P/644P as listed on page 86.
2.3.6 Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort D output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port D pins that are externally pulled low will source current if the pull-upresistors are activated. The Port D pins are tri-stated when a reset condition becomes active,even if the clock is not running.
Port D also serves the functions of various special features of the ATmega164P/324P/644P aslisted on page 88.
68011MS–AVR–08/09
ATmega164P/324P/644P
ATmega164P/324P/644P
2.3.7 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate areset, even if the clock is not running. The minimum pulse length is given in ”System and ResetCharacteristics” on page 332. Shorter pulses are not guaranteed to generate a reset.
2.3.8 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.9 XTAL2
Output from the inverting Oscillator amplifier.
2.3.10 AVCC
AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be exter-nally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connectedto VCC through a low-pass filter.
2.3.11 AREF
This is the analog reference pin for the Analog-to-digital Converter.
78011MS–AVR–08/09
3. About
3.1 Resources
A comprehensive set of development tools, application notes and datasheetsare available fordownload on http://www.atmel.com/avr.
3.2 About Code Examples
This documentation contains simple code examples that briefly show how to use various parts ofthe device. Be aware that not all C compiler vendors include bit definitions in the header filesand interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.
The code examples assume that the part specific header file is included before compilation. ForI/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instruc-tions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and"STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
3.3 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much lessthan 1 PPM over 20 years at 85°C or 100 years at 25°C.
88011MS–AVR–08/09
ATmega164P/324P/644P
ATmega164P/324P/644P
4. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 29
0x1D (0x3D) EIMSK - - - - - INT2 INT1 INT0 69
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
118011MS–AVR–08/09
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-isters, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). AlsoHalide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 329.
Speed (MHz)(3) Power Supply Ordering Code Package(1) Operational Range
44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
168011MS–AVR–08/09
ATmega164P/324P/644P
ATmega164P/324P/644P
6.2 ATmega324P
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). AlsoHalide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 329.
Speed (MHz)(3) Power Supply Ordering Code Package(1) Operational Range
44M1 44-pad, 7 x 7 x 1.0 mm Body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
178011MS–AVR–08/09
6.3 ATmega644P
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). AlsoHalide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 329.
Speed (MHz)(3) Power Supply Ordering Code Package(1) Operational Range
Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
208011MS–AVR–08/09
ATmega164P/324P/644P
ATmega164P/324P/644P
7.3 44M1
TITLE DRAWING NO.GPC REV. Package Drawing Contact: [email protected] 44M1ZWS H
44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN)
9/26/08
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
A1 – 0.02 0.05
A3 0.20 REF
b 0.18 0.23 0.30
D
D2 5.00 5.20 5.40
6.90 7.00 7.10
6.90 7.00 7.10
E
E2 5.00 5.20 5.40
e 0.50 BSC
L 0.59 0.64 0.69
K 0.20 0.26 0.41Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D
E
Marked Pin# 1 ID
E2
D2
b e
Pin #1 CornerL
A1
A3
A
SEATING PLANE
Pin #1 Triangle
Pin #1 Chamfer(C 0.30)
Option A
Option B
Pin #1 Notch(0.20 R)
Option C
K
K
123
218011MS–AVR–08/09
8. Errata
8.1 ATmega164P
8.1.1 Rev. A
No known Errata.
8.2 ATmega324P
8.2.1 Rev. A
No known Errata.
8.3 ATmega644P
8.3.1 Rev. A
Not sampled.
8.3.2 Rev. B
No known Errata.
228011MS–AVR–08/09
ATmega164P/324P/644P
ATmega164P/324P/644P
9. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. Thereferring revision in this section are referring to the document revision.
9.1 Rev. 8011M- 08/09
9.2 Rev. 8011L- 02/09
9.3 Rev. 8011K- 09/08
1. Updated ”Features” on page 1.2. Removed VFBGA - pinout from ”Pin Configurations” on page 2.3. Updated ”System Control and Reset” on page 50.4. Updated Input Hysteresis Unit (V) in the “Typical Characteristics”.5. Updated ”Ordering Information” on page 420. Removed 44MC and 49C2 packages.
6. Updated ”Packaging Information” on page 423.
1. Updated ”Features” on page 1 by inserting a table note 1.2. Merged Sections 3.1, 3.2 and 3.3 in one section ”About” on page 9.3. Updated the front page by removing “Preliminary”.4. Updated the ”DC Characteristics” on page 326 by removing VIL3/VIH3 and VOL3/VOH3 and
the table note 5.
5. Updated the table note1 of the Table 25-6 on page 332.6. Updated ”Typical Characteristics” on page 339.6. Updated ”Typical Characteristics” on page 339
1. Updated ”Features” on page 1, ”Pin Configurations” on page 2 and ”Ordering Informa-tion” on page 15 according to the updated 44M1 package drawing.
2. Updated VOL in the table of ”DC Characteristics” on page 326.3. Updated tRST and tBOD unites in the table of ”System and Reset Characteristics” on
page 332.4. Updated typical values for ATmega324P and ATmega644P in the tables of ”DC Char-
acteristics” on page 326.5. Replaced the package drawing ”44M1” on page 426 by a rev H update.2. Added 49-ball VFBGA pinout for ATmega164P/324P in ”Pinout - VFBGA” on page 4.6. Added 49-ball VFBGA (49C2) to ”Packaging Information” on page 19.
238011MS–AVR–08/09
9.4 Rev. 8011J- 09/08
9.5 Rev. 8011I- 05/08
9.6 Rev. 8011H- 04/08
9.7 Rev. 8011G- 08/07
1. Updated ATmega644P ”Errata” on page 428.2. Added 49-ball VFBGA pinout for ATmega164P/324P in ”Pinout - VFBGA” on page 4.6. Added 49-ball VFBGA (49C2) to ”Packaging Information” on page 425.
1. Updated description in ”AVCC” on page 7.2. Updated ”Stack Pointer” on page 14.3. Updated Data Memory Map addresses, Figure 7-2 on page 21.4. Updated description of use of external capacitors in ”Low Frequency Crystal Oscillator”
on page 35.5. Updated typo in”Alternate Functions of Port C” on page 86.6. Updated bit description in ”TWSR – TWI Status Register” on page 235.7. Updated typo in ”Programming via the JTAG Interface” on page 313.8. Updated conditions for VOL in the table of ”DC Characteristics” on page 326.9. Updated ”External Clock Drive” on page 331.10. Updated conditions for VINT2 in Table 27-11 (Single Ended channels) in ”ADC Charac-
teristics” on page 336.11. Updated Minimum Reference Voltage in Table 27-12 (Differential channels) in ”ADC
Characteristics” on page 336.12. Updated bit bit field typos in ”Register Summary” on page 414.2. Added 49-ball VFBGA pinout for ATmega164P/324P in ”Pinout - VFBGA” on page 4.6. Added 49-ball VFBGA (49C2) to ”Packaging Information” on page 425.
1. Added 44-pad DRQFN pinout for ATmega164P in ”Pinout - DRQFN” on page 3.2. Added 49-ball VFBGA pinout for ATmega164P/324P in ”Pinout - VFBGA” on page 4.2. Added note to ”Address Match Unit” on page 215.3. Updated ATmega164P ”Ordering Information” on page 421.4. Added 44-lead QFN (44MC) to ”Packaging Information” on page 424.6. Added 49-ball VFBGA (49C2) to ”Packaging Information” on page 425.
1. Updated ”Features” on page 12. Added ”Data Retention” on page 9.3. Updated ”SPH and SPL – Stack Pointer High and Stack pointer Low” on page 15.4. LCD reference removed from table note in ”Sleep Modes” on page 43.5. Updated code example in ”Bit 0 – IVCE: Interrupt Vector Change Enable” on page 66.
248011MS–AVR–08/09
ATmega164P/324P/644P
ATmega164P/324P/644P
9.8 Rev. 8011F- 04/07
9.9 Rev. 8011E - 04/07
9.10 Rev. 8011D - 02/07
9.11 Rev. 8011C - 10/06
6. Removed reference to External Memory Interface in ”Alternate Functions of Port A” onpage 81.
7. Updated ”Data Reception – The USART Receiver” on page 181.8. Updated ”ADCSRB – ADC Control and Status Register B” on page 239.9. Updated overview in ”ADC - Analog-to-digital Converter” on page 241.10. Added ”ATmega644P Typical Characteristic” on page 389.11. Updated Figure 28-31 on page 355, Figure 28-32 on page 356,Figure 28-33 on page
35612. Updated notes in Table 8-3 on page 33.Table 8-8 on page 36, Table 8-9 on page 37,
and Table 8-11 on page 38.13. Updated Table 13-7 on page 85, Table 13-8 on page 85, Table 13-10 on page 87,
Table 13-11 on page 88, Table 13-14 on page 91, Table 27-1 on page 328,Table 27-2on page 328,Table 27-5 on page 331, Table 27-9 on page 333, and Table 27-12 onpage 337
14. Updated ”ATmega324P DC Characteristics” on page 328 and ”ATmega644P DC Char-acteristics” on page 329.
15. Updated Table 27-7 on page 332 and Table 8-13 on page 38.
1. Updated ”Watchdog Timer Configuration” on page 60.
1. Updated ”GTCCR – General Timer/Counter Control Register” on page 160.2. Updated ”EECR – The EEPROM Control Register” on page 24.
1. Updated ”Pinout ATmega164P/324P/644P” on page 2.2. Updated ”Power-down Mode” on page 45.3. Updated note in Table 12-1 on page 69.4. Updated Table 24-1 on page 273.5. Updated ”Boot Size Configuration(1)” on page 290.6. Updated VOL limits in ”DC Characteristics” on page 326.7. Updated note 3 and 4 in ”DC Characteristics” on page 326.8. Added note to ”ATmega164P DC Characteristics” on page 328.9. Added note to ”ATmega324P DC Characteristics” on page 328.10. Updated Figure 28-13 on page 346 and Figure 28-60 on page 371.
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