Verific Design Automation, Alameda, CA (510) 522-1555 www.verific.com head and shoulders above the rest... BUILD YOUR OWN RTL TOOLS with Verific’s industry standard parsers and elaborators • Parse and analyze • Elaborate • Traverse and manipulate the parse tree and netlist • Modify RTL and print out with comments and layout preserved • Find, insert, remove, and change modules, ports, nets, etc.. • • Group / ungroup All through easy to understand Perl and Python APIs. Not every EDA application needs to be written in C++. erefore Verific has enabled its industry standard SystemVerilog, UPF, and VHDL parsers with a complete Perl and Python interface. All regular Verific functionality is now available at your Perl or Python fingertips. RTL modifications, debug insertion, design for test adjustments, interface changes, clock domain checks, you name it: It is all easily accomplished with Verific’s parsers and data structures. Keep / flatten hierarchy Elaboration Parser / Analyzer Pre- Processor Synthesis / Elaboration Synthesis / Elaboration System Verilog UPF VHDL Parser / Analyzer Parser / Analyzer UPF Data Model Netlist Database VHDL Parse Tree Verilog Parse Tree Static Elab Static Elab Perl / Python APIs Your Application
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Veri�c Design Automation, Alameda, CA (510) 522-1555 www.veri�c.com
head and shoulders above the rest...
BUILD YOUR OWN RTL TOOLSwith Verific’s industry standard
parsers and elaborators
• Parse and analyze
• Elaborate
• Traverse and manipulate theparse tree and netlist
• Modify RTL and print out withcomments and layout preserved
All through easy to understand Perland Python APIs.
Not every EDA application needs to be written in C++. �erefore Veri�c has enabled its industry standard SystemVerilog, UPF, and VHDL parsers with a complete Perl and Python interface. All regular Veri�c functionality is now available at your Perl or Python �ngertips.
RTL modi�cations, debug insertion, design for test adjustments, interface changes, clock domain checks, you name it: It is all easily accomplished with Veri�c’s parsers and data structures.
Keep / �atten hierarchy
Elaboration
Parser /Analyzer
Pre-Processor
Synthesis /Elaboration
Synthesis /Elaboration
SystemVerilog UPF VHDL
Parser /Analyzer
Parser /AnalyzerUPF Data
Model
NetlistDatabase
VHDLParse Tree
VerilogParse Tree
Static Elab Static Elab
Perl / Python APIs
Your Application
Veri�c Design Automation, Alameda, CA (510) 522-1555 www.veri�c.comJune 2017
#!/usr/bin/perl
use Verific;
# this application parses a SystemVerilog design,# finds all clock nets, and prints them to stdout
# Analyze the design. In case of failure returnif (!Verific::veri_file::Analyze($file_name, $mode)){ exit(1);}
# Elaborate all analyzed design units. In case of failure returnif (!Verific::veri_file::ElaborateAll()) { exit(1) ;}
# Get a handle to the top-level design$top = Verific::Netlist::PresentDesign() ;
# Flatten down to primitives$top->Flatten() ;
# Iterate over all DFF instances$insts = $top->GetInsts();$iter = $insts->Iterator(“Instance”);for (my $inst = $iter->First; $iter < $iter->Size; $inst = $iter->Next) { if ($inst->Type() eq $Verific::PRIM_DFF || $inst->Type() eq $Verific::PRIM_DFFRS) {
# Get clock net for this flipflop my $clock_net = $inst->GetClock(); # Use a Perl hash table to check if the net has occurred before # and if not, print to screen if (!defined($clocknets{$clock_net->Name()})) { # Have not seen this clock net before printf “-- Net %s is a clock net\n” , $clock_net->Name() ; $clocknets{$clock_net->Name()}=1; } }}