Chng 1 Gii Thiu Dng Vi iu Khin STM32
1. Gii thiu dng vi iu khin STM32Nhng c im ni tri ca dng ARM
Cortex thu ht cc nh sn xut IC, hn 240 dng vi iu khin da vo nhn
Cortex c gii thiu. Khng nm ngoi xu hng , hng sn xut chip ST
Microelectronic nhanh chng a ra dng STM32. STM32 l vi iu khin da
trn nn tng li ARM Cortex-M3 th h mi do hng ARM thit k. Li ARM
Cortex-M3 l s ci tin t li ARM7 truyn thng tng mang li thnh cng vang
di cho cng ty ARM.1.1 Mt vi c im ni bt ca STM32ST a ra th trng 4
dng vi iu khin da trn ARM7 v ARM9, nhng STM32 l mt bc tin quan trng
trn ng cong chi ph v hiu sut (price/performance), gi ch gn 1 Euro
vi s lng ln, STM32 l s thch thc tht s vi cc vi iu khin 8 v 16-bit
truyn thng. STM32 u tin gm 14 bin th khc nhau, c phn thnh hai dng:
dng Performance c tn s hot ng ca CPU ln ti 72Mhz v dng Access c tn
s hot ng ln ti 36Mhz. Cc bin th STM32 trong hai nhm ny tng thch hon
ton v cch b tr chn (pin) v phn mm, ng thi kch thc b nh FLASH ROM c
th ln ti 512K v 64K SRAM.
Hnh 1. Kin trc ca STM32 nhnh Performance v Access
Nhnh Performance hot ng vi xung nhp ln n 72Mhz v c y cc ngoi vi,
nhnh Access hot ng vi xung nhp ti a 36Mhz v c t ngoi vi hn so vi
nhnh Performance.a. S tinh viThot nhn th cc ngoi vi ca STM32 cng
ging nh nhng vi iu khin khc, nh hai b chuyn i ADC, timer, I2C, SPI,
CAN, USB v RTC. Tuy nhin mi ngoi vi trn u c rt nhiu c im th v. V d
nh b ADC 12-bit c tch hp mt cm bin nhit t ng hiu chnh khi nhit thay
i v h tr nhiu ch chuyn i. Mi b nh thi c 4 khi capture compare (dng
bt s kin vi tnh nng input capture v to dng sng ng ra vi output
compare), mi khi nh thi c th lin kt vi cc khi nh thi khc to ra mt
mng cc nh thi tinh vi hn. Mt b nh thi cao cp chuyn h tr iu khin ng
c, vi 6 u ra PWM vi dead time (khong thi gian c chn vo gia hai u tn
hiu xut PWM b nhau trong iu khin mch cu H) lp trnh c v mt ng break
input (khi pht hin iu kin dng khn cp) s buc tn hiu PWM sang mt trng
thi an ton c ci sn. Ngoi vi ni tip SPI c mt khi kim tng (CRC) bng
phn cng cho 8 v 16 word h tr tch cc cho giao tip th nh SD hoc
MMC.STM32 c h tr thm ti a 12 knh DMA (Direct Memory Access). Mi knh
c th c dng truyn d liu n cc thanh ghi ngoi vi hoc t cc thanh ghi
ngoi vi i vi kch thc t (word) d liu truyn i c th l 8/16 hoc 32-bit.
Mi ngoi vi c th c mt b iu khin DMA (DMA controller) i km dng gi hoc
i hi d liu nh yu cu. Mt b phn x bus ni (bus arbiter) v ma trn bus
(bus matrix) ti thiu ho s tranh chp bus gia truy cp d liu thng qua
CPU (CPU data access) v cc knh DMA. iu cho php cc n v DMA hot ng
linh hot, d dng v t ng iu khin cc lung d liu bn trong vi iu
khin.STM32 l mt vi iu khin tiu th nng lng thp v t hiu sut cao. N c
th hot ng in p 2V, chy tn s 72MHz v dng tiu th ch c 36mA vi tt c cc
khi bn trong vi iu khin u c hot ng. Kt hp vi cc ch tit kim nng lng
ca Cortex, STM32 ch tiu th 2A khi ch Standby. Mt b dao ng ni RC
8MHz cho php chip nhanh chng thot khi ch tit kim nng lng trong khi
b dao ng ngoi ang khi ng. Kh nng nhanh i vo v thot khi cc ch tit
kim nng lng lm gim nhiu s tiu th nng lng tng th.b. S an tonNgy nay
cc ng dng hin i thng phi hot ng trong mi trng khc khe, i hi tnh an
ton cao, cng nh i hi sc mnh x l v cng nhiu thit b ngoi vi tinh vi.
p ng cc yu cu khc khe , STM32 cung cp mt s tnh nng phn cng h tr cc
ng dng mt cch tt nht. Chng bao gm mt b pht hin in p thp, mt h thng
bo v xung Clock v hai b Watchdogs. B u tin l mt Watchdog ca s
(windowed watchdog). Watchdog ny phi c lm ti trong mt khung thi
gian xc nh. Nu nhn n qu sm, hoc qu mun, th Watchdog s kch hot. B th
hai l mt Watchdog c lp (independent watchdog), c b dao ng bn ngoi
tch bit vi xung nhp h thng chnh. H thng bo v xung nhp c th pht hin
li ca b dao ng chnh bn ngoi (thng l thch anh) v t ng chuyn sang dng
b dao ng ni RC 8MHz.c. Tnh bo mtMt trong nhng yu cu khc khe khc ca
thit k hin i l nhu cu bo mt m chng trnh ngn chn sao chp tri php phn
mm. B nh Flash ca STM32 c th c kha chng truy cp c Flash thng qua
cng Debug. Khi tnh nng bo v c c kch hot, b nh Flash cng c bo v chng
ghi ngn chn m khng tin cy c chn vo bng vector ngt. Hn na bo v ghi c
th c cho php trong phn cn li ca b nh Flash. STM32 cng c mt ng h thi
gian thc v mt khu vc nh d liu trn SRAM c nui nh ngun pin. Khu vc ny
c mt u vo chng gi mo (anti-tamper input), c th kch hot mt s kin ngt
khi c s thay i trng thi u vo ny. Ngoi ra mt s kin chng gi mo s t ng
xa d liu c lu tr trn SRAM c nui bng ngun pin.d. Pht trin phn mmNu
bn s dng mt vi iu khin da trn li ARM, th cc cng c pht trin cho ARM
hin c c h tr tp lnh Thumb-2 v dng Cortex. Ngoi ra ST cng cung cp mt
th vin iu khin thit b ngoi vi, mt b th vin pht trin USB nh l mt th
vin ANSI C v m ngun l tng thch vi cc th vin trc c cng b cho vi iu
khin STR7 v STR9. C rt nhiu RTOS m ngun m v thng mi v middleware
(TCP/IP, h thng tp tin, v.v.) h tr cho h Cortex. Dng Cortex-M3 cng
i km vi mt h thng g li hon ton mi gi l CoreSight. Truy cp vo h thng
CoreSight thng qua cng truy cp Debug (Debug Access Port), cng ny h
tr kt ni chun JTAG hoc giao din 2 dy (serial wire-2 Pin), cng nh
cung cp trnh iu khin chy g li, h thng CoreSight trn STM32 cung cp h
thng im truy cp(data watchpoint) v mt cng c theo di
(instrumentation trace). Cng c ny c th gi thng tin v ng dng c la
chn n cng c g li. iu ny c th cung cp thm cc thng tin g li v cng c
th c s dng trong qu trnh th nghim phn mm.e. Dng Performance v
Access ca STM32H STM32 c hai nhnh u tin ring bit: dng Performance v
dng Access. Dng Performance tp hp y cc thit b ngoi vi v chy vi xung
nhp ti a 72MHz. Dng Access c cc thit b ngoi vi t hn v chy ti a
36MHz. Quan trng hn l cch b tr chn (pins layout) v cc kiu ng gi
chip (package type) l nh nhau gia dng Access v dng Performance. iu
ny cho php cc phin bn khc nhau ca STM32 c hon v m khng cn phi sa i
sp sp li footprint (m hnh chn ca chip trong cng c layout bo mch)
trn PCB (Printed Circuit Board).Ngoi hai dng Performance v Access u
tin, hin nay ST a ra th trng thm hai dng USB Access v Connectivity
nh hnh bn di.
Hnh 2. c im ca bn nhnh trong h STM32
Chng 2 Gii thiu b x l ARM Cortex-M3
I. Gii Thiu Chung1. Gii thiuGii php Soc (System-on-chip) da trn
b vi x l nhng ARM c ng dng vo rt nhiu th trng khc nhau bao gm cc ng
dng doanh nghip, cc h thng t, mng gia nh v cng ngh mng khng dy...
Dng vi x l ARM Cortex da trn mt kin trc chun p ng hu ht cc yu cu v
hiu nng lm vic trong tt c cc lnh vc trn. Dng ARM Cortex bao gm ba
cu hnh khc nhau ca kin trc ARMv7: cu hnh A cho cc ng dng tinh vi,
yu cu cao chy trn cc h iu hnh m v phc tp nh Linux, Android; cu hnh
R dnh cho cc h thng thi gian thc v cu hnh M c ti u cho cc ng dng vi
iu khin, cn tit kim chi ph. B vi x l Cortex-M3 l b vi x l ARM u tin
da trn kin trc ARMv7-M v c thit k c bit t c hiu sut cao trong cc ng
dng nhng cn tit kim nng lng v chi ph, chng hn nh cc vi iu khin, h
thng c t, h thng kim sot cng nghip v h thng mng khng dy. Thm vo l
vic lp trnh c n gin ha ng k gip kin trc ARM tr thnh mt la chn tt
cho ngay c nhng ng dng n gin nht.2. Hiu sut cao t c hiu sut cao hn,
b vi x l c th lm vic nhiu hn hoc lm vic thng minh hn. y tn s hot ng
cao hn c th lm tng hiu sut nhng cng i km vi vic tiu th nng lng nhiu
hn v vic thit k cng phc tp hn. Ni cch khc, cng thc hin nhng tc v
nhng bng cch nng cao hiu qu tnh ton trong khi vn hot ng tn s thp s
dn n s n gin ha trong vic thit k v t tn nng lng hn. Trung tm ca b
vi x l Cortex-M3 l mt li c cu trc ng ng tin tin 3 tng, da trn kin
trc Harvard, kt hp nhiu tnh nng mi mnh m nh suy on vic r nhnh, php
nhn c thc thi trong mt chu k v php chia c thc hin bng phn cng to nn
mt hiu nng vt tri (im Dhrystone l 1,25 DMIPS/MHz). B vi x l
Cortex-M3 h tr kin trc tp lnh Thumb-2, gip n hot ng hiu qu hn 70%
cho mi MHz so vi mt b vi x l ARM7TDMI-S thc thi vi tp lnh Thumb, v
hiu qu hn 35% so vi b x l ARM7TDMI-S thc thi vi tp lnh ARM.3. D s
dng, pht trin ng dng nhanh chng, hiu qu
Tiu ch quan trng trong vic la chn b vi x l l gim thi gian v chi
ph pht trin, c bit l kh nng pht trin ng dng phi tht nhanh chng v n
gin. B vi x l Cortex-M3 c thit k p ng mc tiu trn. Ngi lp trnh khng
cn phi vit bt k m hp ng no (assembler code) hoc cn phi c kin thc su
v kin trc to ra mt ng dng n gin. B vi x l c m hnh lp trnh da trn
ngn xp c n gin ho tng thch vi kin trc ARM truyn thng nhng tng t vi
h thng c trin khai trn kin trc 8 v 16-bit, gip vic chuyn tip n kin
trc 32-bit d dng hn. Ngoi ra mt m hnh ngt da trn phn cng s gip vic
vit cc chng trnh x l ngt tr nn n gin hn bao gi ht, chng trnh khi ng
c th c vit trc tip bng ngn ng C m khng cn bt k mt lnh assembly no
so vi kin trc ARM truyn thng. Cc tnh nng chnh mi trong tp lnh
Thumb-2 bao gm vic thc hin m lnh C mt cch t nhin hn, thao tc trc
tip trn cc bit, php chia phn cng v lnh If/Then. Hn na, nhn t gc pht
trin ng dng, Thumb-2 tng tc pht trin, n gin ha vic bo tr, h tr cc i
tng bin dch thng qua ti u ha t ng cho c hiu sut v mt m m khng cn
quan tm n vic m c bin dch cho ch ARM hoc Thumb. Kt qu l lp trnh vin
c th m ngun ca h trong ngn ng C m khng cn to ra cc th vin i tng bin
dch sn, c ngha l kh nng ti s dng m ngun ln hn nhiu.4. Gim chi ph
pht trin v nng lng tiu th
Chi ph lun l ro cn ln nht cho s la chn mt b vi x l hiu sut cao.
B vi x l c thit k trn mt din tch nh s gim chi ph ng k. B vi x l
Cortex-M3 thc hin iu ny bng cch ci t cc li ARM nh nht t trc n nay,
ch vi 33.000 cng (cng c th l NAND hoc NOR tu vo cng ngh sn xut)
trong li trung tm (0.18um G) v bng cch kt hp hiu qu, cht ch cc thnh
phn trong h thng vi x l. B nh c ti gin bng cch ci t b nh khng thng
hng (unaligned), thao tc bit d dng vi k thut bit banding. Tp lnh
Thumb-2 tit kim b nh hn 25% so vi tp lnh ARM. p ng nhu cu ngy cng
tng trong vic tit kim nng lng cc ng dng mng khng dy, b vi x l
Cortex-M3 h tr m rng xung nhp cho cc cng (c th ngng cung cp xung
nhp cho cc cng tit kim nng lng) v tch hp ch ng. Kt qu l b vi x l ch
tiu th 4.5mW in nng v chim din tch 0.3 mm2 (silicon footprint) khi
trin khai tn s 50MHz trn qu trnh cng ngh TSMC 0.13G, s dng t bo tiu
chun ARM Metro.5. Tch hp kh nng d li v theo vt trong lp trnh
H thng nhng thng khng c giao din ngi dng ha (GUI) lm cho vic g
li chng trnh tr thnh mt thch thc tht s i cc lp trnh vin. Ban u, b
ICE (In-circuit Emulator) c s dng to mt ca s theo di h thng thng
qua mt giao din quen thuc nh trn PC. Tuy nhin khi h thng ngy cng nh
v phc tp hn, phng php ny khng cn kh thi na. Cng ngh g li ca b vi x
l Cortex-M3 c ci t trong chnh phn cng ca n (kt hp vi mt vi thnh phn
khc) gip g li nhanh hn vi cc tnh nng trace & profiling,
breakpoints, watchpoints v bn v li gip rt ngn thi gian pht trin ng
dng. Ngoi ra, b vi x l cn cung cp mt mc nhn cao hn vo h thng thng
qua cng JTAG truyn thng hoc cng SWD (Serial Wire Debug) ch s dng 2
ng tn hiu, thch hp cho cc thit b c kiu ng gi nh gn.6. Chuyn t dng x
l ARM7 sang Cortex-M3 hot ng v s dng nng lng hiu qu hnTrong gn mt
thp k qua, dng vi x l ARM7 c s dng rt rng ri. B vi x l Cortex-M3 c
xy dng trn nn tng ny nn vic nng cp t dng ARM7 ln Cortex-M3 l hp l v
d dng. Li trung tm lm vic hiu qu hn, m hnh lp trnh n gin, cch x l
ngt tt nh (deterministic interrupt behaviour), vic tch hp cc thit b
ngoi vi gip nng cao hiu nng lm vic m vn gi c chi ph thp.
Bng 1. So snh ARM7TDMI-S v Cortex-M3 (100MHz - TSMC 0.18G)(*:
Khng bao gm cc thit b ngoi vi (MPU & ETM) hoc cc thnh phn tch
hp khc)
Hnh 1. So snh hiu sut gia ARM7TDMI-S (ARM) v Cortex-M3
(Thumb-2)
Hnh 2. So snh kch thc m lnh gia ARM7TDMI-S (ARM) v Cortex-M3
(Thumb-2)
II. C Ch To Xung Ca Cortex M31. Kin trc v tnh nng vi x l
Cortex-M3B vi x l Cortex-M3 da trn kin trc ARMv7-M c cu trc th bc.
N tch hp li x l trung tm, gi l CM3Core, vi cc thit b ngoi vi h thng
tin tin to ra cc kh nng nh kim sot ngt, bo v b nh, g li v theo vt h
thng.Cc thit b ngoi vi c th c cu hnh mt cch thch hp, cho php b vi x
l Cortex-M3 p ng c rt nhiu ng dng v yu cu kht khe ca h thng. Li ca
b vi x l Cortex-M3 v cc thnh phn tch hp (hnh 3) c thit k c bit p ng
yu cu b nh ti thiu, nng lng tiu th thp v thit k nh gn.1.1 Li
Cortex-M3Li trung tm Cortex-M3 da trn kin trc Harvard, c c trng bng
s tch bit gia vng nh cha d liu v chng trnh do c cc bus ring truy cp
(hnh 3). c tnh ny khc vi dng ARM7 da trn kin trc Von Neumann s dng
chung vng nh cha d liu v chng trnh, do dng chung bus cho vic truy
xut. V c th c cng lc lnh v d liu t b nh, b vi x l Cortex-M3 c th
thc hin nhiu hot ng song song, tng tc thc thi ng dng.
Hnh 3. B vi x l Cortex-M3
Li Cortex c cu trc ng ng gm 3 tng:Instruction Fetch,Instruction
DecodevInstruction Execute. Khi gp mt lnh nhnh, tng decode cha mt
ch th np lnh suy on c th dn n vic thc thi nhanh hn. B x l np lnh d
nh r nhnh trong giai on gii m. Sau , trong giai on thc thi, vic r
nhnh c gii quyt v b vi x l s phn tch xem u l lnh thc thi k tip. Nu
vic r nhnh khng c chn th lnh tip theo sn sng. Cn nu vic r nhnh c
chn th lnh r nhnh cng sn sng ngay lp tc, hn ch thi gian ri ch cn mt
chu k.Li Cortex-M3 cha mt b gii m cho tp lnh Thumb truyn thng v
Thumb-2 mi, mt ALU tin tin h tr nhn chia phn cng, iu khin logic, v
cc giao tip vi cc thnh phn khc ca b x l.B vi x l Cortex-M3 l mt b
vi x l 32-bit, vi rng ca ng dn d liu 32 bit, cc di thanh ghi v giao
tip b nh. C 13 thanh ghi a dng, hai con tr ngn xp, mt thanh ghi lin
kt, mt b m chng trnh v mt s thanh ghi c bit trong c mt thanh ghi
trng thi chng trnh.B vi x l Cortex-M3 h tr hai ch hot ng (Thread v
Handler) v hai mc truy cp ti nguyn ca li x l (c quyn v khng c
quyn), to iu kin cho vic ci t cc h thng m v phc tp nhng vn bo mt.
Nhng dng m khng c quyn b gii hn hoc khng cho php truy cp vo mt s ti
nguyn quan trng (mt s lnh c bit v cc vng nh nht nh). Ch Thread l ch
hot ng tiu biu h tr c m c quyn v khng c quyn. B vi x l s vo ch
Handler khi mt ngoi l (exception) xy ra v tt c cc m l c quyn trong
ch ny. Ngoi ra, tt c cc hot ng trong b vi x l u thuc mt trong hai
trng thi hot ng: Thumb cho ch thc thi bnh thng v Debug cho vic g
li.B vi x l Cortex-M3 l mt h thng nh x b nh n gin, qun l vng nh c
nh ln ti 4 gigabyte vi cc a ch nh ngha sn, dnh ring cho m lnh (vng
m lnh), SRAM (vng nh), b nh/thit b bn ngoi, thit b ngoi vi bn trong
v bn ngoi. Ngoi ra cn c mt vng nh c bit dnh ring cho nh cung
cp.
Hnh 4. Bn b nh
B vi x l Cortex-M3 cho php truy cp trc tip n tng bit d liu trong
cc h thng n gin bng cch thc thi mt k thut c gi l bit-banding (hnh
5). B nh bao gm hai vng bit-band (mi vng 1MB) trong SRAM v vng b
danh 32MB ca vng khng gian ngoi vi (Mi byte trong vng b danh s tng
ng vi mt bit trong vng bit-band). Mi hot ng np/lu ti mt a ch trong
khu vc b danh (alias region) s trc tip tng ng vi hot ng trn bit c i
din bi b danh . C th, khi ghi gi tr 0x01 vo mt a ch trn vng b danh
th c ngha l xc nh bit tng ng s c gi tr l 1, tng t gi tr 0x00 s xc
nh bit tng ng c gi tr 0. Cn c gi tr ti mt a ch vng b danh c ngha l
c c gi tr ca bit tng ng. Mt vn cn ch na l hot ng ny mang tnh nguyn
t (khng chia nh c na), khng th b gin on bi cc hot ng khc trn
bus.
Hnh 5
Cc h thng c da trn ARM7 ch h tr truy xut d liu thng hng, ch cho
php lu tr v truy xut d liu ca mt khi b nh m mi phn t c n v l mt
word. B vi x l Cortex-M3 h tr truy xut d liu khng thng hng, cho php
chuyn d liu khng thng hng trong mt truy xut n. Thc t, vic chuyn d
liu khng thng hng c bin thnh vic chuyn nhiu ln d liu thng hng v c
tnh trong sut i vi lp trnh vin (ngha l lp trnh vin hon ton khng cn
quan tm n iu ny). Ngoi ra b vi x l Cortex-M3 cng h tr php nhn
32-bit hot ng trong mt chu trnh n v cc php chia c du, khng du vi cc
lnh SDIV v UDIV, mt t 2 n 12 chu k ph thuc vo kch thc ca ton hng.
Php chia c thc thi nhanh hn nu s chia v s b chia c kch thc tng t
nhau. Nhng ci tin trong kh nng ton hc gip Cortex-M3 tr thnh b vi x
l l tng cho cc ng dng thin v tnh ton nh c cm bin hoc cc h thng m
phng.1.2 Kin trc tp lnh Thumb-2ARMv7-M l cu hnh vi iu khin ca kin
trc ARMV7 v khc vi cc kin trc ARM trc ch n ch h tr tp lnh Thumb-2.
Tp lnh Thumb-2 l s pha trn gia tp lnh 16 v 32 bit, t c hiu sut ca
cc lnh ARM 32 bit, ng thi ph hp vi mt m cng nh tng thch ngc vi tp
lnh gc Thumb 16 bit.
Hnh 6
Trong mt h thng da trn b vi x l ARM7, vic chuyn i nhn x l gia ch
Thumb (c li v mt m) v ARM (c li v mt hiu sut) l cn thit cho mt s ng
dng. Cn b vi x l Cortex-M3 c cc lnh 16 bit v 32 bit tn ti trong cng
mt ch , cho php mt m cng nh hiu sut u cao hn m khng cn phi chuyn i
phc tp. V tp lnh Thumb-2 l tp bao hm ca tp lnh Thumb 16 bit nn b vi
x l Cortex-M3 c th thc thi cc on m trc y vit cho Thumb 16 bit. Do c
ci t tp lnh Thumb-2 nn b vi x l Cortex-M3 c kh nng tng thch vi cc
thnh vin khc ca dng ARM Cortex.Tp lnh Thumb-2 c cc lnh c bit gip lp
trnh vin d dng vit m cho nhiu ng dng khc nhau. Cc lnh BFI v BFC l
cc lnh thao tc trn bit, rt c ch trong cc ng dng x l gi tin mng. Cc
lnh SBFX v UBFX gip vic chn vo hoc trch xut mt s bit trong thanh
ghi c nhanh chng. Lnh RBIT o bit trong mt WORD, c ch trong cc thut
ton DSP nh DFT. Cc lnh bng r nhnh TBB v TBH to s cn bng gia mt m v
hiu sut. Tp lnh Thumb-2 cng gii thiu cu trc If-Then mi c th xc nh
iu kin thc hin ti a bn lnh tip theo.1.3 B iu khin vector ngt lng
nhau (NVIC)NVIC (Nested Vectored Interrupt Controller) l thnh phn
tch hp ca b vi x l Cortex-M3 c kh nng x l ngt rt linh hot v nhanh
chng. Trong ci t chun, n cung cp mt NMI (Non-Maskable Interrupt) v
32 ngt vt l a dng vi 8 mc u tin pre-emption. N c th c cu hnh t 1 n
240 ngt vt l vi ti a 256 mc u tin.B vi x l Cortex-M3 s dng mt bng
vector c th ti nh v c, dng cha a ch ca hm x l ngt. Khi nhn mt ngt,
b x l s ly a ch t bng vector thng qua bus chng trnh. Bng vector ngt
c t a ch 0 khi reset, nhng c th c di chyn n v tr khc bng cch lp
trnh mt thanh ghi iu khin. gim bt s cng v tng tnh linh hot h thng,
b vi x l Cortex-M3 chuyn t m hnh ngoi l thanh ghi theo di ca b vi x
l ARM7 sang m hnh ngoi l da trn stack. Khi c mt ngoi l xut hin th b
m chng trnh (Program Counter), thanh ghi trng thi chng trnh
(Program Status Register), thanh ghi lin kt (Link Register) v cc
thanh ghi a dng t R0-R3, R12 b y vo ngn xp. Trong khi bus d liu y
cc thanh ghi ln vng ngn xp th bus chng trnh xc nh cc vector ngoi l
t bng vector v np lnh u tin ca m chng trnh x l ngoi l. Sau khi hon
tt vic lu tr d liu trn ngn xp v np lnh, chng trnh phc v ngt v x l
li c thc thi, tip theo cc thanh ghi s c phc hi t ng chng trnh b ngt
tip tc thc hin bnh thng. V thc hin cc hot ng ngn xp bng phn cng nn
ta khng cn vit cc on hp ng thc hin cc thao tc trn ngn xp cho cc hm
x l ngt truyn thng da trn ngn ng C, gip vic pht trin ng dng d dng
hn rt nhiu.NVIC h tr ngt lng nhau, cho php mt ngt c x l trc mt ngt
khc da trn mc u tin. N cng h tr cu hnh mc u tin ng cho cc ngt. u
tin c th c thay i bng phn mm trong thi gian chy (run time). Cc ngt
ang c x l u b kha cho n khi hm x l ngt hon thnh, do , u tin ca ngt
c th thay i m khng cn lo n chuyn trng lp.Trong trng hp cc ngt ni ui
nhau, cc h thng c s lp li hai ln vic lu trng thi hon thnh v khi
phc, dn n tr cao. B vi x l Cortex-M3 n gin ha vic chuyn i gia cc
ngt ang hot ng v ang ch bng cch ci t cng ngh tail-chaining trong
phn cng NVIC. Tail-chaining t tr thp hn nhiu bng cch thay th chui
cc thao tc pop v push vn mt hn 30 chu k xung nhp bng mt thao tc np
lnh n gin ch mt 6 chu k. Trng thi b vi x l c t ng lu khi ngt bt u c
x l v phc hi ngay khi kt thc, t chu k hn so vi vic thc thi bng phn
mm, nng cao hiu sut ng k h thng hot ng di 100MHz.
Hnh 7. Tail chaining trong NVIC
NVIC cng ci t cch thc qun l nng lng ca b vi x l Cortex-M3 tch hp
ch ng. Ch Sleep Now c gi bng mt trong hai lnh WFI (Wait For
Interrupt) hoc WFE (Wait For Event) s ngay lp tc t nhn b vi x l vo
trng thi nng lng thp v ch mt ngoi l (exception). Ch Sleep On Exit t
h thng vo ch nng lng thp ngay khi n thot khi hm x l ngt c u tin thp
nht. Nhn b vi x l vn trng thi ng cho n khi gp mt ngoi l. V ch c th
thot khi ch ny bng ngt nn trng thi h thng khng c phc hi. Bit
SLEEPDEEP ca thanh ghi iu khin h thng nu c thit lp c th c s dng kho
cng (clock gate) li b vi x l v cc thnh phn h thng khc tit kim in
nng.NVIC cng tch hp mt b m SysTick 24-bit m ngc (count-down timer)
c th c s dng nh thi to ra ngt, cung cp nhp p mt h iu hnh thi gian
thc hot ng hoc cc tc v c lp lch.1.4 n v bo v b nh (MPU)MPU l mt
thnh phn ty chn ca b vi x l Cortex-M3, c th nng cao tin cy ca h
thng nhng bng cch bo v cc d liu quan trng c h iu hnh s dng khi cc
ng dng khc, tch bit c lp cc tc v ang thc thi bng cch khng cho php
truy cp vo d liu ca nhau, v hiu ho quyn truy cp vo mt s vng nh, cho
php cc vng nh c nh ngha l ch c (read only) v pht hin cc truy cp b
nh c th ph v h thng.MPU cho php mt ng dng c chia nh thnh cc tin
trnh. Mi tin trnh s c b nh (code, d liu, ngn xp, heap) v thit b
ring, cng nh c quyn truy cp vo b nh v cc thit b c chia s. MPU cng c
cc quy tc (rule) truy cp ca ngi dng v c quyn bao gm vic thc thi m
ti mc c quyn thch hp cng nh quyn s hu b nh v cc thit b ca m c quyn
v m ngi dng.MPU chia b nh thnh cc vng ring bit v thc hin vic bo v
bng cch ngn cc truy cp tri php. MPU c th chia b nh thnh ti a 8 vng
trong mi vng c th c chia thnh 8 vng con. Kch thc vng c th bt u t 32
byte v tng gp i dn cho n ti a 4 gigabyte. Cc vng c nh s th t bt u t
0. C th xc nh mt bn b nh (memory map) nn mc nh truy cp c quyn. Vic
truy cp n cc a ch b nh khng c xc nh trong vng MPU hoc khng c php s
to ra ngoi l li v qun l b nh (Memory Management Fault
Exception).Quy tc bo v vng nh c da trn vo loi tc v (c, vit hoc thc
thi) v c quyn ca m thc hin vic truy cp. Mi vng bao gm mt b bit quy
nh loi truy cp c php v hnh ng no c php trn bus. MPU cng h tr cc vng
chng ln nhau (overlapping regions), tc l c s giao nhau cng mt vng a
ch. V kch thc mi vng l bi s ca 2 nn nu 2 vng chng ln nhau th s c th
c mt vng nm hon ton trong vng kia. Do , hon ton c kh nng xy ra trng
hp nhiu vng nm trn trong mt vng hoc trng hp chng lng nhau. Trong
trng hp a ch tra cu nm trong vng chng nhau th kt qu tr v s l vng c
s th t cao nht.1.5 G li (Debug) v theo vt (Trace)Vic g li h thng da
trn b vi x l Cortex-M3 c thc hin thng qua DAP (Debug Access Port),
c th l mt cng SWD (Serial Wire Debug) s dng 2 ng tn hiu hoc mt cng
SWJ-D (Serial Wire JTAG Debug) s dng giao thc JTAG hoc SW. Cc
SWJ-DP mc nh ch JTAG khi reset v c th chuyn giao thc vi mt chui iu
khin c th c cung cp bi phn cng g li bn ngoi.Hnh ng debug c th c kch
hot bi cc s kin khc nhau nh breakpoints, watchpoints, iu kin li hoc
yu cu debug t bn ngoi. Khi mt s kin debug xy ra, b vi x l Cortex-M3
c th vo ch tm dng (halt mode) hoc ch theo di debug. Trong ch tm
dng, b vi x l ngng thc thi hon ton cc chng trnh. Ch ny h tr chy tng
bc. Lc ny, mt ngt pht sinh c th b tr hon p ng, c th c thc thi tng
bc, hoc b che (masked) nn ngt bn ngoi c th b b qua trong qu trnh
debug. Trong ch theo di debug, mt hm x l ngoi l c thc thi thc hin
vic g li trong khi vn cho php cc exception c u tin cao hn din ra.
Ch ny cng h tr chy tng bc.B FPB (Patch Flash and Breakpoint ) c 6
breakpoint trong chng trnh v 2 breakpoint np d liu, hoc chuyn lnh/d
liu t b nh m n b nh h thng. B FPB ny c su comparator so snh cc lnh
c ly t b nh m. Mi comparator c th c kch hot nh v li m chng trnh n
mt vng trong b nh h thng, hoc thc hin mt breakpoint phn cng bng cch
tr v mt lnh breakpoint cho b vi x l. N cng c hai comparator vi nhim
v tng t cho d liu.B DWT (Data Watchpoint and Trace) c bn comparator
c th c cu hnh thnh watchpoint phn cng. Khi c s dng trong cu hnh ny,
comparator c th c lp trnh so snh a ch truy cp d liu hoc b m chng
trnh. Cc DWT comparator cng c th c cu hnh kch hot cc s kin ly mu
PC, s kin ly mu a ch d liu v lm cho ETM (Embedded Trace Macrocell)
pht ra cc gi kch hot trong dng lnh ang c truy vt.ETM l mt thnh phn
ty chn h tr vic theo vt lnh m bo rng c th ti cu trc li vic thc hin
chng trnh m ch nh hng mt cch ti thiu n b nh. ETM cho php truy vt
theo thi gian thc v vic thc thi lnh v truyn d liu bng cch nn thng
tin truy vt t nhn b x l gim thiu yu cu bng thng.
Hnh 8. H thng theo vt Cortex-M3
B vi x l Cortex-M3 thc hin vic theo vt d liu bng DWT v ITM
(Trace Instrumentation Macrocell). DWT cung cp s liu thng k v vic
thc hin lnh v c th to ra s kin watchpoint gi debug hoc ETM trn cc s
kin h thng. ITM l cng c truy vt ng dng h tr cch g li kiu "printf"
cho h iu hnh v theo vt cc s kin ng dng. N chp nhn cc gi truy vt phn
cng t DWT v phn mm theo di s kch thch t li b vi x l v pht ra thng
tin chn on h thng nh k. B TPIU (Trace Port Interface Unit) chp nhn
cc thng tin truy vt t ETM v ITM, sau ha trn chng, nh dng li v pht
ra thng qua SWV (Serial Wire Viewer) n cc b phn tch truy vt bn
ngoi. SWV cho php to ra profile cho cc s kin h thng mt cch n gin v
hiu qu bng cch xut dng d liu thng qua mt pin duy nht. M ha
Manchester v UART l cc nh dng c h tr cho SWV.2.6 Ma trn bus v cc
giao din lin ktMa trn bus ca b vi x l Cortex-M3 kt ni b x l v giao
din debug n cc bus bn ngoi, ICode, DCode v giao din h thng da trn
AMBA AHB-Lite 32 bit, v bus cho cc ngoi vi (Private Peripheral Bus)
da trn AMBA APB 32 bit. Ma trn bus cng m nhim vic truy cp d liu
khng thng hng v cc vng bit-banding. Giao din ICode 32 bit ly cc lnh
t vng nh chng trnh v ch c th truy cp bi CM3Core. Tt c cc ln np lnh
u c rng l mt t (WORD), vi s lng lnh c ly trn mi t ty thuc vo loi m
thc hin v v tr ca n trong b nh. Giao din DCode 32 bit truy cp d liu
t vng nh m chng trnh v c th c truy cp bi CM3Core v DAP. Giao din h
thng 32 bit ly cc lnh v truy cp d liu trong vng b nh h thng v ging
nh bus DCode, c th c truy cp bi CM3Core v DAP. PPB cho php truy cp
vo cc thnh phn bn ngoi ca h thng Cortex-M3.