Bounded Dataflow Networks and Latency Insensitive Circuits Arvind Computer Science and Artificial Intelligence Laboratory MIT Based on the work of Murali Vijayaraghavan and Arvind[MEMOCODE 2009] November 17, 2009 L22-1 http://csg.csail.mit.edu/ korea
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Bounded Dataflow Networks and Latency Insensitive Circuits
Bounded Dataflow Networks and Latency Insensitive Circuits. Arvind Computer Science and Artificial Intelligence Laboratory MIT Based on the work of Murali Vijayaraghavan and Arvind[MEMOCODE 2009]. Modeling of a processor on an FPGA. Exception. Branch Resolution. Reg File. Fetch. Decode. - PowerPoint PPT Presentation
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Bounded Dataflow Networks and Latency Insensitive Circuits
ArvindComputer Science and Artificial Intelligence Laboratory MIT
Based on the work of Murali Vijayaraghavan and Arvind[MEMOCODE 2009]
November 17, 2009 L22-1http://csg.csail.mit.edu/korea
Modeling of a processor on an FPGA
Fetch DecodeExecute/AddrCalc
Mem
RegWrite
Commit
ExceptionBranch Resolution
RegFile
Divide and multiply are resource hogsCan we pipeline or implement them as a multicycle operation
Multiported register file maps poorly on FPGAsCan we map it as a multicycle operation into BRAMs?
CAM for TLBs map poorly on FPGAsCan we implement CAMs as sequential search using BRAMs?
How to do these refinements to Synchronous Sequential Machines (SSMs) without affecting the overall correctness
November 17, 2009 L22-2http://csg.csail.mit.edu/korea
Conventional “modular refining” methodology
Requires re-verificationBesides, in our processor example, after the ad-hoc changes, what are we modeling?
Rest of the design, with ad-hoc modification
Complete Design
Rest of the design
Module to be
refined
Refined module, with changed
timing contract
November 17, 2009 L22-3http://csg.csail.mit.edu/korea
Rest of the design,“wrapped” automatically
Complete Design
Rest of the design
True modular refinement
Module to be
refined
Refined module, with changed
timing contract
Ability to replace any module by an “equivalent” module without affecting the overall correctness
November 17, 2009 L22-4http://csg.csail.mit.edu/korea
Theory of Latency Insensitive Designs by Carloni et. al[ICCAD99, IEEE-TCAD01]
A method to reduce critical wire delays by adding buffers
Module is treated as a black-box and wrapped to make it latency-insensitive to input/output wire latencies
Our goal is to also permit refinements that may change the timing of a module
November 17, 2009 L22-5http://csg.csail.mit.edu/korea
Carloni’s method
SSM1
SSM2 SSM2
SSM1
SSM1patient
Make a cut to include the wires of interest (some restrictions on cuts)
Create wrappers and insert buffers or FIFOs
SSM2patient In patient SSMs the
state change can be controlled by an external wire
November 17, 2009 L22-6http://csg.csail.mit.edu/korea
Bounded Dataflow Networks (BDNs)
Primitive BDNs that directly implement SSMs
Bounded FIFOs, initially empty
Different from a Kahn Network because a send can block
November 17, 2009 L22-7http://csg.csail.mit.edu/korea