Booster Low Level Modules, Timing and some Measurements.

Booster Low Level

Modules, Timing and some Measurements

Questions Questions and/or Points of Interest with respect to Booster LLRF

• 1) System overview – What are the basic building blocks? (functional description)

• 2) How is phase jump at transition implemented?• 3) What distinct modules are involved?• 4) What is the response (low level and high level) to a request for a sudden

change of phase – ROFF, RFSUM change, transition phase jump, etc.?• 5) What limits a change of phase under sudden voltage reduction to 90o or

less? How precise is the limit?• 6) What determines the time constant for a change of phase as seen in the

high level?• 7) Is there any low level control of the slew rate?• 8) Do you have any ideas about why the synchronous phase appears to

approach 170deg just after the transition phase jump when the intensity is high?

• 10) Is there a current comprehensive drawing of the low level system?• 11) Are the block labels readable in a printed version?

Things not discussed

• Cogging

• Snyc. Transfer between Booster and MI

• Bunch Rotation

• Various Timing Modules

• Not much on Booster to Mi phase lock– Craig will discuss upgrades

Injection and Capture modules and parameters

Acceleration and Cogging modules and parameters

Extraction modules and parameters

Three parts to Booster RF cycle

Injection and Capture Modules

CAMAC 071: generates Paraphase Curve Nim Sum Mod : Adds DC offsets to PP curve

Paraphase Turn-on Mod : Shifts the Vector phase of ‘A’ and ‘B’ stations

B:TPPP : Triggers 071 Paraphase curve

B:VFIDR : Injection Frequency Decrement

B:PPOFF : Injection DC level Paraphase offset

B:RFBLON : RF Station ‘A’ and ‘B’ Balancer enable

B:RFBLOF : RF Station ‘A’ and ‘B’ Balancer disable

Paraphase Curve

Beam Capture

• The paraphase curve takes about 600 us.

• The beam gate generator box uses an AM detected signal to produce a logic high beam gate.

• The generation of the beam gate valid will depend upon intensity and paraphase timing relative to injection timing.

• The beam gate signal enables the feedback.

Injection Timing1)RFSUM 2)CHG0 3)Phase Error 4)Beam Gate

Paraphase Turn-on and Sum Box Bandwidth

• The response of the paraphase turn-on module is limited by a multiplier chip. It was required only to be as fast as required by the paraphase CAMAC 071 curve and the transition jump curves. The requirement at transition is a curve that swings 20 volts in 20 us. The sum box bandwidth is about 1 MHz.

Acceleration and Cogging• The Frequency sweeps from 37.7 to 52.82 MHz• The bias and frequency programs start to play at

BDOT level crossing.• Feedback is enabled on valid cycles when Beam

Gate appears.• The low level VXI program is triggered on all

$11, $12, $10. ( B:DDSCTG )• A revolution marker is reset with the chop on

trigger. The marker is used to keep track of bunch # 1 and sampling.

• Cogging is planned to start after transition.

Acceleration/Cogging Feedback

• There are two acceleration feedback systems; radial position and phase feedback.

• A gap detector at long 18 provides the beam phase information.

• A resistive wall (BPM) at long ’18’ provides the position feedback.

• The cogging control of Booster will just be an offset to the radial position feedback.

VXI

Phase Det.

Phase Det.

L18 pickup Wideband Gap

Delay

Phase Shifter

Beam

MI RF

PGMGenerator

ParaphaseTurn-onModule

‘A’ ‘B’

Trans.Trig

Phase ShifterController

Radial Position Det. (L6)RAG / ROF Curves

BdotTrans. Trig

Acceleration Phase Detector

• Type – Overlap• Bandwidth - ~1MhZ• Modified TEV Phase

Detector• Other types could

work but would require phase adjustments

• Being Replaced with log det on VXI card.

RPOS Feedback PathBlock Diagram

Phase Shifter DriveModule

Paraphase turn-onModule

Phase ShifterModule

BPMMod

ROFF RAGBdot

Aux 2 (AC RPOS Damper)

Aux 1 input (Cogging Feedback)

TransitionTrigger

RPERR

PSDRIVE

PSDRIVE

RF (from dist. Box )

“A” “B”

Phase Matched AMPS

Long 18 BPM

BPM LO28.8 MHz above RF~ 1 MHz Bandwidth DDS

Phase Shifter Drive

• Feedback path for Radial Position

• Several Inputs: RPOS,ROF,RAG,BDOT,AC Damper,and Cogging Control

• Uses transition trigger to flip phase

Phase Shift Controller Module

Transition Timing• Three modules are involved in transition:

– Phase Shift Controller– Paraphase Turn-on Module– Paraphase Sum Box

They all get a transition trigger which is an ‘or’ of all transition triggers.

Question

How do we get through transition with high beam current?

Answer the question first.

• At transition we have a situation where we’re current limited but need to drive a large reactive load.

• Tuners are not designed to be fast enough (they are slow compared to synchronous period) so the reactive componet needs to be handled by the tetrode. But since we’re running the stations at full voltage, there is not enough power (or current) to switch the reactive power. Like any filter, the rate at which the circuit cavity responds can be overdriven….if we had more current!

What we do know….what can we do?

• Mis-time transition – Why, because it gives beam a slight energy kick pre-transition.

• Quad Damper…but only works after transition so will not help reduce the bucket reduction at transiton.

• More Anode voltage at transition…no voltage available.

• More RF…means more available volts at transition.

• Slow down ramp…make GMPS work harder.

RF INPUT

X r

LO LO

r X X r r X

B A

INJ

Trans

INJ Trans

Analog CircuitsProduce proper transition curvesTrigger at Transition

Scope Picture 4.5E121)Phase Error 2)Phase Ctrl 3)RPERR 4)Paraphase Jump Ramp

Scope Picture 2.8E12

Scope Plots of Transition 4.5E121) DDS Phase Error2)Phase CTRl Error

3) RPERR 4)Paraphase Turn-on Jump

VXI - LOW LEVEL RF

• This system replaced the VCO about 7 years ago.

• It also replaced the BPM frequency offset module.

• It generates the Bias, LO Frequency, BPM Frequency and phase lock Frequency trigger.

• We have two working modules and one that may be made to work.

• Plans are being made to replace this module.

VXI DDS Details• It runs on a 25 MHz clock.• An application program loads a two 1000 point

curves ( Bias and Frequency.)• The frequency curve is updated every 1 us.• The Bias is updated every 4 us. • The firmware is written in assembly code due to

timing constraints.• The biggest concern is that the DDS’s which

operate at 574.998 MHz are no longer made and we have no spares.

• Newer technology would allow more flexibility.

Response of Old VCODDS has similar response

Extraction – Phase lock

• The phase lock process is enabled by a CAMAC timer B:BMIPLT.

• The VXI puts out a pulse when it reaches a frequency set by B:VPLFRQ.

• The pulse triggers a one-shot that begins the Booster to MI phase lock process.

• Extraction will occur about 2.8ms later.• The error signal B:PLERR is the main

diagnostic on the process.

Extraction PL Phase Detector

• This is a complex phase detection system

• A baseband error signal is compared against an op amp generated exponential curve

• Lots of pots to tune• Timing is a challenge• Large RPOS swing• Less than +/-5deg. jitter• Bunch Rotation also can

occur at the end• Being Upgraded

Questions ? Questions and/or Points of Interest with respect to Booster LLRF

• 1) System overview – What are the basic building blocks? (functional description) DONE

• 2) How is phase jump at transition implemented? DONE• 3) What distinct modules are involved? DONE• 4) What is the response (low level and high level) to a request for a sudden change

of phase – ROFF, RFSUM change, transition phase jump, etc.? DONE• 5) What limits a change of phase under sudden voltage reduction to 90deg or less?

DONE• 6) How precise is the limit? • 7) What determines the time constant for a change of phase as seen in the high

level? Done• 8) Is there any low level control of the slew rate? Done• 9) Do you have any ideas about why the synchronous phase appears to approach

170deg just after the transition phase jump when the intensity is high? YES• 11) Is there a current comprehensive drawing of the low level system? YES• 12) Are the block labels readable in a printed version? YES