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BIRLA VISHWAKARMA MAHAVIDYALAYA
( An Autonomous Institution)
CERTIFICATE
This is to certify that Mr/Miss_________________________
of third year, ID No:________________ has successfully
completed all the practical work in subject name: Applied
Electronics, Subject Code: EC 371 in year 20__/__ at
Electronics & Communication Engineering Department,
BVM Engineering College.
Date:
Sign of Lab Teacher Sign of H.O.D
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SR
No
Experiment Name Page
No
Date Sign
1 To study about measuring Amplitude & Frequency of signal
2 To study about Slew rate of op amp
3 To study about Op amp inverting & Non inverting
configurations
4 To study & perform astable mode of IC555
5 To study & perform monostable mode OF IC555
6 To study & perform linear variable diff. transducer
7 To study about thermocouple
8 To study about working of strain gauge
9 To study about The basic of LDR
10 To study about digital modulation technique
11 To study about MUX AND DMUX
12 To study About flip flop and counter
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Practical: - 1
AIM: - To study about measuring amplitude and frequency of
signal by using CRO APPARATUS: - Function Generator, C.R.O, Connecting Probes.
Figure:-
Fig: Cathode Ray Oscilloscope THEORY:-
Amplitude:
Amplitude is a measure of how big the wave is.
Imagine a wave in the ocean. It could be a little ripple or a
giant tsunami.
1- What you are actually seeing are waves with different
amplitudes.
2- They might have the exact same frequency and
wavelength.
The amplitude of a wave is measured as:
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1. The height from the equilibrium point to the highest point of a crest or
2. The depth from the equilibrium point to the lowest point of a
trough
When you measure the amplitude of a wave, you are really
looking at the energy of the wave.
it takes more energy to make a bigger amplitude wave.
Anytime you need to remember this, just think of a home stereo‟s amplifier… it
Makes the amplitude of the waves bigger by using more electrical energy.
Frequency: When we first started looking at SHM we defined period as the
amount of time it takes for one cycle to complete... seconds per
cycle
Frequency is the same sort of idea, except we‟re just going to
flip things around.
Frequency is a measurement of how many cycles can happen
in a certain amount
of time… cycles per second.
If a motor is running so that it completes 50 revolutions in
one second, I would say that it has a frequency of 50
Hertz.
Hertz is the unit of frequency, and just means how many cycles per second.
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oIt is abbreviated as Hz.
o It is named after Heinrich Hertz, one member of the
Hertz family that made many important
contributions to physic
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in formulas frequency appears as an "f". Since frequency and period are exact inverses of each other, there is a very basic pair of
formulas you can use to calculate one if you know the other…
Procedure:
Connect function generator to C.R.O Measure volts/div for amplitude measurement and multiply
that number to peak to peak divisions on Y-axis. Measure time/div for frequency measurement and
multiply that number to division those are covered by one complete cycle of input sine wave.
Obsrevation Table:-
SR.No amplitude frequency
Conclusion:-
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PRACTICAL-2
AIM : To study about. Slew rate of op amp.
APPARATUS :741 Op Amp, Assorted Resistors, signal generator,
CRO,DMM, power supply, connecting wires, probes,etc.
THEORY:
Rate Slew Rate
An ideal op-amp has an infinite frequency response. This means that
no matter how fast the input changes, the output will be able to keep
up. In a real op-amp, this is not the case.
If the input signal changes too fast then the output will not be able to
keep up. This is defined as slewing and it results in distortion of the output waveform. Stated more formally, Slew Rate = SR = maximum
dvo/dt or the maximum rate at which the output can change without
distorting.
This can be measured by applying a high frequency square wave
signal. The frequency of the waveform should be increase until the waveform becomes a triangular wave.
The slope of the triangular waveform is the slew rate.
(SR = ΔV/ΔT)
In this Op-amp circuit the Rf is zero and we provide input at the non-inverting terminal so this ckt is in voltage follower mode.
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Fig 1.
PROCEDURE:
Connect the circuit as shown in the figure for the 741.
Now apply a 1 kHz frequency and 5 volt peak to peak square
wave at the input terminal.
Now measure the output waveforms and see the changes by
attaching both the channels in CRO.
Now measure the time scale and amplitude difference of the
output wave forms and put the value in the equation and find out
the slew rate of 741C for the given input.
Now change the amplitude and frequency of the input signal and
measure the output waveforms and calculate the slew rate.
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OBSERVATIONS TABLE AND CALCULATIONS:
Input wave forms SR theoretically SR practically
Square wave 5vpp
1khz
Square wave 7 vpp 2khz
Square wave 9 vpp
3khz
CONCLUSION:
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Practical:-3
AIM: To study about Op amp inverting & Non inverting
configurations.
APPARATUS :741 Op Amp, Assorted Resistors, signal generator,
CRO,DMM, power supply, connecting wires, probes,etc
THEORY:
Inverting amplifier
An inverting amplifier uses negative feedback to invert and amplify a
voltage. The Rf resistor allows some of the output signal to be
returned to the input. Since the output is 180° out of phase, this amount is effectively subtracted from the input, thereby reducing the
input into the operational amplifier. This reduces the overall gain of
the amplifier and is dubbed negative feedback.
Zin = Rin (because V− is a virtual ground)
A third resistor, of value , added
between the non-inverting input and ground, while not necessary, minimizes errors due to input bias currents
The gain of the amplifier is determined by the ratio of Rf to Rin. That
is:
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Take Rf = 100KΩ and Rin = 10 KΩ, we get Af =10
Non-inverting amplifier
Amplifies a voltage (multiplies by a constant greater than 1)
Input impedance
R2 = 10K And R1 = 1K
Gain bandwidth product of the op amp,
(A)(fo) = (Af) (Ff)
For 741 fo = 5 Hz and A= 2 X 105
If we adjust the gain Af = 10 we can easily calculate the Bandwidth
Ff of the op amp 741C
PROCEDURE:
As shown in figure connect the circuit on bread board using 741
C op-amps or connect the same circuit by using kit.
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Now for both of the amplifier circuits apply the inputs and check the output wave forms in both circuits.
Compare the waveforms with the input signals and measure the
voltage gain of the circuits. Now for both of the amplifier increase the frequency and meanwhile
check the output waveform on CRO
Plot the Graph on semi log graph paper of Frequency Vs Gain (dB) and determine the value of the bandwidth of the circuit.
Compare with the theoretical values.
OBSERVATIONS TABLE AND CALCULATIONS:
Vin =
Fre
q
Hz
Output
voltage
Vo(inv)
Output
voltage
Vo
(Non-
inv)
Voltag
e Gain
Ad(dB)
(inv)
practic
al
Voltage
Gain
Ad(dB)
(Non-
inv)
practical
Voltage
Gain
Ad(dB)
(inv)
(theoretical)
Voltage
Gain
Ad(dB)
(Non-inv)
(theoretic
al)
CONCLUSION:
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Practical-4
AIM: To study & perform astable mode of IC555.
APPRATUS:555 Timers IC, Resistors, Capacitors, Wires.
THEORY:An actable multi vibrator, often called a free-running
multi vibrator, is a rectangular-wave-generating circuit. This circuit
does not require an external trigger to change the state of the output, hence the name free-running.
However, the time during which the output is either high or low is
determined by two resistors and a capacitor, which are externally connected to the 555 timer. The bellow figure shows the circuit
diagram of the Astable Multi vibrator connected using 555 timers IC.
Initially, when the output is high, capacitor C starts charging toward Vcc through RA and RB. However, as soon as voltage across the
capacitor equals 2/3 Vcc, comparator 1 triggers flip-flop, and the
output switches low as shown in output voltage waveform.
(A) CIRCUIT DIAGRAM OF AN ASTABLE MULTIVIBRATOR
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(B) OUTPUT VOLTAGE WAVEFORM
Now the capacitor starts discharging through RB and transistor Q1.When the voltage across C equals 1/3 Vcc, comparator 2‟s output
triggers the flip-flop, and the output goes high. Then the cycle repeats.
PROCEDURE:
Connect the Resistor, Capacitor with wires with their
respective pins as sown in the circuit diagram.
After the connection measure the resistance value of the
resistors RA and RB.
Measure the value of the voltage across the Capacitor C.
Then see the output voltage waveform on CRO.
Astable 555 Oscillator Charge and Discharge Times
T1=0.693(r1+r2)*C
and
T2=0.693*r2*C
CONCLUSION:
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PRACTICAL:-5
AIM- To study & perform monostable mode OF IC555
Monostable 555 Timer
When a negative ( 0V ) pulse is applied to the trigger input (pin 2) of the Monostable configured 555 Timer oscillator, the internal
comparator, (comparator No1) detects this input and “sets” the state
of the flip-flop, changing the output from a “LOW” state to a “HIGH” state. This action in turn turns “OFF” the discharge transistor
connected to pin 7, thereby removing the short circuit across the
external timing capacitor, C1.
This action allows the timing capacitor to start to charge up through resistor, R1 until the voltage across the capacitor reaches the threshold
(pin 6) voltage of 2/3Vcc set up by the internal voltage divider network. At this point the comparators output goes “HIGH” and
“resets” the flip-flop back to its original state which in turn turns
“ON” the transistor and discharges the capacitor to ground through
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pin 7. This causes the output to change its state back to the original
stable “LOW” value awaiting another trigger pulse to start the timing process over again. Then as before, the Monostable Multivibrator has
only “ONE” stable state.
The Monostable 555 Timer circuit triggers on a negative-going pulse
applied to pin 2 and this trigger pulse must be much shorter than the output pulse width allowing time for the timing capacitor to charge
and then discharge fully. Once triggered, the 555 Monostable will
remain in this “HIGH” unstable output state until the time period set up by the R1 x C1network has elapsed. The amount of time that the
output voltage remains “HIGH” or at a logic “1” level, is given by the
following time constant equation.
T=1.1*R1*C1
Where, t is in seconds, R is in Ω and C in Farads.
555 Timer Example No1
A Monostable 555 Timer is required to produce a time delay within
a circuit. If a 10uF timing capacitor is used, calculate the value of the resistor required to produce a minimum output time delay of 500ms.
500ms is the same as saying 0.5s so by rearranging the formula
above, we get the calculated value for the resistor, R as
R=t/(1.1*C)=0.5/(1.1*10*10^-6)=45.5 kohm
The calculated value for the timing resistor required to produce the required time constant of 500ms is therefore, 45.5KΩ. However, the
resistor value of 45.5KΩ does not exist as a standard value resistor, so we would need to select the nearest preferred value resistor
of 47kΩ which is available in all the standard ranges of tolerance
from the E12 (10%) to the E96 (1%), giving us a new recalculated time delay of 517ms.
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If this time difference of 17ms (500 – 517ms) is unacceptable instead
of one single timing resistor, two different value resistor could be connected together in series to adjust the pulse width to the exact
desired value, or a different timing capacitor value chosen.
We now know that the time delay or output pulse width of a
monostable 555 timer is determined by the time constant of the connected RC network. If long time delays are required in the 10‟s of
seconds, it is not always advisable to use high value timing capacitors
as they can be physically large, expensive and have large value tolerances, e.g, ±20%.
One alternative solution is to use a small value timing capacitor and a much larger value resistor up to about 20MΩ‟s to produce the require
time delay. Also by using one smaller value timing capacitor and
different resistor values connected to it through a multi-position rotary switch, we can produce a Monostable 555 timer oscillator circuit that
can produce different pulse widths at each switch rotation such as the
switchable Monostable 555 timer circuit shown below.
A Switchable 555 Timer
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We can manually calculate the values of R and C for the individual
components required as we did in the example above. However, the choice of components needed to obtain the desired time delay requires
us to calculate with either kilohm‟s (KΩ), Megaohm‟s (MΩ),
microfarad‟s (μF) or picafarad‟s (pF) and it is very easy to end up with a time delay that is out by a factor of ten or even a hundred.
We can make our life a little easier by using a type of chart called a
“Nomograph” that will help us to find the monostable multivibrators
expected frequency output for different combinations or values of both the R and C. For example,
Monostable Nomograph
So by selecting suitable values of C and R in the ranges of 0.001uF to
100uF and 1kΩ to 10MΩ respectively, we can read the expected output frequency directly from the nomograph graph thereby
eliminating any error in the calculations. In practice the value of the
timing resistor for a monostable 555 timer should not be less than 1kΩ or greater than 20MΩ.
Conclusion;-
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PRACTICAL:-6
AIM: To study & perform linear variable diff. transducer(LVDT).
APPARATUS:
LVDT Kit, DMM, Connecting Wires, patch codes.
THEORY:
The linear variable differential transformer (LVDT) is a type
of electrical transformer used for measuring linear displacement. The
transformer has three solenoid coils placed end-to-end around a tube. The centre coil is the primary, and the two outer coils are the
secondaries. A cylindrical ferromagnetic core, attached to the object
whose position is to be measured, slides along the axis of the tube.
An alternating current is driven through the primary, causing a
voltage to be induced in each secondary proportional to its mutual inductance with the primary. The frequency is usually in the range 1
to 10 kHz.
3D View of LVDT
As the core moves, these mutual inductances change, causing
the voltages induced in the secondaries to change. The coils are
connected in reverse series, so that the output voltage is the difference (hence "differential") between the two secondary voltages. When the
core is in its central position, equidistant between the two secondaries,
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equal but opposite voltages are induced in these two coils, so the
output voltage is zero. When the core is displaced in one direction, the voltage in one coil
increases as the other decreases, causing the output voltage to increase
from zero to a maximum. This voltage is in phase with the primary voltage. When the core moves in the other direction, the output
voltage also increases from zero to a maximum, but its phase is
opposite to that of the primary. The magnitude of the output voltage is proportional to the distance moved by the core (up to its limit of
travel), which is why the device is described as "linear". The phase of
the voltage indicates the direction of the displacement.
Because the sliding core does not touch the inside of the
tube, it can move without friction, making the LVDT a highly reliable device. The absence of any sliding or rotating contacts allows the
LVDT to be completely sealed against the environment.
LVDTs are commonly used for position feedback in servomechanisms, and for automated measurement in machine tools
and many other industrial and scientific applications.
An LVDT Displacement Transducer comprises 3 coils; a primary and
two secondary‟s.
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The transfer of current between the primary and the secondary‟s of
the LVDT displacement transducer is controlled by the position of a magnetic core called an armature.
On our position measurement LVDTs, the two transducer
secondaries are connected in opposition.
At the center of the position measurement stroke, the two
secondary voltages of the displacement transducer are equal but because they are connected
in opposition the resulting output from the sensor is zero.
As the LVDTs armature moves away from centre, the result is an increase in one of the position sensor secondaries and a decrease in
the other. This results in an output from the measurement sensor.
With LVDTs, the phase of the output (compared with the
excitation phase) enables the electronics to know which half of the
coil the armature is in.
The strength of the LVDT sensor's principle is that there is no
electrical contact across the transducer position sensing element which for the user of the sensor means clean data, infinite resolution
and a very long life.
Our range of signal conditioning electronics for LVDTs handles
all of the above so that you get an output of voltage, current or serial
data proportional to the measurement position of the displacement transducer.
Advantages:-
Relative low cost due to its popularity.
Solid and robust, capable of working in a wide variety of environments.
No friction resistance, since the iron core does not contact the transformer coils, resulting in an infinite (very long) service life.
High signal to noise ratio and low output impedance.
Negligible hysteresis.
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Infinitesimal resolution (theoretically). In reality, displacement resolution is limited by the resolution of the amplifiers and
voltage meters used to process the output signal.
Short response time, only limited by the inertia of the iron core and the rise time of the amplifiers.
No permanent damage to the LVDT if measurements exceed the designed range.
Disadvantage:-
The core must contact directly or indirectly with the measured
surface which is not always possible or desirable. However, a non-contact thickness gage can be achieved by including a
pneumatic servo to maintain the air gap between the nozzle and
the work piece.
Dynamic measurements are limited to no more than 1/10 of the
LVDT resonant frequency. In most cases, this results in a 2 kHz frequency cap
.
PROCEDURE:
1. Make the necessary connections of available kit.
2. Switch on the unit.
3. Adjust the core position such that output voltage reading will be zero.
4. Apply Displacement gradually to the core of transducer.
5. Measure corresponding electrical output which is directly calibrated as displacement.
6. For every 1mm of displacement of core note the output reading.
7. Repeat the same procedure for different displacement on both sides of center position of core.
8. Tabulate the results.
9. Plot the graph of Displacement of core in mm Vs Output readings.
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OBSERVATION TABLE:
SR.
NO.
Applied Displacement of
core
(mm)
Output meter reading
1
2
3
4
5
6
7
8
9
CONCLUSION:
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PRACTICAL:-7
AIM: To study about thermocouple.
APPARATUS:
Thermocouple, thermometer. Jug of water, D.M.M., etc.
Figure:
THEORY:
Thermocouples are the most commonly used electrical device
for temperature measurement. It is based upon principal of that emf is developed in the closed circuit made up of two dissimilar of the two
metals. If the junction of the two metals are kept at different temperature. Two emf generated is proportion to the temp.
Difference.
Thus pair of two dissimilar metals that is in physical contact with each other forms a thermocouple.
Emf produced;
F=A (∆θ) +B (∆θ) 2
Where,
(∆θ)= TEMPRATURE DIFFERNCE
A & B ARE CONSATANT E=A (∆θ) : (∆θ) = E/A
In a thermocouple temperature measuring circuit the emf setup is measured by sensing a current through a moving coil instrument.
The deflection link directly proposal to the emf. The emf can be
measured by potentiometer
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In practice the temp. Measurement is carried out with two
junctions. One of temperature is reference junction and other expert to
the medium where temp. is to be measured to reference temp. is
usually 0 °C
PROCEDURE:
1. Take the cold water in jug and join the heater. 2. Put the thermometer and thermocouple in it and join the D.M.M.
with the thermocouple.
3. Measure the value Voltage across thermocouple at difference temp. Vary the temp. Up to 100°C.
4. Tabulate the results.
5. Plot the graph of Displacement of core in mm Vs Output readings.
CHARECTERISTIC TABLE:
SR.
NO.
materials
Typical range in (°C)
1 Copper (cu) VS
constantan
-270 TO 400
2 Iron vs constantan -210 TO 1200
3 Chromel vs alumal -270 TO 1370
4 Chromel vs constantan -270 TO 1000
5 (Pt-10% RH) VS (Pt) -50 TO 1768
6 (Pt-13% RH) VS (Pt-6%
RH)
0 TO 1820
7 (Pt-13% RH) VS Pt -50 TO 1768
8 (Ni-Cr-Si) VS (Ni-Si-Mg) -270 TO 1300
CONCLUSION:
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PRACTICAL:8
AIM: To study about working of strain gauge.
APPARATUS:
strain gauge load cell , weights , D.M.M.
THEORY:
The strain gauge is a transducer employing electrical resistance
variation to sense the strain produced by a force or weight. It is a very versatile detector for measuring weight, pressure, mechanical force, or
displacement.
Strain, being a fundamental engineering phenomenon, exists in
all matters at all times, due either to external loads or the weight of
the matter itself. These strains vary in magnitude, depending upon the materials and loads involved. Engineers have worked for centuries in
an attempt to measure strain accurately, but only in the last decade we
have achieved much advancement in the art of strain measurement. The terms linear deformation and strain are synonymous and refer to
the change in any linear dimension of a body, usually due to the
application of external forces. The strain of a piece of rubber, when loaded, is ordinarily apparent to the eye. However, the strain of a
bridge strut as a locomotive passes may not be apparent to the eye.
Strain as defined above is often spoken of as "total strain." Average unit strain is the amount of strain per unit length and has somewhat
greater significance than does total strain. Strain gauges are used to
determine unit strain, and consequently when one refers to strain, he is usually referring to unit strain. As defined, strain has units of inches
per inch.
Strain gauges work on the principle that as a piece of wire is
stretched, its Resistance
changes. A strain gauge of either the bonded or the unbounded type is made of fine wire wound back and forth in such a way that with a
load applied to the material it is fastened to, the strain gauge wire will
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stretch, increasing its length and decreasing its cross-sectional area.
The result will be an increase in its resistance, because the resistance, R, of a metallic conductor varies directly with length, L, and inversely
with cross-sectional area, A. Mathematically the relationship is
R = ρ L/A
Where ρ is a constant depending upon the type of wire, L is the length of the wire in the same units as ρ , and A is the cross-sectional
area measured in units compatible with ρ .
Four properties of a strain gauge are important to consider when it is used to measure the strain in a material. They are:
1. Gauge configuration.
2. Gauge sensitivity. 3. Gauge backing material.
4. Method of gauge attachment.
The sensitivity of a strain gauge is a function of the conductive
material, size, configuration, nominal resistance, and the way the
gauge is energized.
Strain-gauge conductor materials may be either metal alloys or
semiconductor material. Nickel-chrome-iron-alloys tend to yield high gauge sensitivities as well as have long gauge life. These alloys are
quite good when used for dynamic strain measurements, but because
of a high temperature coefficient, they are not as satisfactory for static strain measurements Copper-nickel alloys are generally use
when temperatures are below 500 to 600°F. They are less sensitive to
temperature changes and provide a less sensitive gauge factor than the nickel-chrome-iron alloys. Nickel-chrome alloys are useful in the
construction of strain gauges for high temperature measurements.
In using electric strain gauges, two physical qualities are of
particular interest, the change in gauge resistance and the change in
length (strain). The relationship between these two variables is dimensionless and is called the "gauge factor" of the strain gauge and
can be expressed mathematically as:
GF = ΔR/R
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ΔL/L
In this relationship R and L represent, respectively, the initial resistance and the initial length of the strain gauge wire, while Δ
R and Δ L represent the small changes in resistance and length
which occur as the gauge is strained along with the surface to which it is bonded. The gauge factor of a strain gauge is a measure of the
amount of resistance change for a given strain and is thus an index of
the strain sensitivity of the gauge. With all other variables remaining the same, the higher the gauge factor, the more sensitive the gauge
and the greater the electrical output.
The most common type of strain gauge used today for stress analysis is the bonded resistance strain gauge shown below.
These gauges use a grid of fine wire or a constantan metal foil grid
encapsulated in a thin resin backing. The gauge is glued to the carefully prepared test specimen by a thin layer of epoxy. The epoxy
acts as the carrier matrix to transfer the strain in the specimen to the
strain gauge. As the gauge changes in length, the tiny wires either contract or elongate depending upon a tensile or compressive state of
stress in the specimen. The cross-sectional area will increase for
compression and decrease in tension. Because the wire has an electrical resistance that is proportional to the inverse of the cross-
sectional area, R α L/A a measure of the change in resistance will
produce the strain in the material.
The load cell is used to weight extremely heavy loads. A length of
bar, usually steel ,is used as the active element. The weight of the loads applies a particular stress to the bar. The amount of strain which
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results in the bar for different values of applied stress is determined,
so that the strain may be used as direct measure of the stress causing it.
The load cell is a good example of the use of strain gauges in
weighing operations. It is desirable that the strain-gage measurement system be
stable and not drift with time. In calibrated instruments, the passage of
time always causes some drift and loss of calibration.
The stability of bonded strain-gage transducers is inferior to that of
diffused strain-gage elements. Hysteresis and creeping caused by imperfect bonding is one of the fundamental causes of instability,
particularly in high operating temperature environments.
PROCEDURE:
1. Collect all the equipment required for this practical.
2. Put all the weight sample one by one and measure difference in
voltage. 3. This makes the load cell sensitive to very small values of
applied stress , as well as to extremely heavy loads.
4. Measure the voltage according to load.
CIRCUIT DIAGRAM:
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OBSERVATION TABLE:
SR.NO
LOAD(THEORETICAL)
LOAD SENSED
BY KIT\
(PRACTICAL)
1
2
3
4
5
6
7
8
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9
10
11
CONCLUSION:
PRACTICAL:9
AIM: To study about photoconductive cell LDR
(a) In the power of the incandescent lamp, used to „illuminate‟ the
LDR. (Keeping all the lamps at a fixed distance). (b) In the distance of a incandescent lamp, (of fixed power),
used to „illuminate‟ the LDR.
THEORY:
What is an LDR (Light Dependent Resistor)?
An LDR is a component that has a (variable) resistance that changes
with the light intensity that falls upon it. This allows them to be used
in light sensing circuits.
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A typical LDR
LDR Circuit Symbol
Variation in resistance with changing light intensity
Typical LDR resistance vs light intensity graph
The most common type of LDR has a resistance that falls with an increase in the light intensity falling upon the device (as shown in the
image above). The resistance of an LDR may typically have the
following resistances:
Daylight
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= 5000Ω
Dark = 20000000Ω
You can therefore see that there is a large variation between these figures. If you plotted this variation on a graph you would get
something similar to that shown by the graph shown above.
Applications of LDRs
There are many applications for Light Dependent Resistors. These
include:
Lighting switch
The most obvious application for an LDR is to automatically turn on a
light at a certain light level. An example of this could be a street light or a garden light.
Camera shutter control
LDRs can be used to control the shutter speed on a camera. The LDR
would be used to measure the light intensity which then adjusts the camera shutter speed to the appropriate level.
Example - LDR controlled Transistor circuit
LDR controlled transistor circuit
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The circuit shown above shows a simple way of constructing a circuit
that turns on when it goes dark. In this circuit the LDR and the other Resistor form a simple 'Potential Divider' circuit, where the centre
point of the Potential Divider is fed to the Base of the NPN
Transistor.
When the light level decreases, the resistance of the LDR increases.
As this resistance increases in relation to the other Resistor, which has
a fixed resistance, it causes the voltage dropped across the LDR to also increase. When this voltage is large enough (0.7V for a typical
NPN Transistor), it will cause the Transistor to turn on.
The value of the fixed resistor will depend on the LDR used, the transistor used and the supply voltage
OBSERVATION TABLE:-
If experiment has been conducted by using various sources with
different power ratings.
Voltage OF battery =6V
SR
NO
Source (light intensity) resistance
1 Dark room(0 lux)
2 FTL(1600 lux)
3 flash light(200 lux)
4 FTL with flash light(1600+200)
Advantages of Light sensor
Following are the advantages of Light sensor :
It is easy to integrate with lighting system such as automatic
lighting system.
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It is used for energy consumption or energy management by
automatic control of brightness level in mobile phones and auto
ON/OFF of street lights based on ambient light intensity.
LDR (i.e. photoresistor) based light sensors are available in
different shapes and sizes.
Light sensors need small voltage and power for its operation.
Photoresistors are lower in cost, bi-directional and offer moderate
response time.
Photodiodes offer quick response time, lower in cost and provide
digital output.
Phototransistors are very fast and provide immediate output
compare to photoresistors.
Phototransistors generate high current compare to photodiodes.
Disadvantages of Light sensor
Following are the disadvantages of Light sensor :
LDRs are highly inaccurate with high response time (about 10s or
100s of milliseconds).
Resistance varies continuosly (analog) in photoresistor and are
rugged in nature.
Photodiodes are temperature sensitive and are uni-directional
unlike photoresistors.
Phototransistors can not withstand voltages above 1000 volts.
Phototransistors are vulnerable to surges, spikes and EM energy.
CONCLUSION:-
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PRACTICAL:10
Aim: To study about ASK modulation and demodulation. Apparatus: Data conditioning and carrier modulation transmitting kit,
data reconditioning and carrier demodulation receiving kit, 20MHz CRO, Path cords.
Theory: Amplitude-shift keying (ASK) is a form of modulation that
represents digital data as variations in the amplitude of a carrier wave.
The amplitude of an analog carrier signal varies in accordance with the bit stream (modulating signal), keeping frequency and
phase constant
The level of amplitude can be used to represent binary logic 0s and 1s. We can think of a carrier signal as an ON or OFF switch.
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In the modulated signal, logic 0 is represented by the absence of a carrier, thus giving OFF/ON keying operation and hence the
name given.
On-off keying (OOK) the simplest form of amplitude-shift keying (ASK) modulation that represents digital data as the
presence or absence of a carrier wave.
Carrier modulation is technique by which digital data is made up to
modulate sine wave carrier.
For all types of carrier modulation, the carrier frequency should
be at least two times the modulating frequency to satisfy
Nyquist criteria.
In ask, carrier is transmitted when data is „one‟ and carrier is
rejected when data is „zero‟.
Carrier frequency chosen for ASK is 2MHz.
Carrier generation blocks DCL-005, generates carrier wave
which are phase synchronous with modulating data. This is
ensured by phase lock loop. The PLL is used in multiplier mode.
The VCO of PLL generates frequency 2MHz. Divide by s,
counter is used in feedback to ensure PL goes for 100K if
frequency of data coding clock is around 250 KHz.
Carrier modulation block on DCL-005 consists of an analog
multiplier which acts as an modulating switch. The digital data
is fed to control input and depending upon carrier frequency at
input, various types of carrier modulation techniques like ASK,
FSK, and PSK can be observed for ASK, carrier is converted to
input and other out is grounded.
Figure 1 illustrates a binary ASK signal (lower), together with the binary sequence which initiated it (upper). Neither signal
has been band limited.
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an ASK signal (below) and the message (above)
There are sharp discontinuities shown at the transition points.
These result in the signal having an unnecessarily wide bandwidth. Bandlimiting is generally introduced before
transmission, in which case these discontinuities would be
„rounded off‟. The bandlimiting may be applied to the digital message, or the modulated signal itself.
The data rate is often made a sub-multiple of the carrier frequency. This has been done in the waveform of Figure 1.
One of the disadvantages of ASK, compared with FSK and
PSK, for example, is that it has not got a constant envelope. This
makes its processing (eg, power amplification) more difficult,
since linearity becomes an important factor. However, it does
make for ease of demodulation with an envelope detector
WAVEFORM:
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Procedure:
Connect power supply with power supply to bit DLC-005 and
DLC-006 and switch it “ON ”.
Connect the s-clock snd s-data generated on DLC-005 to coding
clock and input data respectively by means of patch codes
provided.
Connect NRZ-L data input to control unit input of carrier
modulator logic.
Connect carrier component to input-1 and ground the input-2 of
carrier modulation
Connect ASK modulation about i.e modulated output on DCL-
005 to ASK input of ASK modulator on DCL-006 and observe
output wave-form.
Observation:
1. ON KIT DCL-005 :
Input NRZ-L data at control unit
Carrier frequency SW-1
ASK modulated signal at modulated output.
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2. ON KIT DCL-006
ASK modulated signal at ASK input.
ASK demodulated signal at data output.
Frequency Shift Keying (FSK) Modulation and Demodulation.
Apparatus: Data conditioning and carrier modulation - FSK practical
kit, CRO, Probes, connecting wires etc.
Theory:
Frequency-shift keying (FSK) is a frequency modulation
scheme in which digital information is transmitted through discrete frequency changes of a carrier wave.
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The simplest FSK is binary FSK (BFSK). BFSK literally implies using a pair of discrete frequencies to transmit binary
(0s and 1s) information.
With this scheme, the "1" is called the mark frequency and the "0" is called the space frequency.
Frequency Shift Keying (FSK) demodulation is the process of
recovering the original signal by detecting the frequencies
involved in the original modulation.
Typically, this is done with a band pass amplifier tuned to one
of the two frequencies, followed by an amplitude demodulator. The output is the original signal. It is possible, though often
unnecessary, to use two band pass appliers, one for each
frequency, but this is redundant.
Here in our practical kit the carrier frequencies chosen for FSK
modulation are 2MHz and 1MHz. Note that these frequencies are twice grater than modulating signal frequency.
Carrier generation block on kit board generates carrier waves of
2MHz and 1MHz. which are available at SIN1 and SIN2 ports respectively.
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FSK modulator is built around 2 to 1 analog multiplexer, which switches between 2MHz to 1MHz signals for all „one‟ to „zero‟
transition.
FSK demodulator employs PLL logic for recovery of data or original input signal.
The digital PLL forms the heart of this logic. The PLL center frequency and lock range are fixed around 2MHz. so whenever
2MHz signal is transmitted phase detector output goes low.
Thus phase detector output at PLL directly gives original data.
Applications:
Most early telephone-line modems used audio frequency-shift
keying to send and receive data, up to rates of about 300 bits per second. The common Bell 103 modem used this technique, for
example.
Even today, North American caller ID uses 1200 baud AFSK in the form of the Bell 202 standard.
Some early microcomputers used a specific form of AFSK modulation, the Kansas City standard, to store data on audio
cassettes.
AFSK is still widely used in amateur radio, as it allows data transmission through unmodified voice band equipment.
Procedure:
Connect power supply to the practical kit.
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Connect clock and data input signal to coding logic. And to the control input of the FSK modulator.
Connect NRZ-L data input to convert input of carrier modulator
logic.
Connect carrier components SIN1 and SIN2 to input 1 and input
of carrier modulator logic respectively.
Connect the output to the CRO and observe the output
waveforms.
Now connect output of modulator to the demodulator and
observe output on CRO.
Observation:
Different waveforms on different test points given on kit as shown in the graph.
To study about Phase Shift Keying Modulation and Demodulation.
APPARATUS: Data conditioning and carrier modulation transmission kit, Data reconditioning and carrier demodulation receiver kit, 20MHz
dual trace oscilloscope and Patch chords.
THEORY:
In PSK Modulation technique, the modulated output switches
between in phase and out of phase component chosen for PSK
Modulation at 1MHz (0) and 1MHz (180).
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Carrier Modulation block on PSK kit generates carrier waves 1MHz
(0) and 1MHz (180) which are available at SIN2 and SIN2* ports.
The PSK Modulator is built around 2:1 analog multiplexer which
switches between 1MHz (0) and 1MHz (180) signals for all „1‟ and
„0‟.
Phase detector works on the principle of squaring loops. First step in
PSK detection is the SINE to SQUARE wave conversion using a
Schmitt trigger. This enables PSK detector to be built around digital
IC‟s. Divide by 2 counters is used to divide frequency of PLL output
by 2; thus recovering reference carrier.
It is observed that successful operation of PSK detector is fully
dependent on phase component of transmitted modulated carrier.
If phase reversal of modulated carrier along with rising and falling
edges of data is not proper, then the efficient detection of data from
PSK modulated carrier becomes impossible.
It is also known as Phase Reversal Keying (PRK), the modulated
carrier is described as:
e(t) = Ecmax cos(2πfct+Фc) binary 1 Ecmax cos(2πfct+Фc+180
о) binary 0
PSK is digital modulation scheme that conveys data by changing,
modulating the phase of reference signal (the carrier wave).
Any digital modulation scheme uses a finite number of distinct
signals to represent digital data. PSK uses a finite number of phases;
each assigned a unique pattern of binary digits. Usually each phase
encodes an equal number of bits. Each pattern of bits forms the
symbol that is represented by a particular phase.
The demodulator, which is designed specifically for the symbol set
used by the modulator determines the phase of the received signals
and maps it back to the symbol it represents, thus recovering the
original data.
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This requires the receiver to be able to compare the phase of the
received signal to a reference signal - such a system is termed as
coherent.
A convenient way to represent PSK schemes is on a constellation
diagram. Two common examples which can be represented on the
constellation diagram are BPSK, which uses two phases and QPSK,
which uses four phases.
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect power supply with proper polarity to the PSK modulation kit.
2. Connect S-clock and S-data generated on the kit to coding clock and
input data respectively by means of patch codes.
3. Connect NRZ-L to control input of carrier modulation logic.
4. Connect carrier component SIN2 to input1 and SIN2*
to input2 of carrier
modulation logic.
5. Take the waveforms from the output of the carrier modulation logic,
this is your PSK modulated signal.
6. Connect PSK modulated signal output to PSK input of PSK demodulator
and observe the output waveforms.
OBSERVATION:
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When NRZ-L data of control input is provided to the carrier
modulator logic the output obtained is a PSK modulated signal.
In the output waveform, a phase change takes place at zero crossing
point.
When the input changes from 1 to 0 or from 0 to 1 the phase either
leads or lags.
Suppose our data input is 110110, phase change takes place at
second, third and last bits.
So the observed waveforms are as shown below.
WAVEFORM 1:
WAVEFORM 2:
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Conclusion:
Practical:-11
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AIM:-To design and verify the truth table of a 4X1 Multiplexer &
1X4 Demultiplexer.
APPARATUS REQUIRED:
1-Digital ic trainer kit =1
2-or gate IC7432
3-NOR gate IC 7404 4-AND gate(three input) IC 7411
5-connecting wires
THEORY:
Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. The basic
multiplexer has several data input lines and a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally, there are 2
n input lines and n selector lines whose bit
combinations determine which input is selected. Therefore,
multiplexer is „many into one‟ and it provides the digital equivalent of an analog selector switch.
A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2
n possible output lines. The
selection of specific output line is controlled by the values of n
selection lines.
DESIGN:
4 X 1 MULTIPLEXER
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LOGIC SYMBOL:
TRUTH TABLE:
S.No
SELECTION
INPUT OUTPUT
S1 S2 Y
1. 0 0 I0
2. 0 1 I1
3. 1 0 I2
4. 1 1 I3
PIN DIAGRAM OF IC 7411:
CIRCUIT DIAGRAM:
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1X4 DEMULTIPLEXER
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LOGIC SYMBOL:
TRUTH TABLE:
S.No INPUT OUTPUT
S1 S2 Din Y0 Y1 Y2 Y3
1. 0 0 0 0 0 0 0
2. 0 0 1 1 0 0 0
3. 0 1 0 0 0 0 0
4. 0 1 1 0 1 0 0
5. 1 0 0 0 0 0 0
6. 1 0 1 0 0 1 0
7. 1 1 0 0 0 0 0
8. 1 1 1 0 0 0 1
CIRCUIT DIAGRAM:
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PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th
pin is grounded and 14th pin is given +5
V supply.
3. Apply the inputs and verify the truth table for the
multiplexer & DEmultiplexer.
CONCLUTION
Practical:- 12
AIM:- To study About flip flop and counter
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Objectives:
To construct RS, JK, D and T flip-flops and verity their truth tables.
Theory:
In digital circuits, a FIip-FIop is a term referring to an electronic circuit (a bistable
multivibrator) that has two stable states and thereby is
capable of serving as one bit of memory. A flip-flop is usually controlled by one or two control signals and /or a gate or
clock signal. The output often includes the complement as well as the
normal output.
SR FIip-FIop:
The fundamental latch is the simple SR flip-flop, where S and R stand for set and reset respectively. It can be constructed from a
pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.
Normally, in storage mode, the S and R inputs are both low,
and feedback maintains the outputs in a constant state, with Q and the
complement of Q. If S (Set) is given with high while R is held low, then the Q output is forced high, and stays high even after S returns
low; similarly, if R (Reset) is given with high while S is held low,
then the Q output is forced low, and stays low even after R returns low.
JK-FIip-FIop:
The JK flip-flop augments the behavior of the SR flip-flop (J = Set, K
= Reset) by interpreting the S = R = 1 condition as a “flip“ or toggle
command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset
the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical
complement of its current value.
D-FIip-FIop:
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The Q output always takes on the state of the D input at the moment
of a rising clock edge. (or falling edge if the clock input is active low) It is called the D flip-flop for this reason, since the output takes the
value of the D input or Data input, and Delays it by one clock
count. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line.
T-FIip-FIop:
If the T input is high, the T flip-flop changes state
(“toggles“) whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described
by the characteristic equation: A T flip-flop can also be built using a
JK flip-flop (J & K pins are connected together and act as T) or D flip-flop.
Circuit diagrams:
RS FIip FIop Truth table
RS Flip-Flop basic version
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RS Flip-Flop Clocked version
Symbol:
JK FIip-FIop:
Fig.6.3 JK Flip Flop using IC 7476(Power connection, ground
connection, the above are two JK Flip-Flops in a single IC)
Truth table:
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Symbol:
D-FIip-FIop using JK FIip-FIop:
D-Flip-Flop using JK Flip-Flop & its Truth table
Symbol:
TRUTH TABLE
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T-FIip-FIop using JK FIip-FIop:
T-Flip-Flop using JK Flip-Flop & its Truth table
Symbol:
TRUTH TABLE
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Counter
Asynchronous 3-bit up/down counters
By adding up the ideas of UP counter and DOWN counters, we can
design asynchronous up /down counter. The 3 bit asynchronous up/ down counter is shown below.
It can count in either ways, up to down or down to up, based on the
clock signal input.
UP Counting
If the UP input and down inputs are 1 and 0 respectively, then the
NAND gates between first flip flop to third flip flop will pass the non
inverted output of FF 0 to the clock input of FF 1. Similarly, Q output of FF 1 will pass to the clock input of FF 2. Thus the UP /down
counter performs up counting.
DOWN Counting
If the DOWN input and up inputs are 1 and 0 respectively, then the NAND gates between first flip flop to third flip flop will pass the
inverted output of FF 0 to the clock input of FF 1. Similarly, Q output
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of FF 1 will pass to the clock input of FF 2. Thus the UP /down
counter performs down counting.
The up/ down counter is slower than up counter or a down counter, because the addition propagation delay will added to the NAND gate
network
Advantages
Asynchronous counters can be easily designed by T flip flop or D
flip flop.
These are also called as Ripple counters, and are used in low
speed circuits. They are used as Divide by- n counters, which divide the input
by n, where n is an integer.
Asynchronous counters are also used as Truncated counters. These can be used to design any mod number counters, i.e. even
Mod (ex: mod 4) or odd Mod (ex: mod3).
Disadvantages
Sometimes extra flip flop may be required for “Re
synchronization”. To count the sequence of truncated counters (mod is not equal to
2n), we need additional feedback logic.
While counting large number of bits, the propagation delay of asynchronous counters is very large.
For high clock frequencies, counting errors may occur, due to
propagation delay.
Applications of Asynchronous Counters
Asynchronous counters are used as frequency dividers, as divide
by N counters.
These are used for low power applications and low noise
emission. These are used in designing asynchronous decade counter.
Also used in Ring counter and Johnson counter.
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Asynchronous counters are used in Mod N ripple counters. EX:
Mod 3, Mod 4, Mod 8, Mod 14, Mod 10 etc.
CONCLUSION:-