Bill W. Haynes Slide 1 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico Common Design for Multiple Timing Applications Available PLD Based SERDES Devices Time to Digital Converter (TDC) w/ PLD Based SERDES Timing Distribution System (TDS) w/ PLD Based SERDES Other PLD Based SERDES Potential Applications Simulation Results of TDC w/ 400ps Resolution Prototype TDC/TDS Card Status Simulation Only
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Bill W. Haynes Slide 1 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u Common Design for Multiple Timing Applications.
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Bill W. Haynes
Slide 1
February 26, 2002
CKM Precision Timing
CKM Workshop In San Luis Potosi, Mexico
Common Design for Multiple Timing Applications Available PLD Based SERDES Devices Time to Digital Converter (TDC) w/ PLD Based SERDES Timing Distribution System (TDS) w/ PLD Based SERDES Other PLD Based SERDES Potential Applications
Simulation Results of TDC w/ 400ps Resolution
Prototype TDC/TDS Card Status
Simulation Only
Bill W. Haynes
Slide 2
February 26, 2002
CKM Precision Timing
CKM Workshop In San Luis Potosi, Mexico
Available PLD Based SERDES Devices Cypress Programmable Serial Interface (PSI)
CPLD w/ a single channel 2.5Gbs SERDES device Cost ~ $140
Xilinx-II Pro FPGA Up to 16-channel FPGA w/ 3.125 Gbs SERDES devices Not in production & Cost is UNK
Altera Stratix FPGA Up to 80-channel FPGA w/ 800 Mbs SERDES devices Not in production & Cost is UNK
Bill W. Haynes
Slide 3
February 26, 2002
CKM Precision Timing
CKM Workshop In San Luis Potosi, Mexico
High-Resolution TDC Block Diagram
DetectorOutput(CML)
156 MHzRef Clk
Serdes Control
16bit Data
FPGA/CPLD( Cypress / Xilinx )
SerialReceiver(Cypress
/ Xilinx)
General I/O
General I/O
Gen
eral
I/O
Bill W. Haynes
Slide 4
February 26, 2002
CKM Precision Timing
CKM Workshop In San Luis Potosi, Mexico
Programmable TDC Features Resolution of 400ps (or better) is possible
Single channel Cypress PSI w/ 2.5 Gbs SERDES (in production) Multiple channel FPGAs planned by several vendors Single & Multiple channel dedicated SERDES
Available or Planned by several vendors
8 channel TDC at lower resolution (666 ps) 4-channel Cypress device (in production) 8-channel Cypress device (planned)
80 channels at lower resolution (1.25 ns) Altera Stratix FPGA
Not in production
Fully Programmable (VHDL) Backend Timing compensation Interface to external world (PCI, CPCI, etc.) Transmit TDC data over one of the serial links
Bill W. Haynes
Slide 5
February 26, 2002
CKM Precision Timing
CKM Workshop In San Luis Potosi, Mexico
TDC w/ 400ps Resolution Input Pulse Width = FFFF F800 0000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns
T Ref Offset = # of 0 bits from T Ref x 400ps = 0 x 400ps = 0ps
4 –PCI Card w/ a 1.5Gbs Resolution TDC/TDS Design near completion PC board layout will start in March Prototype Testing in May/June Beam Testing in November Test Beam
Bill W. Haynes
Slide 15
February 26, 2002
CKM Precision Timing
CKM Workshop In San Luis Potosi, Mexico
Timing (or Clock) Distribution System (TDS) Discussed at the CKM Ann Arbor Workshop Uses a 2-channel 2.5 Gbs Cypress device Can be converted to a high resolution TDC by:
Setting lock to reference rather than lock to data
Bill W. Haynes
Slide 16
February 26, 2002
CKM Precision Timing
CKM Workshop In San Luis Potosi, Mexico
Timing (or Clock) Distribution System (TDS) The Far-End of the Cable is a Common Reference for all Receivers Reference can be Determined by: T = (Round Trip Time)/2 Or The Time from Incident Wave to the Reflected Wave Divided by Two
I-Wave
R-Wave
Round Trip Time = 2T
I-WaveR-Wave
TfarEnd= (TI-Wave – TR-Wave)/2
I-Wave
R-Wave
TfarEnd= (TI-Wave – TR-Wave)/2
TfarEnd= (TI-Wave – TR-Wave)/2
Bill W. Haynes
Slide 17
February 26, 2002
CKM Precision Timing
CKM Workshop In San Luis Potosi, Mexico
TDS Simpified Block Diagram
Bill W. Haynes
Slide 18
February 26, 2002
CKM Precision Timing
CKM Workshop In San Luis Potosi, Mexico
Other PLD Based SERDES Potential Applications Data Links for DAQ Control & Monitoring Links