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5 Power Supply ........................................................................................................................10 5.1 5V Power Supply ...............................................................................................11 5.2 3.3V Power Supply ............................................................................................11 5.3 2.5V Core Power Supply ...................................................................................11 5.4 3.3V/2.5V Wide Range I/O Power Supply........................................................11
6 Test Points.............................................................................................................................11
8 Schematic..............................................................................................................................12 BGA242: Top Level ....................................................................................................13 BGA242: Test Headers ................................................................................................14 BGA242: TD242LP.....................................................................................................15 BGA242: PC104 Connectors.......................................................................................16 BGA242: Power Distribution ......................................................................................17 BGA242: System CPLD..............................................................................................18 BGA242: USB Ports ....................................................................................................19
TransDimension Inc. BGA242: TD242LP Evaluation Board User’s Guide
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Voltage Regulator
PLL OSC2 CLKW/ CLKCFG
OSC1 48 MHz 12 MHz
/RESET
/CS /WR /RD
A12:A1 D15:D0
INT
TEST
Memory Blocks
OTG Trans- ceiver
Host SIE &
Root Hub
µP Interface
USB Host Controller Registers
System Configuration
& Control
Registers
USB Function Controller Registers
USB Host
Control Logic
Function SIE
USB Trans- ceiver
DM2 DP2
DM1 DP1
/PO /OC
VBus Control Circuit
HNP/ SRP Logic ID
Test Control
ENVREG VREGOUT VBUS /EXVBO
PSH
USB Function Control Logic
H/F
PSFPSH
PSC
VBP
1 TD242LP: USB OTG Host/Function Controller TransDimension’s TD242LP (TDI part number: TDOTG242-000C 64 pin LQFP, and TDOTG242-00BC for 64 pin BGA) is the second controller in the family of integrated low-cost, high-performance, On-the-Go (OTG) controllers. The TD242LP is a combination of a standard USB host controller and an OTG dual-role device controller. Designed specifically for embedded applications with a non-PCI microprocessor interface, this 16-bit interface is ideal for low power mobile applications. It is USB Specification 2.0 compliant, operating at full speed (12Mb/s) and/or low speed (1.5Mb/s). The controller supports all four types of USB transfers: Control, Interrupt, Bulk, and Isochronous with highest data throughput, and lowest interrupt rate among all embedded host controllers on the market. In particular, isochronous performance is guaranteed. The pipe/transfer level programming makes the TD242LP very easy to use, ensuring shortest time-to-market. The block diagram of the TD242LP is shown in Figure 1-1. The TD242LP operational modes are given in Figure 1-2.
Figure 1-1: TD242LP OTG Host/Function Controller
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The TD242LP chip can be configured by software to operate in any of four modes as described in Figure 1-2. Description Hardware HNP
• State machines for both the A-DEVICE and B-DEVICE are updated and tracked by the Hardware. • All timers are started and stopped by the Hardware events. • The OTG port can work either as a USB Host or USB Function, as determined by the automatic
negotiation with the connected remote device. Host Only Mode
• All the ports are USB Hosts. The HNP and Function are disabled. Function Host Mode
• The dual-role USB port operates as a USB Function. The other port will operate as USB Host. The HNP is disabled in this mode.
Software HNP • The TD242LP will allow Software to control the operation of the shared USB port. Software is
responsible for the timing, control of the external charge pump, tracking the HNP state and performing the HNP protocol.
• The shared OTG port can work either as a USB Host or USB Function, as determined by the Software negotiation with the connected remote device. Note: Software HNP is quite CPU intensive.
Figure 1-2: TD242LP Operating modes
The TD242LP is targeted towards embedded applications with low power requirements, especially mobile and post-PC products, including cellular phones, palm platforms, PDAs, STBs, home gateway systems, and Internet appliances. Peer-to-Peer communication is made simple with the TD242LP as USB connectivity is achieved without PC intervention. TransDimension, together with SoftConnex Inc, a wholly owned subsidiary, offer total solutions including controller chips, reference designs and development kits, firmware for microprocessor interfacing, HCD (Host Controller Driver), HNP (Host Negotiation Protocol), SRP (Session Request Protocol) as well as USB host and function stacks running under most real time operating systems.
TransDimension Inc. BGA242: TD242LP Evaluation Board User’s Guide
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TDOTG242LP
Figure 1-5 TD242LP BGA 64-pin package (top view) 2 Microprocessor Interface The TD242LP supports a 16-bit interface whether it be a microcontroller, a microprocessor, or a custom ASIC. Figure 2-1 shows a typical interface between the TD242LP and a microprocessor.
8 7 6 5 4 3 2 1
A B C D E F G H
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Figure 2-1: A typical TD242LP interface to a microprocessor
3 BGA242 Evaluation Board 3.1 General Description The BGA242 (TDI part number TDOTG242-1010) evaluation board is designed for internal software development and customer evaluation of the TD242LP chip. Measured at 4.80 in. (121.9mm) by 3.00 in. (76.2mm), it can be employed to:
• Evaluate TransDimension's TD242LP USB OTG Host/Function Controller; • Run TD242LP demonstrations; • Develop user software for TD242LP based applications; and • Serve as a subassembly in an OEM's product to provide USB OTG Host/Function
Controller. With the block diagram of Figure 2-1, the BGA242 has the following features:
• Onboard TD242LP chip (64-pin, BGA package). • Onboard USB power distribution and over-current protection circuit for host applications. • One mini-AB OTG port and one Type A USB port.
/RESET
TEST
16
OSC1 OSC2
Crystal (Oscillator)
Circuit
GPIOR
A12:A1 D15:D0
12
/CS /WR/RD
INT /INTP
/CSK /WR /RD
A12:A1 D15:D0
Microprocessor
10K
3.3V
3.3V
10K x 4
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• Onboard Dual footprint USB mini-AB OTG socket and a Dual footprint USB Type A socket for host operations.
• Onboard 6 MHz crystal. • Onboard test points for key signal probing. • Support for both self-powered and bus powered USB function. • Standard PC104 connector for interface to PC Motherboard or our PCI104 PCI adaptor
card. • 5V supply through the interfacing connector with LEDs indicating power conditions. • Support for both 2.5V and 3.3V I/O’s. • Low powered 2.5V core operating voltage.
5.0V to 3.3V DC Converter
2.5V Core
3.3V
2.5 or 3.3V I/O
PC104
CONNECTOR
5V
Mictor Test Header
(Optional)
5.0V to 2.5V Converter
Resistor
Port 1 Mini AB
Port 2 Type A
Processor Bus TD242LP
BGA64
VREGOUT
Crystal TPS2044
Figure 3-1 EVB242 Block Diagram
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3.2 Board Operation Requirements The following items are required to operate the BGA242:
• A DC power source capable of supplying 5V±10%@1.5A through a power switch. Regulated power supply is required.
4 Hardware Description/Configuration The BGA242 was designed for either stand alone use or for use in a PCI bus configuration; the BGA242S for standalone and BGA242P for PCI. The PCE242 evaluation system is a combination of the BGA242P and a PCI104 bridge board. Switching in between the two configurations consists of either installing or removing a couple of resistors and moving a jumper. Please refer to the following check lists to see if you have the correct board configuration. 4.1 Default Factory Settings – Standalone Configuration (BGA242S) The default settings support the development of:
• an OTG Dual Role Device (Port 1) and a USB host (Port 2) simultaneously • a self powered or a bus powered USB function port (Port 1) and a USB Host (Port 2)
simultaneously Please double check the factory settings given below before using the board.
4.2 Optional Configuration Installations To use the BGA242 as a USB Host on both ports (Port 1 and Port 2), make the following changes:
• R54: Install for Host Controller operation (R53 must be removed) To use different sources for the I/O Voltage supplies, do one of the following:
• R16: Install to use the Internal OTG_VREG for the 2.5V I/O (R15, R17 removed) • R17: Install to use the external 5V-to-2.5V regulator for the 2.5V I/O (R15, R16
removed) AND R42: Install to disable the Internal OTG_VREG (R41 is removed)
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To use the external regulator as the 2.5V Core Voltage supplies, do the following:
• R18: Install to use the 5V-to-2.5V regulator for the 2.5V core (R19 removed) NOTE: OTG_VREG is the internal voltage regulator inside the TD242LP chip. The internal OTG_VREG can be disabled by installing R42 (R41 removed) and also removing R16 and R19. 4.3 TD242LP Reset The /RESET of the TD242LP is brought out to the PC104 connector. Users can control the /RESET through a GPIO of the MCU as depicted in Fig. 2-1. 4.4 DP/DM Signals Each of the DP/DM pairs has a 2-pin, 0.1” spacing, connector for attaching a differential probe. These traces are impedance controlled to 90 ohms + 10%. 4.5 LEDs The BGA242 board supplies several LEDs to check the normal operation of the board. These LEDs should be green for the functions that are working correctly: D14: 3.3V Power Rail Indicator D2: 2.5V Power Rail Indicator D3: VDDW Power Rail Indicator D4: 5.0V Power Rail Indicator D1: Type A VBUS Power Indicator D5: Mini-AB VBUS Power Indicator 4.6 Oscillator Input The TD242LP supports the use of a 6MHz crystal, or a crystal oscillator of 6, 12, 24 or 48MHz. The 12 or 24MHz crystal oscillator is supported only for the BGA package. A 6MHz crystal or a 6MHz crystal oscillator is recommended for lower EMI. The only footprint provided in the BGA242 board is the use of a 6MHz (default) crystal. 4.7 Mounting Holes The BGA242 board has four unplated standoff holes, one near each corner of the board. Each hole is 0.146” in diameter. The placement matches the PCI104 PCI board. 5 Power Supply Before using the BGA242, one must determine the way the power is applied to the board. Listed below are the configurations for both the core and I/O voltage supplies. The default
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configuration assumes that the user will be using the internal voltage regulator (OTG_VREG) supply for the 2.5V core voltage and the 5V-to-3.3V converter for the 3.3V I/O supply. 5.1 5V Power Supply The BGA242 board will receive its 5V power from one of two sources. The source will be resistor selectable.
1. The PC104 Connector [Default setting]. 2. An external source connecting to a test pin. Protection circuitry is not provided. (remove
R1 and R13) 5.2 3.3V Power Supply The BGA242 board will receive its 3.3V power only from a voltage regulator.
1. The 5V-to-3.3V DC converter. 5.3 2.5V Core Power Supply The BGA242 board will receive its 2.5V core power from one of three sources. The source will be resistor selectable.
1. The TD242LP’s internal regulator output pin, VREGOUT [Default setting]. 2. The 5.0V-to-2.5V DC converter. 3. An external source connecting to a test pin (JP4, pin 3). Protection circuitry is not
provided. The power for the core voltage (VDD2.5 pins) is independent from the power for the I/O voltage, meaning you can drive the core from the internal regulator and drive the 2.5V I/O from the DC converter. 5.4 3.3V/2.5V Wide Range I/O Power Supply The BGA242 board will receive its power from one of three sources. The VDDW (VDD Wide-range) power source will be resistor selectable.
1. From the 3.3V supply directly (3.3V) [Default setting]. 2. The TD242LP’s internal regulator output pin, VREGOUT (2.5V). 3. The 5.0V-to-2.5V DC converter (2.5V). 4. An external source connecting to a test pin (JP3, pin 3). Protection circuitry is not
provided. 6 Test Points The following test points are furnished on the BGA242: Ground Test Points JP1, JP2, JP9 and JP10 VBUS, DP1, DM1, DP2, DM2, VREG_OUT, ID.
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7 References • USB 2.0 Specification (www.usb.org) • USB On-The-Go Supplement to USB 2.0 Specification (www.usb.org) • TD242LP Technical Manual (TDI Document Number: MU4006) 8 Schematic The schematics of the BGA242 are presented on Pages 13-19 of this document. NOTE: The TD242LP also comes in an LQFP64 package which is not shown in the schematics.
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BGA242: Top Level
PO_N
OTG_CSL
RESET_LOCALL
D[7:0]
A11
D6
GPIO8
A4
A7
D[15:0]
RESET_CONN
CPLD_READYL
A2
TD242LP
TD242LP
OTG_INTL
RESET_CONN
OTG_CSL
OTG_WRLOTG_RDL
OTG_D[15:0]
OTG_A[12:1]
OTG_DP1_ROTG_DM1_R
OTG_DP2_ROTG_DM2_R
OTG_ID
OTG_POLOTG_OCL
OTG_EXVBOL
OTG_VBP
OTG_VREG_OUT
OTG_VBUS
RESET_LOCALL
CPLD_CSL
OTG_WRLOTG_INTL
A19
GPIO7
A[19:0]
OTG_INTL
CPLD_READYL
D7 DP1_R
D5
A16
OTG_RDL
A17
Sy stem_CPLD
Sy stem_PLD
RESET_LOCALLRESET_CONN
OTG_RDLOTG_WRL
CPLD_CSL
OTG_CSLA[19:13]
D[7:0]
OTG_CSL_CONN
CPLD_READYLALEL
GPIO7GPIO8
A[3:0]
OTG_RDL
EXT_VBO_N
A9
OC_N
USB_PORTS
USB_PORTS
DP1_RDM1_R
DP2_RDM2_R
ID
PO_NOC_N
EXT_VBO_N
VBPVBUS
OTG_WRL
D4
A8
D1
A1
VBP
D0
OTG_CSL_CONN
DP2_R
A10
RESET_CONN
OTG_CSL
A0
OTG_INTL
A15
CPLD_CSL
VREG_OUT
ALEL
PC104_CONN
PC104_CONN
RESET
SD[15:0]
SA[19:0]
CS1L
/MEMRD/MEMWR
CS2L
OTG_INTL
READYLBALE
GPIO7GPIO8
GPIO7
GPIO8
A3
A[12:1]
RESET_LOCALL
A14
ALEL
OTG_WRL
A3
A5
A1
D3D2
RESET_CONN
A[19:0]
DM2_R
CPLD_READYL
VBUS
Power_Dist
Power_Dist
VREG_OUT
ALEL
OTG_CSL
OTG_CSL_CONN
A13
DM1_RD[15:0]
A18
GPIO8
A[3:0]
A12
BGA242 CARD TOP LEVEL
A[19:13]
A6
SC-OTG242-A2-001 2.1
BGA242 Card : TOP LEVEL
1 7Thursday , July 21, 2005
Title
Size Document Number Rev
Date: Sheet of
RESET_LOCALL
OTG_RDL
A2
D[15:0]
ID
GPIO7
A[19:0]
CPLD_CSLOTG_CSL_CONN
Rev2.1: 1. TD242LP pin B2 to AVDD2.5 from VDD2.5 2. Removed DNI pulldowns on DP/DM
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BGA242: Test Headers
D10
MH's are to be .146" non-plated thru holesPlace one at each corner.