BCM ® Bus Converter Rev 1.7 vicorpower.com Page 1 of 25 07/2015 800 927.9474 BCM ® Bus Converter Fixed Ratio DC-DC Converter S NRTL C US C US ® BCM380x475y1K2A3z Features • Up to 1200 W continuous output power • 1876 W/in 3 power density • 97.9% peak efficiency • 4,242 Vdc isolation • Parallel operation for multi-kW arrays • OV, OC, UV, short circuit and thermal protection • 6123 through-hole ChiP package n 2.494” x 0.898” x 0.286” (63.34 mm x 22.80 mm x 7.26 mm) Typical Applications • 380 DC Power Distribution • High End Computing Systems • Automated Test Equipment • Industrial Systems • High Density Power Supplies • Communications Systems • Transportation Product Description The VI Chip® Bus Converter (BCM®) is a high efficiency Sine Amplitude Converter™ (SAC™), operating from a 260 to 410 VDC primary bus to deliver an isolated, ratiometric output from 32.5 to 51.3 VDC. The BCM380x475y1K2A3z offers low noise, fast transient response, and industry leading efficiency and power density. In addition, it provides an AC impedance beyond the bandwidth of most downstream regulators, allowing input capacitance normally located at the input of a POL regulator to be located at the primary side of the BCM module. With a primary to secondary K factor of 1/8, that capacitance value can be reduced by a factor of 64x, resulting in savings of board area, material and total system cost. Leveraging the thermal and density benefits of Vicor’s ChiP packaging technology, the BCM module offers flexible thermal management options with very low top and bottom side thermal impedances. Thermally-adept ChiP-based power components, enable customers to achieve low cost power system solutions with previously unattainable system size, weight and efficiency attributes, quickly and predictably. This product can operate in reverse direction, at full rated power, aſter being previously started in forward direction. Product Ratings V PRI = 380 V (260 – 410 V) P SEC = up to 1200 W V SEC = 47.5 V (32.5 – 51.3 V) (NO LOAD) K = 1/8
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BCM® Bus Converter Rev 1.7 vicorpower.comPage 1 of 25 07/2015 800 927.9474
BCM® Bus Converter
Fixed Ratio DC-DC Converter
S
NRTLC USC US® S
NRTLC USC US®
BCM380x475y1K2A3z
Features
• Up to 1200 W continuous output power
• 1876 W/in3 power density
• 97.9 % peak efficiency
• 4,242 Vdc isolation
• Parallel operation for multi-kW arrays
• OV, OC, UV, short circuit and thermal protection
• 6123 through-hole ChiP package
n 2.494 ” x 0.898 ” x 0.286 ”
( 63.34 mm x 22.80 mm x 7.26 mm)
Typical Applications
• 380 DC Power Distribution
• High End Computing Systems
• Automated Test Equipment
• Industrial Systems
• High Density Power Supplies
• Communications Systems
• Transportation
Product Description
The VI Chip® Bus Converter (BCM®) is a high efficiencySine Amplitude Converter™ (SAC™), operating from a 260 to 410 VDC primary bus to deliver an isolated, ratiometric outputfrom 32.5 to 51.3 VDC.
The BCM380x475y1K2A3z offers low noise, fast transientresponse, and industry leading efficiency and power density. Inaddition, it provides an AC impedance beyond the bandwidthof most downstream regulators, allowing input capacitancenormally located at the input of a POL regulator to be located atthe primary side of the BCM module. With a primary tosecondary K factor of 1/8 , that capacitance value can bereduced by a factor of 64 x, resulting in savings of board area,material and total system cost.
Leveraging the thermal and density benefits of Vicor’s ChiPpackaging technology, the BCM module offers flexible thermalmanagement options with very low top and bottom sidethermal impedances. Thermally-adept ChiP-based powercomponents, enable customers to achieve low cost powersystem solutions with previously unattainable system size,weight and efficiency attributes, quickly and predictably.
This product can operate in reverse direction, at full ratedpower, after being previously started in forward direction.
Product Ratings
VPRI = 380 V ( 260 – 410 V) PSEC= up to 1200 W
VSEC = 47.5 V ( 32.5 – 51.3 V)(NO LOAD)
K = 1/8
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BCM380x475y1K2A3z + PRM + VTM, Remote Sense Configuration
PRMENABLE
TRIM
SHARE/CONTROL NODE
AL
IFB
VC
VT
VAUX
REF/REF_EN
+IN
–IN
+OUT
–OUT
TM
VC
PC
+IN
–IN –OUT
+OUTAdaptive Loop Temperature Feedback
VTM Start Up Pulse
SGND
SGND
SGND
ISOLATION BOUNDRY LOAD_RTN
VTM
PRIMARY SECONDARY
BCM
VAUX
EN
+VPRI
–VPRI
+VSEC
–VSEC
enable/disableswitch
FUSE
ISOLATION BOUNDRYPRIMARY SECONDARY
TM
RI_PRM_CER
RTRIM_PRM RAL_PRM
SGND
CI_BCM_ELEC
SOURCE_RTN
VPRI
RI_PRM_DAMP
LI_PRM_FLT
RO_PRM_DAMP
LO_PRM_FLT CO_PRM_CER
LOAD
VOUT
CO_VTM_CER
enable/disableswitch
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BCM380x475y1K2A3z
Pin Configuration
1 2
A
B
C
D
E D’
C’
B’
+VPRI +VSEC
TOP VIEW
6123 ChiP Package
A’
VAUX
EN
+VSEC
–VSEC
–VSEC–VPRI
TM
Pin Descriptions
Pin Number Signal Name Type Function
A1 +VPRI
PRIMARY POWER Positive primary power terminal
B1 TM OUTPUT Temperature Monitor; Primary side referenced signals
C1 EN INPUT Enables and disables power supply; Primary side referenced signals
D1 VAUX OUTPUT Auxilary Voltage Source; Primary side referenced signals
E1 – VPRI
PRIMARY POWER RETURN
Negative primary power terminal
A’2, C’2 +VSEC
SECONDARY POWER
Positive secondary power terminal
B’2, D’2 –VSEC
SECONDARY POWER RETURN
Negative secondary power terminal
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Absolute Maximum RatingsThe absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter Comments Min Max Unit
+VPRI_DC to –VPRI_DC -1 480 V
VPRI_DC or VSEC_DC slew rate
(operational) 1 V/µs
+VSEC_DC to –VSEC_DC -1 60 V
TM to –VPRI_DC
-0.3
4.6 V
EN to –VPRI_DC 5.5 V
VAUX to –VPRI_DC 4.6 V
Part Ordering Information
DeviceInput Voltage
RangePackage Type
OutputVoltage x 10
TemperatureGrade
OutputPower
RevisionPackage
SizeVersion
BCM 380 x 475 y 1K2 A 3 z
BCM = BCM 380 = 260 to 410 V P =
ChiP Through Hole 475 = 47.5 V
T = -40 to 125 °C M = -55 to 125 °C
1K2 = 1,200 W A 3 = 6123 0 = Analog
R = Reversible
Standard Models
All products shipped in JEDEC standard high profile (0.400” thick) trays (JEDEC Publication 95, Design Guide 4.10).
Part Number VIN Package Type VOUT Temperature Power Package Size
BCM 380 P 475 T 1K2 A30 260 to 410 V ChiP Through Hole 47.5 V
32.5 to 51.3 V -40 °C to 125 °C 1,200 W 6123
BCM 380 P 475 M 1K2 A30 260 to 410 V ChiP Through Hole 47.5 V
32.5 to 51.3 V -55 °C to 125 °C 1,200 W 6123
BCM 380 P 475 T 1K2 A3R 260 to 410 V ChiP Through Hole 47.5 V
32.5 to 51.3 V -40 °C to 125 °C 1,200 W 6123
BCM 380 P 475 M 1K2 A3R 260 to 410 V ChiP Through Hole 47.5 V
32.5 to 51.3 V -55 °C to 125 °C 1,200 W 6123
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BCM380x475y1K2A3z
Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
General Powetrain PRIMARY to SECONDARY Specification (Forward Direction)
Primary Input Voltage range,continuous
VPRI_DC 260 410 V
VPRI µController VµC_ACTIVEVPRI_DC voltage where µC is initialized,(ie VAUX = Low, powertrain inactive)
LPRI_IN_LEADSFrequency 2.5 MHz (double switching frequency),Simulated lead model
6.7 nH
Secondary Output Leads Inductance(Parasitic)
LSEC_OUT_LEADSFrequency 2.5 MHz (double switching frequency),Simulated lead model
1.3 nH
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Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
General Powetrain PRIMARY to SECONDARY Specification (Forward Direction) Cont.
Effective Primary Capacitance(Internal)
CPRI_INT Effective Value at 380 VPRI_DC 0.37 µF
Effective Secondary Capacitance(Internal)
CSEC_INT Effective Value at 47.5 VSEC_DC 25.6 µF
Effective Secondary OutputCapacitance (External)
CSEC_OUT_EXTExcessive capacitance may drive module into SCprotection
100 µF
Effective Secondary OutputCapacitance (External)
CSEC_OUT_AEXTCSEC_OUT_AEXT Max = N * 0.5 * CSEC_OUT_EXT MAX, whereN = the number of units in parallel
Protection PRIMARY to SECONDARY (Forward Direction)
Auto Restart Time tAUTO_RESTARTStartup into a persistent fault condition. Non-Latchingfault detection given VPRI_DC > VPRI_UVLO+
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
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Attribute Symbol Conditions / Notes Min Typ Max Unit
Protection SECONDARY to PRIMARY (Reverse Direction)
Secondary Overvoltage LockoutThreshold
VSEC_OVLO+ Module latched shutdown with VPRI_DC < VPRI_UVLO-_R 52.5 54.5 56.5 V
Secondary Overvoltage LockoutResponse Time
tPRI_OVLO 100 µs
Secondary Undervoltage LockoutThreshold
VSEC_UVLO- Module latched shutdown with VPRI_DC < VPRI_UVLO-_R 14 15 16 V
Secondary Undervoltage LockoutResponse Time
tSEC_UVLO 100 µs
Primary Undervoltage LockoutThreshold
VPRI_UVLO-_R
Applies only to reversilbe products in forward and inreverse direction; IPRI_DC ≤ 20 while VPRI_UVLO-_R
< VPRI_DC < VPRI_MIN
110 120 130 V
Primary Undervoltage RecoveryThreshold
VPRI_UVLO+_RApplies only to reversilbe products in forward and inreverse direction;
120 130 150 V
Primary Undervoltage LockoutHysteresis
VPRI_UVLO_HYST_RApplies only to reversilbe products in forward and inreverse direction;
10 V
Primary Output Overcurrent TripThreshold
IPRI_OUT_OCP Module latched shutdown with VPRI_DC < VPRI_UVLO-_R 3.5 4 6 A
Primary Output OvercurrentResponse Time Constant
tPRI_OUT_OCP Effective internal RC filter 3.6 ms
Primary Short Circuit Protection TripThreshold
IPRI_SCP Module latched shutdown with VPRI_DC < VPRI_UVLO-_R 5.6 A
Primary Short Circuit ProtectionResponse Time
tPRI_SCP 1 µs
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
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BCM380x475y1K2A3z
16
18
20
22
24
26
28
30
32
34
260 275 290 305 320 335 350 365 380 395 410
Seco
ndar
y O
utpu
t Cur
rent
(A)
Primary Input Voltage (V) ISEC_OUT_DC ISEC_OUT_PULSE
700
800
900
1000
1100
1200
1300
1400
1500
1600
260 275 290 305 320 335 350 365 380 395 410
Seco
ndar
y O
utpu
t Pow
er (W
)
Primary Input Voltage (V) PSEC_OUT_DC PSEC_OUT_PULSE
Figure 1 — Specified thermal operating area
Figure 2 — Specified electrical operating area using rated RSEC_HOT
0102030405060708090
100110
0 10 20 30 40 50 60 70 80 90 100 110
Seco
ndar
y O
utpu
t Cap
acita
nce
(% R
ated
CSE
C_E
XT_M
AX)
Secondary Output Current (% ISEC_OUT_DC)
Prim
ary/
Seco
ndar
yO
utpu
t Pow
er (W
)
Case Temperature (°C) Top only at temperature Top and leads at temperature Top, leads, and belly at temperature
0
200
400
600
800
1000
1200
1400
35 45 55 65 75 85 95 105 115 125
Figure 3 — Specified Primary start-up into load current and external capacitance
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BCM380x475y1K2A3z
Signal Characteristics
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
Temperature Monitor
• The TM pin is a standard analog I/O configured as an output from an internal µC.• The TM pin monitors the internal temperature of the controller IC within an accuracy of ±5°C.• µC 250 kHz PWM output internally pulled high to 3.3 V.
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
• The EN pin is a standard analog I/O configured as an input to an internal µC. • It is internally pulled high to 3.3 V.• When held low the BCM internal bias will be disabled and the powertrain will be inactive. • In an array of BCMs, EN pins should be interconnected to synchronize startup and permit startup into full load conditions.
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
ANALOG
INPUT
StartupEN to Powertrain activetime
tEN_STARTVPRI_DC > VPRI_UVLO+, EN held low bothconditions satisfied for T > tPRI_UVLO+_DELAY
250 µs
Regular
Operation
EN Voltage Threshold VEN_TH 2.3 V
EN Resistance (Internal) REN_INT Internal pull up resistor 1.5 kΩ
EN Disable Threshold VEN_DISABLE_TH 1 V
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BCM380x475y1K2A3z
Auxiliary Voltage Source
• The VAUX pin is a standard analog I/O configured as an output from an internal µC.• VAUX is internally connected to µC output as internally pulled high to a 3.3 V regulator with 2% tolerance, a 1% resistor of 1.5 kΩ.• VAUX can be used as a "Ready to process full power" flag. This pin transitions VAUX voltage after a 2 ms delay from the start of powertrain activating,
signaling the end of softstart.• VAUX can be used as "Fault flag". This pin is pulled low internally when a fault protection is detected.
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
Fault VAUX Fault Response Time tVAUX_FR From fault to VVAUX = 2.8 V, CVAUX = 0 pF 10 µs
Signal Characteristics (Cont.)
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
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BCM380x475y1K2A3z
BCM Module Timing diagram
EN TM+VPR
I
BIDI
R
INPU
T
+VSE
C
OU
TPU
T
VPRI_DCINPUT TURN-O
N SECONDARY O
UTPUT
TURN-ON
PRIMARY IN
PUT OVER
VOLTAGE
VPRI_DCINPUT REST
ART
ENABLE PULLE
D LOW
ENABLE PULLE
D HIGH SHORT CIRCUIT EVENT PRIM
ARY INPUT VOLT
AGE
TURN-OFF
OU
TPU
T
OU
TPU
T
V AU
X
EN & VAUX IN
TERNAL Pull-u
p
STAR
TUP
OVE
R VO
LTAG
EEN
ABLE
CO
NTR
OL O
VER
CURR
ENT
SHU
TDO
WN
µcINITIALIZ
E
VPR
I_O
VLO
-V
PRI_
OVL
O+
VPR
I_U
VLO
+V
µC_A
CTI
VE
VN
OM
V PR
I_U
VLO
-
t SE
C_O
UT_
SC
Pt P
RI_
UV
LO+_
DE
LAY
t VA
UX
t AU
TO-R
ESTA
RT
> t P
RI_
UVL
O+_
DE
LAY
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BCM380x475y1K2A3z
FAULT
SEQUENCE
TM Low
EN High
VAUX Low
Powertrain Stopped
VμC_ACTIVE < VPRI_DC < VPRI_UVLO+
VPRI_DC > VPRI_UVLO+
tPRI_UVLO+_DELAY
expiredONE TIME DELAYINITIAL STARTUPFault
Auto-recovery
ENABLE falling edge,or OTP detected
Input OVLO or UVLO,Output OCP,
or UTP detected
ENABLE falling edge,or OTP detected
Input OVLO or UVLO,Output OCP,
or UTP detected
Short Circuit detected
Applicationof input voltage to VPRI_DC
SUSTAINED
OPERATION
TM PWM
EN High
VAUX High
Powertrain Active
STARTUP SEQUENCE
TM Low
EN High
VAUX Low
Powertrain Stopped
STANDBY SEQUENCE
TM Low
EN High
VAUX Low
Powertrain Stopped
High Level Functional State Diagram
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
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BCM380x475y1K2A3z
Application CharacteristicsProduct is mounted and temperature controlled via top side cold plate, unless otherwise noted. All data presented in this section are collected data formprimary sourced units processing power in forward direction.See associated figures for general trend data.
3456789
1011121314
260 275 290 305 320 335 350 365 380 395 410
PRI t
o SE
C, P
ower
Dis
sipa
tion
(W)
Primary Input Voltage (V) - 40°C 25°C 80°CTTOP SURFACE CASE:
Figure 7 — Efficiency and power dissipation at TCASE = 25 °C
0
10
20
30
40
50
-40 -20 0 20 40 60 80 100
Case Temperature (°C)
25.7 AVSEC_DC:
PRI t
o SE
C, O
utpu
t Res
ista
nce
(mΩ
)
Figure 8 — Efficiency and power dissipation at TCASE = 80 °C Figure 9 — RSEC vs. temperature; Nominal VPRI_DC
ISEC_DC = 19.5 A at TCASE = 80 °C
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BCM380x475y1K2A3z
Figure 12 — 0 A– 25.7 A transient response:CPRI_IN_EXT = 270 µF, no external CSEC_OUT_EXT
Figure 11 — Full load ripple, 270 µF CPRI_IN_EXT; No externalCSEC_OUT_EXT. Board mounted module, scope setting : 20 MHz analog BW
380 VVPRI:
0 10 20 30 40 50 60 70 80 90
100
0.0 5.0 10.0 15.0 20.0 25.0 30.0
Seco
ndar
y O
utpu
t Vol
tage
Rip
ple
(mV)
Secondary Output Current (A)
Figure 10 — VSEC_OUT_PP vs. ISEC_DC ; No external CSEC_OUT_EXT. Boardmounted module, scope setting : 20 MHz analog BW
Figure 13 — 25.7 A – 0 A transient response: CPRI_IN_EXT = 270 µF, no external CSEC_OUT_EXT
Figure 14 — Start up from application of VPRI_DC= 380 V, 50 % IOUT,100% CSEC_OUT_EXT
Figure 15 — Start up from application of EN with pre-applied VPRI_DC = 380 V, 50 % ISEC_DC, 100% CSEC_OUT_EXT
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BCM380x475y1K2A3z
General Characteristics
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
ESD WithstandESDHBM Human Body Model, "ESDA / JEDEC JDS-001-2012" Class I-C (1kV to < 2 kV)
ESDCDM Charge Device Model, "JESD 22-C101-E" Class II (200V to < 500V)
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BCM380x475y1K2A3z
[1] Product is not intended for reflow solder attach.
General Characteristics
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
Soldering[1]
Peak Temperature Top Case 135 °C
Safety
Isolation voltage / Dielectric test VHIPOT
PRIMARY to SECONDARY 4,242
VDCPRIMARY to CASE 2,121
SECONDARY to CASE 2,121
Isolation Capacitance CPRI_SEC Unpowered Unit 620 780 940 pF
Insulation Resistance RPRI_SEC At 500 Vdc 10 MΩ
MTBF
MIL-HDBK-217Plus Parts Count - 25°CGround Benign, Stationary, Indoors /Computer
3.53 MHrs
Telcordia Issue 2 - Method I Case III; 25°CGround Benign, Controlled
3.90 MHrs
Agency Approvals / Standards
cTUVus "EN 60950-1"
cURus "UL 60950-1"
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
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BCM380x475y1K2A3z
C01
C02
Q01
C03
C04
C05
C06
C07
C08
C09
C10
L01
Current Flow detection+ Forward IPRI_DC sense
I PR
I_D
C
Star
tup
Circ
uit
+VPR
I /4
SEPI
C E
N
Cr
CO
UT
+VSE
C
-VSE
C
+VPR
I
-VPR
I
ENTM P
WM
TM
EN
VAU
X
Diff
eren
tial C
urre
nt
Sens
ing
Full-
Brid
ge S
ynch
rono
us
Rec
tific
atio
n
Prim
ary
Stag
e
Fast
Cur
rent
Li
mit
Analog Controller
Digital Controller
SEPI
C
Cnt
rlO
n/O
ff
Q02
Q03
Q04
Q05
Q06
Q07
Q08
Lr
Seco
ndar
y St
age
Q11
Q12
Q09
Q10
+Vcc
-VC
C
3.3v
Li
near
R
egul
ator
+VPR
I /4
( +V P
RI /4
) -X
Slow
Cur
rent
Li
mit
Mod
ulat
or
Prim
ary
and
Seco
ndar
y G
ate
Driv
e Tr
ansf
orm
er
1.5
kΩ
1.5
kΩ
Soft-
Star
t
VAU
X
Ove
r-Te
mp
Und
er-T
emp
Ove
r Vol
tage
U
nder
Volta
ge
Star
tup
/R
e-st
art D
elay
Tem
pera
ture
Se
nsor
BCM Module Block Diagram
The Sine Amplitude Converter (SAC™) uses a high frequency resonanttank to move energy from Primary to secondary and vice versa. (Theresonant tank is formed by Cr and leakage inductance Lr in the powertransformer windings as shown in the BCM module Block Diagram).The resonant LC tank, operated at high frequency, is amplitudemodulated as a function of input voltage and output current. A smallamount of capacitance embedded in the primary and secondary stagesof the module is sufficient for full functionality and is key to achievinghigh power density.
The BCM380x475y1K2A3z SAC can be simplified into the preceedingmodel.
At no load:
VSEC = VPRI • K (1)
K represents the “turns ratio” of the SAC. Rearranging Eq (1):
K =VSEC (2)VPRI
In the presence of load, VOUT is represented by:
VSEC = VPRI • K – ISEC • RSEC (3)
and IOUT is represented by:
ISEC = IPRI – IPRI_Q (4)
K
ROUT represents the impedance of the SAC, and is a function of theRDSON of the input and output MOSFETs and the winding resistance ofthe power transformer. IQ represents the quiescent current of the SACcontrol, gate drive circuitry, and core losses.
The use of DC voltage transformation provides additional interestingattributes. Assuming that RSEC = 0 Ω and IPRI_Q = 0 A, Eq. (3) nowbecomes Eq. (1) and is essentially load independent, resistor R is nowplaced in series with VIN.
The relationship between VPRI and VSEC becomes:
VSEC = (VPRI – IPRI • RIN) • K (5)
Substituting the simplified version of Eq. (4) (IPRI_Q is assumed = 0 A) into Eq. (5) yields:
VSEC = VPRI • K – ISEC • RIN • K2 (6)
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BCM380x475y1K2A3z
+
–
+
–
VOUT
COUTVIN
V•I
K
+
–
+
–
CIN
IOUT
RCOUT
IQ
ROUT
RCIN
25.8 mA
1/8 • ISEC 1/8 • VPRI
CPRI_INT_ESR
21.5 mΩ
1.77 nH
139 mΩ
25.6 µFIPRI_Q
LPRI_IN_LEADS = 6.7 nH ISEC
VPRI
R
SACK = 1/32Vin
Vout+–VPRI
VSEC
RIN
SAC™K = 1/8
Figure 17 — K = 1/8 Sine Amplitude Converter with series input resistor
Figure 16 — BCM module AC model
CSEC_INT
LSEC_OUT_LEADS = 1.3 nH
LPRI_INT = 1.20 µH
CPRI_INT
0.37 µF
24.2 mΩRSEC
CSEC_INT_ESR
510 µΩ
VSEC
Sine Amplitude Converter™ Point of Load Conversion
This is similar in form to Eq. (3), where RSEC is used to represent thecharacteristic impedance of the SAC™. However, in this case a real R onthe primary side of the SAC is effectively scaled by K2 with respect to the secondary.
Assuming that R = 1 Ω, the effective R as seen from the secondary side is 16 mΩ, with K = 1/8 .
A similar exercise should be performed with the additon of a capacitoror shunt impedance at the primary input to the SAC. A switch in serieswith VPRI is added to the circuit. This is depicted in Figure 18.
A change in VPRI with the switch closed would result in a change incapacitor current according to the following equation:
IC(t) = CdVPRI (7)dt
Assume that with the capacitor charged to VPRI, the switch is openedand the capacitor is discharged through the idealized SAC. In this case,
IC= ISEC • K (8)
substituting Eq. (1) and (8) into Eq. (7) reveals:
ISEC =C • dISEC (9)K2 dt
The equation in terms of the output has yielded a K2 scaling factor forC, specified in the denominator of the equation.
A K factor less than unity results in an effectively larger capacitance onthe secondary output when expressed in terms of the input. With a K= 1/8 as shown in Figure 18, C=1 μF would appear as C= 64 μF whenviewed from the secondary.
Low impedance is a key requirement for powering a high-current, low-voltage load efficiently. A switching regulation stage should haveminimal impedance while simultaneously providing appropriatefiltering for any switched current. The use of a SAC between theregulation stage and the point of load provides a dual benefit of scalingdown series impedance leading back to the source and scaling up shuntcapacitance or energy storage as a function of its K factor squared.However, the benefits are not useful if the series impedance of the SACis too high. The impedance of the SAC must be low, i.e. well beyond thecrossover frequency of the system.
A solution for keeping the impedance of the SAC low involvesswitching at a high frequency. This enables small magnetic componentsbecause magnetizing currents remain low. Small magnetics mean smallpath lengths for turns. Use of low loss core material at high frequenciesalso reduces core losses.
The two main terms of power loss in the BCM module are:
n No load power dissipation (PPRI_NL): defined as the power used to power up the module with an enabled powertrainat no load.
n Resistive loss (RSEC): refers to the power loss across the BCM® module modeled as pure resistive impedance.
The above relations can be combined to calculate the overall moduleefficiency:
h =PSEC_OUT =
PPRI_IN – PPRI_NL – PRSEC (12)PIN PIN
=VPRI • IPRI – PPRI_NL – (ISEC)2 • RSEC
VIN • IIN
= 1 – (PPRI_NL + (ISEC)2 • RSEC)VPRI • IPRI
C
S
SACK = 1/32Vin
Vout+–
VPRI
VSECCSAC™
K = 1/8
Figure 18 — Sine Amplitude Converter with input capacitor
S
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BCM® Bus Converter Rev 1.7 vicorpower.comPage 21 of 25 07/2015 800 927.9474
BCM380x475y1K2A3z
Input and Output Filter Design
A major advantage of SAC™ systems versus conventional PWMconverters is that the transformer based SAC does not require externalfiltering to function properly. The resonant LC tank, operated atextreme high frequency, is amplitude modulated as a function of inputvoltage and output current and efficiently transfers charge through theisolation transformer. A small amount of capacitance embedded in theprimary and secondary stages of the module is sufficient for fullfunctionality and is key to achieving power density.
This paradigm shift requires system design to carefully evaluateexternal filters in order to:
n Guarantee low source impedance:To take full advantage of the BCM module’s dynamic response, the impedance presented to its input terminals must be low from DC to approximately 5 MHz. The connection of the bus converter module to its power source should be implemented with minimal distribution inductance. If the interconnect inductance exceeds 100 nH, the input should be bypassed with a RC damper to retain low source impedance and stable operation. With an interconnect inductance of 200 nH, the RC damper may be as high as 1 μF in series with 0.3 Ω. A single electrolytic or equivalent low-Q capacitor may be used in place of the series RC bypass.
n Further reduce input and/or output voltage ripple without
sacrificing dynamic response:Given the wide bandwidth of the module, the source response is generally the limiting factor in the overall system response. Anomalies in the response of the source will appear at the output of the module multiplied by its K factor.
n Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
induce stresses:The module primary/secondary voltage ranges shall not be exceeded. An internal overvoltage lockout function prevents operation outside of the normal operating input range. Even when disabled, the powertrain is exposed to the applied voltage and power MOSFETs must withstand it.
Total load capacitance at the output of the BCM module shall notexceed the specified maximum. Owing to the wide bandwidth and lowoutput impedance of the module, low-frequency bypass capacitanceand significant energy storage may be more densely and efficientlyprovided by adding capacitance at the input of the module. Atfrequencies <500 kHz the module appears as an impedance of RSEC
between the source and load.
Within this frequency range, capacitance at the input appears aseffective capacitance on the output per the relationship defined in Eq. (13).
CSEC_EXT =CPRI_EXT (13)
K2
This enables a reduction in the size and number of capacitors used in atypical system.
Thermal Considerations
The ChiP package provides a high degree of flexibility in that it presentsthree pathways to remove heat from internal power dissipatingcomponents. Heat may be removed from the top surface, the bottomsurface and the leads. The extent to which these three surfaces arecooled is a key component for determining the maximum power that isavailable from a ChiP, as can be seen from Figure 1.
Since the ChiP has a maximum internal temperature rating, it isnecessary to estimate this internal temperature based on a real thermalsolution. Given that there are three pathways to remove heat from theChiP, it is helpful to simplify the thermal solution into a roughlyequivalent circuit where power dissipation is modeled as a currentsource, isothermal surface temperatures are represented as voltagesources and the thermal resistances are represented as resistors. Figure19 shows the “thermal circuit” for a VI Chip® BCM module 6123 in anapplication where the top, bottom, and leads are cooled. In this case,the BCM power dissipation is PDTOTAL and the three surfacetemperatures are represented as TCASE_TOP, TCASE_BOTTOM, and TLEADS. Thisthermal system can now be very easily analyzed using a SPICEsimulator with simple resistors, voltage sources, and a current source.The results of the simulation would provide an estimate of heat flowthrough the various pathways as well as internal temperature.
Alternatively, equations can be written around this circuit andanalyzed algebraically:
TINT – PD1 • 1.24 = TCASE_TOP
TINT – PD2 • 1.24 = TCASE_BOTTOM
TINT – PD3 • 7 = TLEADS
PDTOTAL = PD1+ PD2+ PD3
Where TINT represents the internal temperature and PD1, PD2, and PD3
represent the heat flow through the top side, bottom side, and leadsrespectively.
Figure 19 — Top case, Bottom case and leads thermal model
Figure 20 — Top case and leads thermal model
1.28 °C / W
1.28 °C / W 7.9 °C / W
1.28 °C / W
1.28 °C / W 7.9 °C / W
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BCM380x475y1K2A3z Figure 20 shows a scenario where there is no bottom side cooling. Inthis case, the heat flow path to the bottom is left open and theequations now simplify to:
TINT – PD1 • 1.24 = TCASE_TOP
TINT – PD3 • 7 = TLEADS
PDTOTAL = PD1 + PD3
Figure 21 shows a scenario where there is no bottom side and leadscooling. In this case, the heat flow path to the bottom is left open andthe equations now simplify to:
TINT – PD1 • 1.24 = TCASE_TOP
PDTOTAL = PD1
Please note that Vicor has a suite of online tools, including a simulatorand thermal estimator which greatly simplify the task of determiningwhether or not a BCM thermal configuration is valid for a givencondition. These tools can be found at:http://www.vicorpower.com/powerbench.
Current Sharing
The performance of the SAC™ topology is based on efficient transfer ofenergy through a transformer without the need of closed loop control.For this reason, the transfer characteristic can be approximated by anideal transformer with a positive temperature coefficient seriesresistance.
This type of characteristic is close to the impedance characteristic of aDC power distribution system both in dynamic (AC) behavior and forsteady state (DC) operation.
When multiple BCM modules of a given part number are connected inan array they will inherently share the load current according to theequivalent impedance divider that the system implements from thepower source to the point of load.
Some general recommendations to achieve matched array impedancesinclude:
n Dedicate common copper planes within the PCB to deliver and return the current to the modules.
n Provide as symmetric a PCB layout as possible among modules
n An input filter is required for an array of BCMs in order to prevent circulating currents.
For further details see AN:016 Using BCM Bus Converters in High Power Arrays.
Fuse Selection
In order to provide flexibility in configuring power systems VI Chip® modules are not internally fused. Input line fusing of VI Chip products is recommended at system level to provide thermalprotection in case of catastrophic failure.
The fuse shall be selected by closely matching system requirements with the following characteristics:
n Current rating
(usually greater than maximum current of BCM module)
n Maximum voltage rating
(usually greater than the maximum possible input voltage)
n Ambient temperature
n Nominal melting I2t
n Recommend fuse: ≤ 5 A Bussmann PC-Tron
Reverse Operation
BCM modules are capable of reverse power operation. Once the unit isstarted, energy will be transferred from secondary back to the primarywhenever the secondary voltage exceeds VPRI • K. The module willcontinue operation in this fashion for as long as no faults occur.
Transient operation in reverse is expected in cases where there issignificant energy storage on the output and transient voltages appearon the input.
The BCM380T475P1K2A3R and BCM380M475P1K2A3R are bothqualified for continuous operation in reverse power condition. Aprimary voltage of VPRI_DC > VPRI_UVLO+_R must be applied first allowingprimary reference controller and power train to start. Continuousoperation in reverse is then possible after a successful startup.
BCM® Bus Converter Rev 1.7 vicorpower.comPage 23 of 25 07/2015 800 927.9474
BCM380x475y1K2A3z
BCM Module Through Hole Package Mechanical Drawing and Recommended Land Pattern
11.40.449
22.80±.13.898±.005
31.671.247
63.34±.382.494±.015
0
0
0
0
TOP VIEW (COMPONENT SIDE)
1.52.060
(2) PL.
1.02.040
(3) PL.
11.43.450
1.52.060
(4) PL.
0
30.9
11.
217
30
.91
1.21
7
0
2.75.108
8.25.325
2.75.108
8.25.325
8.00.315
1.38.054
1.38.054
4.13.162
8.00.315
0
0
BOTTOM VIEW
.41.016
(9) PL.
4.17.164
(9) PL.
7.26±.05.286±.002
SEATING.
PLANE
.05 [.002]
2.03.080
PLATED THRU.25 [.010]
ANNULAR RING(2) PL.
1.52.060
PLATED THRU.25 [.010]
ANNULAR RING(3) PL.
2.03.080
PLATED THRU.38 [.015]
ANNULAR RING(4) PL.
0
2.75±.08.108±.003
8.25±.08.325±.003
2.75±.08.108±.003
8.25±.08.325±.003
8.00±.08.315±.003
4.13±.08.162±.003
1.38±.08.054±.003
1.38±.08.054±.003
8.00±.08.315±.003
0
30.9
1±.0
81.
217±
.003
30
.91±
.08
1.21
7±.0
03
0
0
+VPRI
TM
EN
VAUX
-VPRI
+VSEC
+VSEC
-VSEC
-VSEC
RECOMMENDED HOLE PATTERN(COMPONENT SIDE)
NOTES:
1- RoHS COMPLIANT PER CST-0001 LATEST REVISION.2- UNLESS SPECIFIED OTHERWISE, DIMESIONS ARE MM / [INCH].
BCM® Bus Converter Rev 1.7 vicorpower.comPage 24 of 25 07/2015 800 927.9474
BCM380x475y1K2A3z
Revision History
Revision Date Description Page Number(s)
1.6 05/15 Previous version of part #BCM380x475y1K2A30 n/a
1.7 07/14/15 Multiple updates. Additional new products. all Analog HV BCM qualified for continuous reversible operations.
BCM® Bus Converter Rev 1.7 vicorpower.comPage 25 of 25 07/2015 800 927.9474
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