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Jun 03, 2018

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    MOS Transistor Theory

    1.2.3 MOSFET Operation Modes

    Figure 1.9: Basic MOSFET channel formation

    n-channel MOSFET:

    Source electrode (n+ region) is at the lowest potential

    Source potential is the reference potential for all voltages:VDS=VD VS, VGS=VG VS, VSB = (VS VB) (1.61)

    VSB >0 because VB must be more negative than VSto make sure that the pn-junctionfrom bulk to source is reverse biased.

    VLSI Design

    Course 1-13 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    MOSFET operation Modes: Cutoff, Nonsaturation, Saturation

    Cutoff: VGS< VT

    Figure 1.10: MOSFET in cutoff mode

    Nonsaturation: VGS VT and VDS (VGS VT)Saturation: VGS VT and VDS (VGS VT)

    VLSI Design

    Course 1-14 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Figure 1.11: MOSFET in nonsaturation mode

    Figure 1.12: MOSFET in saturation mode

    VLSI Design

    Course 1-15 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    1.2.4 MOSFET current characteristic

    The Gradual Channel Approximation

    analysis with the gradual channel approximation=reduction of the three-dimensionalproblem to a one-dimensional current flow problem

    approximation describes very well large devices analysis first done for VS = 0 assumption for derivation of GCA equations: depletion charge is supported entirely by

    the vertical electric fieldEx(y); (assume VT0(QB0) indep. ofV(y))

    Figure 1.13: MOSFET geometry used in GCA (MOSFET in linear/nonsaturated region)

    The channel electric field Ey(y) is established by the drain source voltageVDS is

    Ey(y) = dV(y)dy

    (1.62)

    with V(y= 0) =VS= 0, V(y = L) =VDS.The depletion depth has its maximum at the drain electrode because V(y) has a maximum aty= L:

    Xdm(y)

    2SiqNa

    [2|F|+ V(y)] (1.63)

    The inversion charge density as a function of the position y is given by

    QI(y = 0) =

    Cox[VGS

    VT] (1.64)

    QI(y) = Cox[VGS VT V(y)] (1.65)The resistance for a differential channel increment dy is

    dR= dynW QI(y)

    = dy

    A [] (1.66)

    VLSI Design

    Course 1-16 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Figure 1.14: Geometry for GCA current analysis

    with A : channel cross sectionn : electron surface mobilityW : channel width : conductivity

    Rearranging

    dV = IDdR= IDdynW QI(y)

    (1.67)

    IDL0

    dy = nWVDS0

    QI(V)dV (1.68)

    and Integration yields

    ID = nCoxW

    L

    VDS0

    (VGS VT V)dV (1.69)

    = kW

    L

    (VGS VT)VDS 1

    2V2DS

    (1.70)

    with the process transconductance parameter k = nCox AV2 and the device transconduc-tance parameter = kWL[A/V

    2].

    VLSI Design

    Course 1-17 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    MOSFET Current Equations

    The resulting equation from the GCA for the nonsaturated current in a conveniant form is

    ID =

    2[2(VGS VT)VDS V2DS] (1.71)

    At the onset of saturation the current ID reaches a peak value and remains constant in the

    Figure 1.15: Nonsaturated MOS current

    saturation region:ID

    VDS= 0 = (VGS VT VDS) (1.72)

    Evaluation of the derivation yields

    VDS,SAT = VGS VT (1.73)

    ID,SAT = ID(VDS=VDS,SAT) = 2

    (VGS VT)2 (1.74)

    parabolic border between saturation and nonsaturation.

    VLSI Design

    Course 1-18 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Figure 1.16: Basic MOSFET characteristics

    Figure 1.17: Start of Saturation in a MOSFET

    Channel length modulation in saturation

    The effective channel lenght in saturation is L = L L.From GCA:

    QI(L) = 0 (1.75) V(L) VDS,SAT (1.76)

    (VDS,SAT =VGS VT0no inversion charge is induced).L may be approximated as a depletion region for a one-sided pn junction with a voltageVDS VDS,SATacross it.

    L

    2SiqNa

    [VDS VDS,SAT] (1.77)

    VLSI Design

    Course 1-19 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Figure 1.18: Channel length modulation

    The saturated current is modified to

    ID k

    2

    W

    L(VGS VT)2 (1.78)

    ID01 LL

    (1.79)

    with

    ID0 =

    2(VGS VT0)2.

    Using the empirical relation

    1L

    L 1 VDS (1.80)with [V1] the channel length modulation factor and assuming that VDS 1 the currentcan be represented by

    ID = ID01 VDS

    = ID01 VDS

    1 + VDS1 + VDS

    = ID0(1 + VDS)

    1 (VDS)2

    1

    (1.81)

    ID ID0(1 + VDS) = 2

    (VGS VT0)2(1 + VDS) (1.82)

    has typical values from 0.1 to 0.01V1 and represents the influence of VDS on ID insaturation. is important in small geometrie devices. In the following exercises we willneglect.

    VLSI Design

    Course 1-20 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Figure 1.19: MOSFET characteristics with channel length modulation

    1.2.5 Biased MOSFET Current Equations

    Figure 1.20: General MOSFET bias

    VT = VT0+ (

    2|F|+ VSB

    2|F|) (1.83)ID 0 (VGS< VT) (1.84)ID =

    2

    2(VGS VT)VDS V2DS

    (VGS> VT, VDS< VDS,sat) (1.85)

    VDS,sat = VGS VT (1.86)ID =

    2(VGS VT)2(1 + VDS) (VGS> VT, VDS VDS,sat) (1.87)

    VLSI Design

    Course 1-21 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Figure 1.21: Body bias effects

    1.2.6 Measurement of device parameters

    Figure 1.22: Device parameter measurement (a)

    Get

    (1) VT0from intercept

    (2) k = k W

    L from slope:

    k =

    2ID

    VGS VT(3) =

    VT(VSB) VT02|F|+ VSB

    2|F|

    and from

    (4) ID2

    ID1=

    1 + VD21 + VD1

    VLSI Design

    Course 1-22 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Figure 1.23: Device parameter measurement (b)

    1.2.7 The Complete MOSFET GCA Analysis

    includes additional depletion charge created by the channel voltage V(y), which is reversebias across the n+p junction at the channel-substrate boundary

    assumeVS = 0 = VB calculation for nonsaturated MOSFET

    VT0(V) =VFB+ 2|F|+q DICox

    + 1

    Cox

    2qSiNa(2|F|+ V) (1.88)

    The basic GCA integral

    ID=

    VDS0

    [VGS VT0(V) V] dV (1.89)

    is modified to (now: VT0 not constant and dependent ofQB0)

    ID =

    VDS

    0

    VGS VFB 2|F| qDI

    Cox V 1

    Cox

    2qSiNa(2|F|+ V)

    dV (1.90)

    which gives for the nonsaturated drain current

    ID =

    VGS VFB 2|F| qDI

    Cox

    VDS1

    2V2DS

    23Cox

    2qSiNa[(2|F|+ VDS)3/2 (2|F|)3/2]

    . (1.91)

    Introduction of a reduction factor M

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    MOS Transistor Theory

    Figure 1.24: Comparision of circuit equations with the complete GCA model

    Figure 1.25: Comparision of modified circuit equations with the complete GCA model

    1.2.8 Depletion mode nchannel MOSFET

    only used in NMOS as load device.

    VLSI Design

    Course 1-24 Darmstadt University of Technology

    Institute of Microelectronic Systems

  • 8/12/2019 basic_mos

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    MOS Transistor Theory

    With the donator implant dose DI, VT is modified to

    VT =VFB+ 2|F|+ 1Cox

    2qSiNa(2|F|+ VSB) qDI

    Cox(1.94)

    so thatVT of a depletion MOSFET is negative. The n-type layer resulting from donor doping

    Figure 1.26: Depletion-mode MOSFET

    is modeled by(Nd Na)> 0. (1.95)

    The currentID can be modeled by

    ID= n

    W

    L

    VDS0

    QC(V)dV (1.96)

    with QC(V) the channel charge density

    QC(V) = Qn+ QS(V) + Qj(V) (1.97)

    VLSI Design

    Course 1-25 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Figure 1.27: Simplified depletion-mode MOSFET model

    Qn: total charge density of electrons in then-type layer

    QS: MOS surface charge density (VFB gives the voltage necessary to create a charge-neutralflatband state at the surface of the semiconductor)

    Qj: amount of depletion charge on then-side of the pn junction n-type layersubstrate

    Qn = q(Nd Na)a (1.98)QS(V) = Cox[VGS VFB V] (1.99)Qj(V) =

    2qSiN(0+ V) (1.100)

    0 kTq

    ln(Nd Na)Na

    N2i

    (built-in voltage) (1.101)

    N = (Nd Na)Na(Nd Na) + Na

    = NaNd

    (Nd Na) (1.102)

    Using these charge densities gives

    ID = n

    W

    L

    VDS0

    [q(Nd Na)a + Cox(VGS VFB V)

    2qSiN(0+ V)]dV

    =

    q(Nd Na)a

    CoxVDS+

    (VGS VFB)VDS 1

    2V2DS

    23Cox

    2qSiN[(0+ VDS)

    3/2 (0)3/2]

    . (1.103)

    This equation is too complicate for hand-calculations, so usually the D-mode MOSFET isdescribed by

    ID =

    2[2(VGS VT0)VDS V2DS], (1.104)

    VLSI Design

    Course 1-26 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    whereVT0< 0. Saturation current:

    ID,sat=

    2(VGS+ |VT0|)2 (1.105)

    Application of D-mode MOSFETs often as Depletion load (saturation region):

    Figure 1.28: Depletion-mode MOSFET characteristics

    VLSI Design

    Course 1-27 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Figure 1.29: Square root of saturated depletion-mode MOSFET current

    1.2.9 pchannel MOSFET

    Figure 1.30: p-channel MOSFET

    The source electrode is connected to VDD.

    VLSI Design

    Course 1-28 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Threshold voltage:

    VTP=GS 2Fn 1Cox (QSS+ Qox) 1Cox QBnFn=

    kTq ln

    Ndni

    > 0 Nd: n type substrate doping

    QBn=2qSiNd[2Fn+ VBSp]VTp=VTOp p

    VBSp+ 2Fn

    2Fn

    with p=

    2qNdSiCox

    (1.106)

    VTp is negative for enhancement p-channel MOSFET. Current equations are similar to n-channel MOSFET but all the signs are opposite.

    1.2.10 Conclusions

    VLSI Design

    Course 1-29 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    n channel transistor p channel transistorFermipotential

    Fp = kT

    q lnniNa

    < 0 Fn = kT

    q ln Ndni

    > 0

    Threshold Voltagepositive negative

    VTn =VT0n+ n

    (|2Fp| VBS)|2Fp |

    VTp =VT0p p

    (VBSp+ 2Fn)

    2Fn

    n =

    2qNaSi/Cox p =

    2qNdSi/Cox

    Current Equations

    Cutoff :VGS< VTn |VGS| < |VTp|ID = 0 ID = 0

    Nonsaturation

    VGS> VTn and VDS

    (VGS

    VTn)

    |VGSp

    |>

    |VTp

    | and

    |VDSp

    | |VGSp

    VTp

    |ID =

    n2

    2(VGSn VTn)VDSn V2DSn

    IDp =

    p2

    2(VSGp+ VTp)VSDp V2SDp

    Saturation

    VGS> VTn and VDS (VGS VTn) |VGSp | > |VTp| and |VDSp| |VGSp VTp|

    ID = n

    2(VGS VTn)2 ID = p2(VSGp+ VTp)2

    1.2.11 Modelling the MOS Transistor for Circuit simulation

    MOSFET SPICE Parameters

    SPICE=(Simulation Program with IC Emphasis)

    VLSI Design

    Course 1-30 Darmstadt University of Technology

    Institute of Microelectronic Systems

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    MOS Transistor Theory

    Symbol Name Parameter Units Default Example

    LEVEL Model Index 1VT0 VTO Zero-bias threshold voltage V 0.0 1.0k KP Transconductance parameter A/V2 2.0E-5 3.1E-5

    GAMMA Bulk threshold parameter V1/2 0.0 0.372|F| PHI surface potential V 0.6 0.65 LAMBDA Channel-length modulation 1/V 0.0 0.02rd RD Drain ohmic resistance 0.0 1.0rs RS Source ohmic resistance 0.0 1.0Cbd CBD Zero-bias B-D junction capacitance F 0.0 2.0E-14Cbs CBS Zero-bias B-S junction capacitance F 0.0 2.0E-14Is IS Bulk junction saturation current A 1.0E-14 1.0E-150 PB Bulk junction potential V 0.8 0.87

    CGSO Gate-source overlap capacitanceper meter channel width F/m 0.0 4.0E-11

    CGDO Gate-drain overlap capacitanceper meter channel width F/m 0.0 4.0E-11

    CGBO Gate-bulk overlap capacitanceper meter channel length F/m 0.0 2.0E-10

    RSH Drain and source diffusionsheet resistance / 0.0 10.0

    Cj0

    CJ Zero-bias bulk junction bottom capacitanceper square meter of junction area F/m2 0.0 2.0E-4m MJ Bulk junction bottom grading coefficient 0.0 0.5

    CJSW Zero-bias bulk junction sidewall capacitanceper meter of junction perimeter F/m 0.0 1.0E-9

    m MJSW Bulk junction sidewall grading co efficient 0.33JS Bulk junction saturation current

    per square meter of junction area A/m2 1.0E-8tox TOX Oxide thickness m 1.0E-7 1.0E-7NA or ND NSUB Substrate doping 1/cm

    3 0.0 4.0E15QSS/q NSS Surface state density 1/cm

    2 0.0 1.0E10NFS Fast surface state density 1/cm2 0.0 1.0E10TPG Type of gate material 1.0

    +1 opposite to substrate-1 same as substrate

    0 Al gateXj XJ Metallurgical junction depth m 0.0 1.0E-6LD LD Lateral diffusion m 0.0 0.8E-6 UO Surface mobility cm2/Vs 600 700

    VLSI Design

    Course 1-31 Darmstadt University of Technology

    Institute of Microelectronic Systems