basic Real Time Arbitrary Generator with Dynamic Memory

basic Real Time Arbitrary Generator with Dynamic Memory

Real-Time Arbitrary Generator

• By: Jonathan CohenItamar Friedman

• Instructor: Michael Yampolsky

• At the High Speed Digital System Lab

basic Real Time Arbitrary Generator with Dynamic Memory

Presentation main topics:• The Idea• Requirements• Preliminary Functional Spec• Initial Design (very shortly)• Time Schedule

Real-Time Arbitrary Generator

The Idea:• The Motivation:

• The bottleneck of Arbitrary generator manufacturers is the static memory component.•What makes it a bottleneck:

• It’s Slow• It’s Expensive• It’s embedded into the board

Real-Time Arbitrary Generator

The Idea:• Our Solution:

• Dynamic Memory• such as: DDR2 or DDR3• fast • cheap• easy to replace

Real-Time Arbitrary Generator

The Idea:• Why did not the industry developed Arbitrary generator with dynamic memory until now:

• Real-Time problems:• refreshing• memory control

• Paradigm:• POC?

Real-Time Arbitrary Generator

Requirements:

• Our main Goal:

POC – basic Arbitrary Generator based on Dynamic Memory

RTAG

Real-Time Arbitrary Generator

Requirements:

• 1: The RTAG Gets the Data (waves samples) from the DSP• 2: The RTAG streams the Data forward, starting on trigger (cyclic)

DSP RTAG D/A1 2

Real-Time Arbitrary Generator

Requirements:• Read and Write, simultaneously• Sends Data synchronically• Streams the Data forwards:

• Beside to a initial delay (one clock from trigger) , streams the Data continuously• Output signals frequency rates:

10Hz-50 MHz• Input & Output width: 16 bit

Real-Time Arbitrary Generator

RTAG

Preliminary Functional SPEC:• 1:

• Gets sample wave writes Commands:

• Wave Number (identifier)• Number of points• Data (the wave)

• Gets trigger commands:• which wave to stream on trigger• the trigger

RTAG1 2

Real-Time Arbitrary Generator

Preliminary Functional SPEC:

• 2: Sends Data (to DAC) :• synchronically• cyclic• output streaming frequency rate by request

Real-Time Arbitrary Generator

RTAG1 2

Initial Design:

• RTAG

ControllerController

Real-Time Arbitrary Generator

MCMC

FIFOFIFO

Time Schedule:• Tasks:

• Acquaintance:• GiDEL Tools• Altera Tools• Synthesis Tools• Verilog• DDRs• …

0weeks 14weeks

Real-Time Arbitrary Generator

Time Schedule:• Tasks:

• Understanding fully the project Requirements & functional Spec• Thinking about the Architecture• Planning detailed time schedule

(more specific than it is today)

• We are Here Today

0weeks 14weeks

Real-Time Arbitrary Generator

Time Schedule:• Tasks:

• Design:• FPGA:

• controller, Data Path, …• Board:

• connections• DAC• etc…

0weeks 14weeks

Real-Time Arbitrary Generator

Time Schedule:• Tasks:

• Presentations:• Mid:

• design • Final:

• Thus Far - Final report• Tasks for Second semester

0weeks 14weeks

Real-Time Arbitrary Generator

Time Schedule:

• Tasks:• Implementation:

• RTAG infrastructure• A basic running system

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Real-Time Arbitrary Generator

Time Schedule:• Next Semester:

• Implementation• Verification, Testing, Reviewing• Final tuning• presentations & Final report

Real-Time Arbitrary Generator

0weeks 14weeks

See You Next Time:

• Real Time Arbitrary Generator with dynamic memory• Jony & Ita• HS-DSL: Spring 2009

Real-Time Arbitrary Generator