Basic Building Block

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All possible questions ofAll Unit.

Question set I & II with

all who likely to get failedin Exam.

Objective Questions 10

each Day.

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CPU Organization

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Functional Units

Input

Output

CentralProcessing

Unit (CPU)

Memory

Inter-connect

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ALU

ControlUnit

Registers

Internal Bus

CPU

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CPU Function:

To rfor th followin ov r and ov r

a ain fro th o nt ow r is turn d on

to th o nt it is r ov d:

Fetch an instruction from memory

Execute that instruction

Thats it. Period.

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Operation

There are four steps all CPU use in the operation.

Fetch Retrieving Instruction from program memory by PC.

Decode

Instruction broken up in to parts. Opcode state which operation to perform.

Execute Various portion of CPU are combine foroperation.

Write back Writeresult in eitherregisterOrin Main Memory.

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CPU - ALU

Flags

(Z,N,C,V)

Function:+,-,OR,AND,

OperandA

Operand Result

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CPU - IR The instruction is typically brought in from a

place in memory (more later) and stor ed

temporarily in the CPU in a r egister called the

Instruction Register.

The controlblock can then read the IR and

figure out where to get the operands for the

ALU, what to do with them (the function), andthen where to put the results.

How does the CPU know where to get the

next instruction from?

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CPU - PC There is a r egister in the CPU called the

Program Counter orPC.

When yourprogram is first executed, the PCholds the address in memory of the first

instruction.

nce the instruction has been fetched from

memory, the PC is incremented to point to thenext instruction.

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CPU - Updated

ALU

Status Reg

IR

PCControl andTiming

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CPU: Control Unit

It is thebrain orcoordinator of theISP(instruction set processor) as it ensures that theprocessor will behaveexactly as defined by itsinstruction set.

Theprocessor repeatedly fetches an instruction from thememory,

interprets its functionality, and

executes it.

This activity is carried out in an InstructionFetch/ExecuteCycle and is repeated once thesystempower is turned on.

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CPU - Updated

ALU

Status Reg

IR

Control andTiming

D1

D2

D3D4

D5

D6

D7

D0

PC

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CPU - emory The CPU interacts with the external

memory through a pair of buff ers that ar e

usually hidden from the programmer. These are the Memory Address Register

(MAR) and the Memory Data Register

(MDR).

These buffers ar e connected dir ectly to thepins on the chip that carry the address and

data signals to the external memory.

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CPU - Updated

ALU

Status Reg

IR

Control andTiming

D1

D2

D3

D4

D5

D6

D7

D0

PC

MDRMAR

Data BusAddress

Bus

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Address registers provide flexibility by

allowing indirect addr essing of memory

locations.

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CPU - Updated

ALU

IR

Control andTiming

D1

D2

D3

D4D5

D6

D7

D0

MDRMAR

Data usA ress

us

0781532 16

A1

A2

A3

A4A5

A6

USP

A0

PC

SSP

01532 16

0 01622

UserSystem

07815

Status

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Instruction Cycle

IncrementPC

FetchInstructionatPC intoIR

ExecutetheInstruction

Halt

Start

DecodeIR

FetchOperands(asrequired)

FetchCycle

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FPU - IEEE Standard

SIGN EXPONENT MANTISSA

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