I MPROVED COMPACT GATE C-V MODEL FOR ULTRATHIN HIGH - k DIELECTRICS A thesis submitted for the partial fulfillment of the requirement of the degree of Bachelor of Science By Md. Itrat Bin Shams (Student No. 0006026) K. M. Masum Habib (Student No. 0006012) Rajib Mikail (Student No. 0006065) Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka-1000 October, 2006
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IMPROVED COMPACT GATE C-V MODEL FOR
ULTRATHIN HIGH-k DIELECTRICS
A thesis submitted for the partial fulfillment of the requirement
of the degree of
Bachelor of Science
By
Md. Itrat Bin Shams (Student No. 0006026)
K. M. Masum Habib (Student No. 0006012)
Rajib Mikail (Student No. 0006065)
Department of Electrical and Electronic Engineering,
Bangladesh University of Engineering and Technology,Dhaka-1000
Table 2.3: Barrier height of different dielectric materials for holes
These values can only be used if a high-k material exists adjacent to Si substrate.
2.6.3 Effective Masses
In all the cases Si substrate is considered to have geometry identical to (111) structure.
Negligible error occurs if (111) structure is considered in case of others.
Case Effective mass, m0
Holes 0.25me
Electrons 0.53me
Table 2.4: Values of effective masses
Theory 37
Here, me is the mass of electron = 9.1 ×10−31 kg.
Chapter 3
Simulations and Results
Main drawback of previously published compact model [11] is its independence of λ
and γ with doping concentration Na,d and characteristics of dielectric material (φb, Na,d, k
and m∗) and characteristic of gate metal (φm). Without considering these effects, accu-
rate C-V characteristics cannot be generated. It is seen that variation of γ with Na,d
or φb does not have considerable impact on C-V curves. But variation in λ leads to
reasonable change in C-V curve’s slope. However, from our simulations it is observed
that the variation of λ with k, m∗ and φm is insignificant. Thus the Eqn. 1.1 reduced
to,
λ = f(φb, Na,d) (3.1)
In this chapter, the method of extracting λ from simulation results will be presented
first. It will be followed by the graphical representation of dependence of λ with Na,d
and φb for both electrons (n-MOS inversion and p-MOS accumulation) and holes (p-
MOS inversion and n-MOS accumulation). And then the unknown function 3.1 will
also be presented. Finally, the validation of our model will be justified by verifying the
simulation result with published experimental data.
Simulations and Results 39
3.1 Determination of λ
To evaluate λ, a self-consistent simulator is used [9] to calculate the first eigenenergy.
To extract λ, E1 vs. Fox curve is drawn. Both axes are taken to be logarithmic. This will
show a line which is about straight. A best fit line is drawn through them as shown
in Fig. 3.1-3.4. Slope of this line is required λ. The method is repeated for different
substrate doping concentrations (Na,d) and different dielectric materials (φb).
The equation obtained from the best fitting is,
y = a + bx (3.2)
where, a = γ, b = λ, x = log(Fox) and y = log(E1)
3.1.1 Observations on Values of λ
We took six dielectric materials for this purpose. These are Si3N4, HfO2, ZrO2, TiO2,
Y-O-Si and Ta2O5. Plots of eigenenergy vs. oxide field is shown in Fig. 3.1 and Fig. 3.2
for holes. In Fig. 3.3 and Fig. 3.4 eigenenergy vs. oxide field for electrons is shown
with Si3N4 and Al2O3 as gate dielectric material. Here change in λ for three different
doping densities is also seen. Clearly λ does not show a constant value as in [11].
Li et al. [11] proposed λ to be 0.61 for electrons and 0.64 for holes. But their model
is accurate for only SiO2 and SiO2 gate stack materials. Pure high-k dielectrics have
no interfacial layer and hence barrier height in these conditions cannot be taken to
be equal to that of SiO2. More the deviation of the value of barrier height φb from
SiO2 value, more is the chance of error in C-V characteristics. Li et al. also proposed
λ to be independent of doping density Na,d. But our self-consistent simulator shows
significant variations in λ with Na,d. It is evident that C-V curves will show variations
in the shape with the change of Na,d. So this variation has to be taken into account for
accurate simulation of C-V curves.
Variation of λ suggests that as we change dielectric materials, dependence of first
eigenenergy E1 on oxide field Fox changes. This is due to fact that for different di-
3.2 Graphical Representation of λ with φb and Na,d 40
Figure 3.1: E1 vs. Fox for holes. Gate dielectric used is Y-O-Si for three differentdoping densities, 1016, 1017 and 1018 cm−3.
electric materials, the barrier height (φb) is also different.
When Na,d is varied, the triangular well becomes steeper or narrower. So it is expected
that E1 would be different for change in Na,d. These changes are not incorporated in
model of Li et al. [11]. It will be shown later that these factors are essential for accurate
modeling of high-k dielectric C-V characteristics.
3.2 Graphical Representation of λ with φb and Na,d
In this section dependence of λ with φb and Na,d is shown graphically. In Fig. 3.5 and
3.6 λ is shown as a function of φb and Na,d respectively for holes. In Fig. 3.7 and 3.8
variation of λ for electrons is given.
As shown in the figures λ increases with increasing barrier height φb of dielectric ma-
Simulations and Results 41
Figure 3.2: E1 vs. Fox for holes. Gate dielectric used is HfO2 for three differentdoping densities, 1016, 1017 and 1018 cm−3.
terials. But it decreases with the increase in doping density Na,d. This phenomenon is
seen for both electrons and holes. Physical explanation is given below.
3.2.1 Physical Explanation of λ Variation
λ vs. φb curve follows a typical exponential rising characteristics. More value of λ
means first eigenenergy E1 is more dependent on oxide field Fox. As φb increases, left
margin of potential well in MOSFET also increases. This makes eigenenergies to be
spaced with more difference from each other. As γ is constant, λ is the only value to
support it. Only increasing λ can prove this theory. On the other hand λ decreases
with Na,d increase. A higher doping concentration is responsible for steeper nature of
wells. Higher Na,d means lower width of potential well. Eigenenrgies is placed with
less differences in a steeper well. Lower value of λ can prove this point. For this reason
3.3 Empirical Function for λ 42
Figure 3.3: E1 vs. Fox for electrons. Gate dielectric used is Si3N4 for three differ-ent doping densities, 1016, 1017 and 1018 cm−3.
λ decreases with increasing Na,d.
3.3 Empirical Function for λ
It is complex to determine λ from the above plots for different φb and Na,d. Again
here only a few values of φb and Na,d are shown. For any intermediate value, we need
interpolation technique. But this is not users friendly. For this reason two equations
are formed to calculate λ for holes and electrons. Curve fitting technique is used for
equation extraction. As λ is a function of both φb and Na,d, two dimensional equation is
given. Though this equation seems a little cumbersome, but it is the best to determine
all the values of λ for any values of φb and Na,d accurately.
Empirical equation that represents function 3.1 to determine λ for holes (p-MOS inver-
Simulations and Results 43
Figure 3.4: E1 vs. Fox for electrons. Gate dielectric used is Al2O3 for threedifferent doping densities, 1016, 1017 and 1018 cm−3.
sion, n-MOS accumulation) is given below.
λ =P1 × φb + P2
φb + P3(3.3)
Figure 3.5: λ vs. φb for different doping densities for holes.
3.3 Empirical Function for λ 44
Figure 3.6: λ vs. Na,d for different barrier heights for holes.
Figure 3.7: λ vs. φb for different doping densities for electrons.
Simulations and Results 45
where, impurity concentration, Nimp = Na,d(cm−3)
1017
And,
P1 = −8.1362× 10−5N5imp + 0.00294612N4
imp − 0.031948N3imp + 0.11673N2
imp
−0.108347Nimp + 0.06338(3.4)
P2 = −0.0010917N5imp + 0.03941614N4
imp − 0.524591N3imp + 1.52233917N2
imp
−1.283078Nimp + 0.3197(3.5)
P3 = −0.001635424N5imp + 0.059014N4
imp − 0.63485N3imp + 2.2672N2
imp
−1.867476Nimp + 0.06223
(3.6)
Equation to calculate λ for electrons (n-MOS inversion, p-MOS accumulation) is given
below.
λ =P1 × φb + P2
φb + P3(3.7)
where, impurity concentration, Nimp = Na,d(cm−3)
1017
Figure 3.8: λ vs. Na,d for different barrier heights for electrons.
3.4 Validity of Improved Compact Model 46
0 1 2 3 4 5
0.48
0.52
0.56
0.601.5x1015 cm-3
2x1018 cm-3
5x1017 cm-3
Simulation Equation (3 )
b (eV)Barrier Height,
.3
Figure 3.9: Variation of λ with φb for holes for different doping densities (Na,d).Both original simulated curves and equation fitted curves are given.
And,
P1 = −5.005× 10−5N5imp + 0.0018148N4
imp − 0.0197407N3imp + 0.072722N2
imp
−0.07048Nimp + 0.6391(3.8)
P2 = −9.755× 10−5N5imp + 0.00358048N4
imp − 0.039882N3imp + 0.15386N2
imp
−0.1683Nimp + 0.04982(3.9)
P3 = −6.1225× 10−5N5imp + 0.00230055N4
imp − 0.02676054N3imp + 0.11142N2
imp
−0.1431Nimp + 0.1184
(3.10)
λ can be calculated from the above equations for any dielectric material and doping
density. We have varified our equation approach by plotting curves from the equation
over the original curve. This is shown in Fig. (3.9). This shows the accuracy of our
proposed method.
3.4 Validity of Improved Compact Model
We have verified our proposed compact model by comparing Capacitance-Gate volt-
age characteristics obtained from our model with the one from both experiment and
Simulations and Results 47
compact model introduced by Li et al [11]. Our model shows less error in all the cases.
This makes our model more valid for high-k dielectrics.
3.4.1 Comparison of C-V Characteristics for Holes
We took four experimental C-V curves for comparison for holes (p-MOS inversion and
n-MOS accumulation). In each case two more C-V curves are generated with compact
model by Li et al [11] and our improved compact model. All three curves are placed in
same co-ordinate. For Li et al.’s model C-V λ = 0.64 for holes is used. Our model’s λ
value is determined from equation (3.3).
Fig. 3.10 shows experimental and simulated C-V for MOSFET having Y-O-Si as the
dielectric material [29]. We have used Na = 1× 1017 cm−3, EOT = 1.15 nm and φb = 4.5
eV. Here VFB = -0.74 V. VFB and Na are calculated from the experimental C-V curve. λ
from Eqn. (3.3) is 0.595. (3.11) shows error for Li’s model and our model. Clearly our
model is more accurate at normal operating gate voltage. Maximum error from model
of [11] is 3.2% and from our model is 1.1%.
Figure 3.10: C-V curves for YOSi as gate dielectric material. Here doping den-sity Na = 1× 1017 cm−3, EOT = 1.15 nm.
3.4 Validity of Improved Compact Model 48
Fig. 3.12 shows experimental and simulated C-V for ZrO2 dielectric material [30]. Data
used here are Na = 2.1 × 1015 cm−3, EOT = 1.1 nm and φb = 2.0 eV. Here VFB = -0.38
V. VFB and Na are calculated with the help of the algorithm stated in theory section.
λ from Eqn. 3.3 is 0.60. Fig. 3.13 shows error for model of Li et al. and our model.
Here also our model shows less error than the model of [11]. Maximum error from Li’s
model is 3% and of our model is 1%.
Another C-V comparison is made in Fig. 3.14. Here nitrided ZrO2 is used as gate
dielectric material [30]. Data used here are Na = 2.1 × 1015 cm−3, EOT = 0.87 nm and
φb = 1.8 eV. Though general barrier height of ZrO2 is 2.0 eV, here 1.8 eV is used to make
compromise with nitride layer in the high-k ZrO2. This value of φb is taken from the
findings of Ahmad et al [7]. Here VFB = -0.80 V. VFB and Na are calculated in the same
way as before. λ from Eqn. 3.3 is 0.60. Fig. 3.15 shows error for model of Li et al.
and our model. Our model shows less error than Li et al.’s model. Maximum error of
model of [11] is 5.1% and of our model is 2.1%.
Final C-V comparison is given in Fig. 3.16. Here Si3N4 is used as gate dielectric material
[31]. Value of parameters are Na = 3.7 × 1017 cm−3, EOT = 1.56 nm and φb = 2.0
Figure 3.11: Error curve for YOSi as gate dielectric material.
Simulations and Results 49
Figure 3.12: C-V curves for ZrO2 as gate dielectric material. Here doping den-sity Na = 2.1× 1015 cm−3, EOT = 1.1 nm.
Figure 3.13: Error curve for ZrO2 as gate dielectric material.
3.4 Validity of Improved Compact Model 50
Figure 3.14: C-V curves for nitrided ZrO2 as gate dielectric material. Here dop-ing density Na = 2.1× 1015 cm−3, EOT = 0.87 nm.
Figure 3.15: Error curve for nitrided ZrO2 as gate dielectric material.
Simulations and Results 51
eV. λ from Eqn. 3.3 is 0.5875. Fig. 3.17 shows error both models. Once again our
model shows less error. Maximum error from Li’s model is 2.5% and from our model
is 1.3%.
Figure 3.16: C-V curves for Si3N4 as gate dielectric material. Here doping den-sity Na = 3.7× 1017 cm−3, EOT = 1.56 nm.
Maximum error in our proposed model in these examples is 1.3%. In most of the gate
voltage region error is near 0%. This proves the validity of improved compact model.
Constant λ value keeps the slope of C-V characteristics inadequate to real result. Vari-
ation in φb and Na,d have to be considered for accurate modeling of C-V curves. In
accumulation region our curve is not well matched. This is because in weak accumu-
lation region capacitance Cg is exponentially dependent on surface potential φs. Com-
pact model by Li et al. cannot model C-V in this region via general procedure. As
we took full algorithm of Li et al. as improved compact model except value of λ, it is
customary that we cannot match C-V in weak accumulation region. But our result is
better in strong accumulation region. Li et al. neglects the slope of C-V in this region.
For inversion region our model is better as well agreed with experimental data in all
regions. Here our proposed improved compact model outperforms the model of Li et
al. [11].
3.4 Validity of Improved Compact Model 52
Figure 3.17: Error curve for Si3N4 as gate dielectric material.
3.4.2 Comparison of C-V Characteristics for Electrons
Four C-V curves are taken to evaluate the accuracy of our model and Li et al.’s model
for electrons (n-MOS inversion and p-MOS accumulation). For each case two more C-V
curves are developed. One from model of Ref. [11] taking λ=0.61 and another from our
improved compact model determining λ from (3.7).
Fig. 3.18 shows experimental and simulated C-V for HfO2 dielectric material [32]. We
have used Nd = 2 × 1018 cm−3, EOT = 1.87 nm and φb = 1.5 eV. VFB and Nd are
calculated from the experimental C-V curve. We have VFB = 0.35 V. λ from Eqn. 3.7 is
0.56. Here our model shows less error in strong accumulation region. Maximum error
from model of Li et al. is 2.78% and from our model is 0.94% at Vg = 1.4 V. It is shown
in Fig. 3.19. About 1.4% error is suppressed in our model.
Fig. 3.20 shows another C-V for HfO2 dielectric material [33]. Here value of the pa-
rameters are Nd = 5 × 1017 cm−3, EOT = 1.94 nm and φb = 1.5 eV. VFB and Nd are
calculated from the experimental C-V curve. VFB = 0.90 V is used. From Eqn. 3.7 λ is
0.57. Again our model has less error in strong accumulation region. Maximum error
Simulations and Results 53
Figure 3.18: C-V curves for HfO2 as gate dielectric material. Here doping den-sity Nd = 2× 1018 cm−3, EOT = 1.87 nm.
Figure 3.19: Error curve for HfO2 as gate dielectric material.
3.4 Validity of Improved Compact Model 54
from Li et al.’s model is 2.78% and from our model is 0.94% at Vg = 1.4 V. It is shown in
3.21.
Figure 3.20: C-V curves for HfO2 as gate dielectric material. Here doping den-sity Nd = 5× 1017 cm−3, EOT = 1.94 nm.
Fig. 3.22 shows C-V for Y-O-Si dielectric material [29]. Parameter values are Nd =
5× 1015 cm−3, EOT = 1.17 nm and φb = 2.0 eV. VFB and Nd are calculated in the same
way as above. VFB = -1.63 V is used. From Eqn. 3.7 λ is 0.623. Our model has less error
than the model of Li et al. Maximum error from Li et al.’s model is 2.78% and from our
model is 0.94% at Vg = 1.4 V. Fig. 3.23 shows this result.
Fig. 3.24 shows C-V for Si3N4 dielectric material [31]. Parameter values are Nd =
3.7 × 1017 cm−3, EOT = 1.56 nm and φb = 2.0 eV. 3.7 gives λ to be 0.593. Once again
our model has less error than model of Li et al. Maximum error from model of [11] is
2.78% and from our model is 0.94% at Vg = 1.4 V. Fig. 3.25 shows this result.
Explanation for C-V curves in positive gate voltage region is same as that of negative
gate voltage region. Model of Li et al. underestimates the capacitance. It assumes
that there is a small interfacial layer of SiO2 between Si and gate oxide. But in case of
pure high-k material this assumption is not valid. We should take real barrier height φb.
Simulations and Results 55
Figure 3.21: Error curve for HfO2 as gate dielectric material.
Figure 3.22: C-V curves for YOSi as gate dielectric material. Here doping den-sity Nd = 5× 1015 cm−3, EOT = 1.17 nm.
3.4 Validity of Improved Compact Model 56
Figure 3.23: Error curve for YOSi as gate dielectric material.
Figure 3.24: C-V curves for Si3N4 as gate dielectric material. Here doping den-sity Nd = 3.7× 1017 cm−3, EOT = 1.56 nm.
Simulations and Results 57
Figure 3.25: Error curve for Si3N4 as gate dielectric material.
Again doping concentration Na,d must also be considered for accurate modeling of C-V.
Chapter 4
Conclusion
An improved compact model is developed to simulate C-V curves with high-k gate di-
electrics. It is based on previously published compact model. The exponent over oxide
field of the 2/3 power law relationship (E1 ∝ F2/3ox ) is supposed to vary with dielectric
material properties and doping density of the bulk. Comparison of C-V curves ob-
tained from both the models with experimental one shows validity of improved com-
pact model.
4.1 Summary
Compact model is necessary in day to day life for accurately simulating C-V curves.
MOSFETs are now most popular electronic device in silicon chip technologies. They
are popular due to their low power consumption and less power-delay product than
bipolar transistors. But capacitance play a vital role in determining performance of a
MOSFET. For this reason many simulators are developed to obtain accurate C-V char-
acteristics. Self-consistent simulators can simulate C-V curves with high accuracy but
with the penalty of taking huge time. Compact models are developed to shrink this
time. But compact models have their own limitations. Previously published compact
model can simulate C-V curves only if there is SiO2 in gate oxide or there is a small
Conclusion 59
interfacial layer of SiO2 between gate dielectric and Si body.
Trend of modern MOSFET devices is to move from SiO2 to high-k gate oxide. This
improves leakage current and gate capacitance value in strong accumulation region.
So we need a compact model that can simulate C-V MOS devices with high-k gate
dielectrics correctly. The model presented in this thesis is capable of generating C-V
curves with pure high-k dielectrics. One dielectric has different properties than the
other. So it is necessary to consider different properties of these dielectric materials.
One such property is barrier height. In previously published compact model high-k
materials were simulated with barrier height value of SiO2. This certainly does not
give accurate result in all cases. On the other hand they negletted substrate doping
densities. But C-V curves strongly depends on doping concentration in weak to mod-
erate inversion and accumulation. So complete C-V curve needs this two effects to be
taken into account. Our model incorporates both this effects and exponent over ox-
ide field to calculate eigenenrgy is expressed as a function of these two. Two different
equations are given to determine exponent for holes and electrons.
Finally eight C-V curves are taken to prove the validity of improved compact model.
All the cases showed better result than general compact model. Error is suppressed in
good amount for both holes and electrons. Error minimization is more for holes than
electrons.
4.2 Probable Future Works
Our proposed improved compact model is valid for pure single layer high-k or multi-
layered high-k dielectrics. If one or more layers are of low-k, then our model fails to
simulate C-V curves accurately. Reason behind this is the limitation of our simulator
used to calculate exponent value. This simulator can handle only one layer of dielec-
tric. It is possible to have more simulation results with more than one layer of dielectric
with other simulators. These results can easily combined with the present structure of
4.2 Probable Future Works 60
this model, and via the final model any number of layered dielectric C-V can be simu-
lated.
Also our model fails to give accurate result in case of SiO2 interfacial layer presence. If
we can know the thickness of interfacial layer then special simulators can be used to
find exponent value for total dielectric combination. With this interfacial layered MOS-
FET C-Vs can also be simulated.
Recently MOSFETs are entering in nanometer regime. So there are chances that oxide
energy structure will not remain as smooth as in theory. These special conditions can
also be incorporated in our compact model by evaluating exponent value. In all the
cases only parameter that has to be changed is the exponent. Values of it can be de-
termined and expressed as a function of certain parameters. With this function and
existing compact model of ours, any type of gate dielectrics can be simulated.
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