Backprojection Project Update January 2002

1

Backprojection Project Update January 2002

Haiqian Yu

Miriam Leeser

Srdjan Coric

2

Outline

• Review of backprojection algorithm

• Hardware considerations

• Wildstar implementation and some results

• Comparison of Wildstar and Firebird

• Current work

• Issues and some proposals

• Future work

3

Backprojection

• Square pixel assumed

• Incremental algorithm

• Use lookup tables

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Sinogram data address

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Sinogram data retrieval

Linearinterpolation

Dataaccumulation

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Sinogram data prefetch

Data Flow Block Diagram

5

Hardware ImplementationData Flow

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Parameters selected in our hardware implementation

• Fixed point data is used

• Quantization bits for the sinogram: 9 bits

• Interpolation factor bits: 3 bits

• Restored backprojection data width: 25 bits

• Lookup table width: – table1: 15 bits

– table2: 16 bits

– table3: 17 bits

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Simple Architecture-One Projection Processing

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Advanced Architecture-Four Projection Parallel Processing

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9

Some Results

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Performance Results on Wildstar: Software vs. FPGA Hardware

A Software - Floating point - 450 MHz Pentium : ~ 240 s

B Software - Floating point - 1 GHz Dual Pentium : ~ 94 s

C Software - Fixed point - 450 MHz Pentium : ~ 50 s

D Software - Fixed point - 1 GHz Dual Pentium : ~ 28 s

E Hardware - 50 MHz : ~ 5.4 s

F Hardware (Advanced Architecture) - 50 MHz : ~ 1.3 s

0

50

100

150

200

250

A B C D E F

Parameters: 1024 projections

1024 samples per projection

512*512 pixels image

9-bit sinogram data

3-bit interpolation factor

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Board Parameters Compared

WildStar FireBird 3 Xilinx® VIRTEX™ 1000 FPGAs with

3 million system gates (Processing can’t bedistributed to different chips, only one chipis used.)

1 VirtexTM E FPGA Processing Element -XCV2000E with 2 million gates

Processing clock rates up to 100MHz Processing clock rates up to 150MHz

1.6 GB/s I/O bandwidth 4.2 GB/s I/O bandwidth

6.4 GB/s memory bandwidth (1.3GB/s isused)

6.6 GB/s memory bandwidth

40MB of 100MHz Synchronous ZBT SRAM(We only use part of it)

30MB of 150MHz Synchronous ZBT SRAM

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Logical Block Diagram of WildStar

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Backprojection on Wildstar• PE1 is the only processor element used

• Not all the memory is used to store the data – Left & Right PE1 Mezzanine Mem0 are used to store sinogram

data, the input data for backprojection

– Left & Right PE1 Local memory banks are used to store the results

• The bottleneck is PE1’s block RAM (on chip memory) size.– XCV1000 has 32 block RAMs, each has 4096 bits,

totaling 131,072 bits

– We used 73,728 bits in our implementation, the maximum bits we can use

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Logical Block Diagram of FireBird

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Backprojection on FireBird

• XCV2000E has 160 block RAMs with totally 655,360 bits, 5 times that of XCV1000.

• FireBird has 5 on board memory banks, 4 that are 64 bits wide, one that is 32 bits wide.

• The memory interface is different from WildStar.

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Current Work• Firebird configuration:

– parameters setting for simulation scripts– synthesis settings– C environment settings

• Getting familiar with FireBird memory interface.

• Implementing simple architecture of parallel-beam backprojection.

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Issues• Because of increased CLBs on Virtex2000E:

we can increase parallelism in backprojection processing by a factor of 5 or 20 projection parallelism.

• On chip block RAM is no longer the bottleneck

• Memory bandwidth to off-chip memory is the new bottleneck:– To process 20 projection at one time, we need to load 40

projections (for interpolation), or 2*4*5*9=360 bits in one clock cycle

– Firebird has 4*64-bit memories, we need 6 for 20 projections

– We should be able to achieve 12 projections in parallel

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Imagerows

Projections

Imagecolumns

Data dependency for backprojection processing

Parallelism Improvement

Imagerows

ProjectionsImage

columns

Current parallelism we used in WildStar

Desired parallelism we would implement in FireBird

Imagerows

ProjectionsImage

columns

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Example of Using four memory banks to increase the speed

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

MemoryBank Even64-bit width

9 Bits

9 Bits

9 Bits

9 Bits

MemoryBank Odd

64-bit width

9 Bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

7*9=63BitsMaximum data width provided

by memory banksEvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

...

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

MemoryBank Even64-bit width

9 Bits

9 Bits

9 Bits

9 Bits

MemoryBank Odd

64-bit width

9 Bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

7*9=63BitsMaximum data width provided

by memory banksEvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

...

9 Bits

9 Bits

9 Bits

9 Bits

9 Bits

9 Bits

Processing

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

MemoryBank Even64-bit width

9 Bits

9 Bits

9 Bits

9 Bits

9 Bits

MemoryBank Odd

64-bit width

9 Bits

9 Bits

9 Bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

EvenRAM

512*9 bits

OddRAM

512*9 bits

36Bits

36Bits

Processing

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More memory issues

• If we use four 64-bit width memory banks to store the sinogram data, we have only one 32-bit memory bank for storing the result

• Since the j-th step results depends on (j-1)-th results, we will have to use read-modify-write method to store the final data. This will decrease the overall speed.

• Possible solution: – fewer projections in parallel

– use more memory to store results

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Alternatives

• An alternative is to use 2*512 cycles to double the number of projection processed. – However, we need to make sure processing all the data needs more

than 1024 clock cycle.

– That will introduce extra delay for the first time processing, for the consequent processing, data is pre-fetched while processing the current projection.

• We can also modify the hardware structure to see if there are some other ways to explore parallelism.

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Future Work

• Implement parallel backprojection on FireBird– With bridge to host– Without bridge to host

• Investigate parallelism to optimize performance