90nm Devices and Circuits for mm- Wave applications Babak Heydari, Mounir Bohsali, Ehsan Adabi Prof. Niknejad and Brodersen
90nm Devices and Circuits for mm-Wave applications
Babak Heydari, Mounir Bohsali, Ehsan Adabi
Prof. Niknejad and Brodersen
First 90nm Test Chip
First chip Measured PerformancesCommon-Source (f = 100, W/L=100um/90nm)
7.746446.410.9100
8.336436.420.7100
8.256156.120.9100
7.727627.610.7100
6.510910.910.5100
2.4141.410.3100
MSG(dB)
Ids/w (uA/um)
Ids (mA)
Vds(V)
Vgs(V)
F
Measured PerformanceMinimum Noise Figure (Thanks to VTT)
Fmin - W/L=100um/90nm, 100 fingers
00.5
11.5
22.5
33.5
4
40 50 60 70 80
Freq (GHz)
NFm
in (d
B)
Fmin - W/L=80um/90nm, 80 fingers
0
0.5
1
1.5
2
2.5
3
3.5
4
40 50 60 70 80
Freq (GHz)
NFm
in (d
B)
Fmin - W/L=400um/90nm, 400 fingers
0
1
2
3
4
5
6
40 50 60 70 80
Freq (GHz)
NFm
in (d
B)
NFmin at 60GHz ~ 2.5dB
400 fingers device exhibits lower NF performance
Modeling and Second Test Chip
Small Signal Modeling
PortP2Num =2
PortP1Num =1
CC1C=74.85 fF
CC3C=24.03 fF
RR3R=90 Ohm
CC4C=41.54 fF
LL3
R=L=4.55 pH
LL2
R=L=6 pH
RR2R=1.27 Ohm
RR8R=408 m Ohm
LL1
R=L=9.594 pH
RR1R=1.43
CC6C=51.18 fF
RR4R=1.46
RR5R=30.92 Ohm
RR6R=47.21 Ohm
RR7R=38.21 Ohm
VCCSSRC3G=105.6 m S
CC5C=40.84 fF
• Using series inductances and resistances and three resistor substrate.
• Implementing a Matlab script to extract core transistor parameters from low frequency measurements.
• Using IC-CAP to extract parasitic and optimize
• S-Parameters where fitted up to 40Ghz and the model is frequency independent.
100u/90nm common source NMOS, Small Signal Model
Small Signal Modeling (II)
Magnitude of S-ParametersMeas/Sim up to 40Ghz
Phase of S-ParametersMeas/Sim up to 40Ghz
Modeling and Sensitivity Analysis
The effect of core parameters(Maximum stable gain and maximum unilateral gain)
Performance of the transistor is almost inversely proportional to the gate-drain capacitor. Cgs does not have a great impact on the fmax.
Effect of gm on fmax Effect of cgd on fmax
Modeling and Sensitivity Analysis(II)The effect of parasitics: ( Gate, drain, substrate and body resistances)
• Gate resistance is very important! ( Minimize as much as you can)• Substrate and source resistances effects are small.
Effect of Rgate Effect of Rdrain
Effect of Rsource Effect of Rsub
Second Test chip, ST-90nm– Layout improvements:
• Reduced taper size for transistors and capacitors• Increased number of poly contacts in transistor tapers• Increased number of vias in transistor tapers• Added bridge between ground planes for transmission lines and
transistorsVersion 1
draingate
large taper
Version 2 bridges
draingate
small taper
gate drain
source
Substrate taps
gnd
Gate vias: 1 column of poly contacts2 columns of via_x1 column of via_n
Gate vias: 3column of poly contacts3 columns of via_x2 column of via_n
Rgate_sim,model = 1.4 ohms Rgate_sim = 0.8 ohms
Version 1 Version 2100 finger common-source
Round Table Structures
Interdigitaded Cascode10u/90nm Building block to reduce parasitic resistances *
60u/90nm common source using the Building block
* This structure is widely used by Philips [IEDM 2004]
New Structures in Test Chip IITL Source degenerated NMOS for modeling purpose for applications that source is not grounded.
• Common-Gate NMOS.
• PMOS Devices
• Different variations of MOS varactors.
• LC Tanks
Long Channel devices for NQS modeling purposes
60GHz Preliminary Amplifier Design
Small Signal Modeling
PortP2Num =2
PortP1Num =1
CC1C=74.85 fF
CC3C=24.03 fF
RR3R=90 Ohm
CC4C=41.54 fF
LL3
R=L=4.55 pH
LL2
R=L=6 pH
RR2R=1.27 Ohm
RR8R=408 m Ohm
LL1
R=L=9.594 pH
RR1R=1.43
CC6C=51.18 fF
RR4R=1.46
RR5R=30.92 Ohm
RR6R=47.21 Ohm
RR7R=38.21 Ohm
VCCSSRC3G=105.6 m S
CC5C=40.84 fF
• Using series inductances and resistances and three resistor substrate.
• Implementing a Matlab script to extract core transistor parameters from low frequency measurements.
• Using IC-CAP to extract parasitic and optimize
• S-Parameters where fitted up to 40Ghz and the model is frequency independent.
100u/90nm common source NMOS, Small Signal Model
Transmission Line Model
Momentum Model ADS CPW
Three Stage 90nm CMOS LNA
PortP2Num=2Port
P1Num=1
TLINTL1
MM30_NMOSMOSFET1
TLINTL7
TLINTL9
TLINTL11
TLINTL18
TLINTL20
TLINTL17
MM30_NMOSMOSFET3
TLINTL16
TLINTL6TLIN
TL15
MM30_NMOSMOSFET2
TLINTL14
PortP2Num =2
PortP1Num =1
CC1C=74.85 fF
CC3C=24.03 fF
RR3R=90 Ohm
CC4C=41.54 fF
LL3
R=L=4.55 pH
LL2
R=L=6 pH
RR2R=1.27 Ohm
RR8R=408 m Ohm
LL1
R=L=9.594 pH
RR1R=1.43
CC6C=51.18 fF
RR4R=1.46
RR5R=30.92 Ohm
RR6R=47.21 Ohm
RR7R=38.21 Ohm
VCCSSRC3G=105.6 m S
CC5C=40.84 fF
LNA Measurement BasedSimulation Results
m3freq=m3=14.117
59.00GHz
10 20 30 40 50 60 700 80
-60
-50
-40
-30
-20
-10
0
10
-70
20
freq, GHz
dB(S
(2,1
))
m3
m3freq=m3=14.135
58.80GHz
m2freq=m2=11.292
62.80GHzm4freq=m4=11.309
55.40GHz
56 57 58 59 60 61 62 63 6455 65
10
11
12
13
14
9
15
freq, GHz
dB(S
(2,1
))
m3
m2m4
m1freq=m1=5.508
60.40GHz
56 57 58 59 60 61 62 63 6455 65
5.5
6.0
6.5
7.0
5.0
7.5
freq, GHz
nf(2
)
m1
indep(S_StabCircle1) (0.000 to 51.000)
S_S
tabC
ircle
1
indep(L_StabCircle1) (0.000 to 51.000)
L_S
tabC
ircle
1
10 20 30 40 50 60 700 80
1.2
1.4
1.6
1.8
2.0
1.0
2.2
freq, GHz
Mu1
Power: 84mWVdd: 1VGain = 14 dBNF ~ 6 dBS11=-8db (60GHz)
60 GHz Preliminary Power Amplifier
3-stage amp
3-stage amp
3-stage amp
3-stage amp
4-wayWilkinsonPower Divider
4-wayWilkinsonPower Combiner
2 dB insertion loss(63% efficiency)
13 dB power gain
Wilkinson Power combiner/divider simulation results
CPWSUBCPWSub1
Rough=0 umTanD=0.077T=0.85 umCond=5.7e7Mur=1Er=8.55H=6.57 um
CPWSub
RR1R=50 Ohm
RR2R=50 Ohm
RR3R=50 Ohm
RR4R=50 Ohm
CPWCPW4
L=658 umG=0.55 umW=10 umSubst="CPWSub1"
CPWCPW1
L=658 umG=0.55 umW=10 umSubst="CPWSub1"
CPWCPW2
L=658 umG=0.55 umW=10 umSubst="CPWSub1"
CPWCPW3
L=658 umG=0.55 umW=10 umSubst="CPWSub1"
Zo = 22.5Ω
60 GHz 3-Stage Amplifier
PortP1Num=1
RR6R=47.21 Ohm
RR5R=30.92 Ohm
CC4C=41.54 f F
RR8R=408 mOhm
LL3
R=L=4.55 pH
CC3C=24.03 f F
PortP2Num=2
CC1C=74.85 f F
RR3R=90 Ohm
LL2
R=L=6 pH
RR2R=1.27 Ohm
LL1
R=L=9.594 pH
RR1R=1.43
CC6C=51.18 f F
RR4R=1.46
RR7R=38.21 Ohm
VCCSSRC3G=105.6 mS
CC5C=40.84 f F
BSIM3v3 model
extrinsic layout parasitics
50Ω match High pass output match
(Gate bias not shown)
Preliminary large-signal modelsmall-signal model
VddVdd Vdd
CPWSCCPW18
L=39.9 umG=3.6 umW=10 umSubst="CPWSub1"
CPWCPW11
L=16.4 umG=3.6 umW=10 umSubst="CPWSub1"
CPWCPW12
L=91.6 umG=3.6 umW=10 umSubst="CPWSub1"
CPWOCCPW7
L=470.2 umG=3.6 umW=10 umSubst="CPWSub1"
CPWCPW8
L=37.7 umG=3.6 umW=10 umSubst="CPWSub1"
CPWCPW9
L=83.2 umG=3.6 umW=10 umSubst="CPWSub1"
CPWSCCPW19
L=19.4 umG=3.6 umW=10 umSubst="CPWSub1"
CPWCPW14
L=24.8 umG=3.6 umW=10 umSubst="CPWSub1"
CPWCPW15
L=249.7 umG=3.6 umW=10 umSubst="CPWSub1"
CPWOCCPW16
L=519.5 umG=3.6 umW=10 umSubst="CPWSub1"
TLINTL3
F=60 GHzE=90Z=50.0 Ohm
TLINTL2
F=60 GHzE=90Z=50.0 Ohm
TLINTL1
F=60 GHzE=90Z=50.0 Ohm
PortP2Num=2
PortP1Num=1
CC3C=1.0 pF
CC2C=1.0 pF
EE_MOS1EEMOS3
Temp=Model=EEMOSM1
CC1C=1.0 pF
EE_MOS1EEMOS1
Temp=Model=EEMOSM1
EE_MOS1EEMOS2
Temp=Model=EEMOSM1
Measurement Based Simulation Results of 3-Stage PA
S21 at 60GHz = 13dBS11 at 60GHz = -10dBOutput Power = 17 mW (Vdd = 1V)Power Consumption = 90mWEfficiency = 19%
Future Work
• More accurate Large Signal Modeling• More realistic design by using real
coupling caps and bias network• Non-linearity analysis of PA and LNA• Investigating other structures in designs
using cascode and common gate devices
Acknowledgements
• BWRC Member Companies• STMicroelectronics and VTT• DARPA TEAM Program• Professor Niknejad and senior Members of
60GHz Project: Sohrab and Chinh