BAB17 - The Additional Discrete Library

8/9/2019 BAB17 - The Additional Discrete Library

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Introduction to Simulink with Engineering Applications 17−1Copyright © Orchard Publications

Chapter 17The Additional Discrete Library

his chapter is an introduction to the Additional Discrete Library. This is the sixteenthlibrary in the Simulink group of libraries and contains the blocks shown below. We willdescribe the function of each block included in this library and we will perform simulation

examples to illustrate their application.


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Chapter 17 The Additional Discrete Library

17−2 Introduction to Simulink with Engineering Applications Copyright © Orchard Publications

17.1 The Transfer Fcn Direct Form II Block

The Transfer Fcn Direct Form II block implements a Direct Form II realization of the transferfunction specified by the Numerator coefficients and the Denominator coefficients without the

leading* coefficient in the Denominator.

Example 17.1

The model of Figure 17.1 implements the discrete−time function

(17.1)

Figure 17.1. Direct Form−II of a second-order digital filterIn Figure 17.1, the Sample time for the Sine Wave block is specified as 0.1. The for the

Transfer Fcn Direct Form II block is specified as , and the is

specified as . The leading coefficient 1 in the denominator is excluded. The

input and output waveforms are shown in Figure 17.2.

* By lead we mean that the leading coefficient 1 in the denominator which has the form .1 + z 1– + z 2–

H z( ) 0.5276 1.5828z

1–

– 1.5828z

2–

+1 1.7600z

1–– 1.1829z

2–+

----------------------------------------------------------------------------=

num z( )

0.5276 1.5828 1.5828–[ ] den z( )

1.7600 1.1829–[ ]


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The Transfer Fcn Direct Form II Time Varying Block

Figure 17.2. Input and output waveforms for the model of Figure 17.1

17.2 The Transfer Fcn Direct Form II Time Varying Block

The Transfer Fcn Direct Form II Time Varying block implements a Direct Form II realizationof a specified transfer function. Essentially, this block performs the same function as that of theTransfer Fcn Direct Form II block which is described in the previous section, except that thenumerator and denominator coefficients of the discrete−time transfer function are specified exter-

nally by two inputs Num and Den.

Example 17.2

The model of Figure 17.3 is essentially the same as that of Figure 17.1 and thus the input and out-put waveforms of Figure 17.4 are the same as those of Figure 17.2.


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Figure 17.3. Model for Example 17.3


17.3 The Fixed−Point State−Space Block

The Fixed−Point State−Space block implements the system described by

(17.2)

where:

is a matrix with dimensions , , is a matrix with dimensions

, , is a matrix with dimensions , ,

x n 1+[ ] Ax n[ ] Bu n[ ]+=

y n[ ] Cx n[ ] Du n[ ]+=

A n n× n number of states= B

n m× m number of inputs= C r n× r number of outputs= D


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The Fixed−Point State−Space Block

is a matrix with dimensions , , , and

.

Example 17.3

The matrix form of a 3−input 2−output 3−state discrete−time system is specified as

(17.3)

In the model of Figure 17.5 we enter the values of matrices A, B, C, and D in the Fixed−PointState−Space block parameters dialog box, and we specify initial condition 0. The input vector is asshown and when the simulation command is given the input and output waveforms are as shownin Figure 17.6.


r m× x state, an n 1× vector = u input, an m 1 vector ×=

y output, an r 1 vector ×=

x1 n 1+[ ]

x2 n 1+[ ]

x3 n 1+[ ]

0.25 0 0

0 0.5 0

0 0.25– 0.75–

x1 n[ ]

x2 n[ ]

x3 n[ ]

0 1 0

0 0 1

1 0 1

u1 n[ ]

u2 n[ ]

u3 n[ ]

⋅+⋅=

A B

y1 n[ ]y2 n[ ]

1 0 10 1 0

x1 n[ ]

x2 n[ ]

x3 n[ ]

0 1 00 0 1

u1 n[ ]

u2 n[ ]

u3 n[ ]

⋅+⋅=

C D

⎧ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎩ ⎧ ⎪ ⎨ ⎪ ⎩

⎧ ⎪ ⎨ ⎪ ⎩ ⎧ ⎪ ⎨ ⎪ ⎩


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17.4 The Unit Delay External IC Block

The Unit Delay External IC (Initial Condition) block delays its input by one sample period. This

block is equivalent to the discrete−time operator. The block accepts one input and generates

one output, both of which can be scalar or vector. If the input is a vector, all elements of the vec-tor are delayed by the same sample period. The block's output for the first sample period is equal

to the signal IC. The input u and initial condition IC data types must be the same.

Example 17.4

In the model of Figure 17.7, the Pulse Generator block is specified for a period 2 sec. All otherparameters are in their default state. The input and output waveforms are shown in Figure 17.8.


z 1–


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The Unit Delay Resettable Block


17.5 The Unit Delay Resettable Block

The Unit Delay Resettable block delays a signal one sample period. If the reset input signal isfalse, the block outputs the input signal delayed by one time step. If the reset signal is true, theblock resets the current state to the initial condition, specified by the Initial condition parameter,and outputs that state delayed by one time step.

Example 17.5

In the model of Figure 17.9, the Pulse Generator 1 block is specified for a period 2 sec. and thePulse Generator 2 block is set for a period 4 sec. All other parameters are in their default state.The input and output waveforms are shown in Figure 17.10.



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17.6 The Unit Delay Resettable External IC Block

The Unit Delay Resettable External IC block delays a signal one sample period. The block canbe reset by the external reset signal R. The block has two input ports, one for the input signal uand the other for the reset signal R. When the reset signal is false, the block outputs the input sig-nal delayed by one time step. When the reset signal is true, the block resets the current state to

the initial condition given by the signal IC and outputs that state delayed by one time step.

Example 17.6

In the model of Figure 17.11, the Pulse Generator 1 block is set for a period 2 sec. and the PulseGenerator 2 block is set for a period 4 sec. All other parameters are in their default state. Theinput and output waveforms are shown in Figure 17.12.


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The Unit Delay Enabled Block



17.7 The Unit Delay Enabled Block

The Unit Delay Enabled block delays a signal by one sample period when the external enable sig-nal E is on. When the enable signal E is off, the block is disabled. The block holds the currentstate at the same value and outputs that value. The enable signal is on when E is not 0, and is off when E is 0.


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Example 17.7

Figure 17.13 contains two models where in the upper model the Unit Delay Enabled 1 block isdisabled and thus its output is zero. In the lower model the Unit Delay Enabled 2 block is enabledand causes a delay in the input signal before being propagated to the Discrete Time IntegratorForward Euler 2 block. The inputs and outputs are shown in Figure 17.14.

Figure 17.13. Models for Example 17.7

Figure 17.14. Input and Output waveforms for the models of Figure 17.7


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The Unit Delay Enabled Resettable Block

17.8 The Unit Delay Enabled Resettable Block

The Unit Delay Enabled Resettable block delays a signal one sample period, if the externalenable signal is on. This block combines the features of the Unit Delay Enabled and Unit DelayResettable blocks. When the enable signal E is on and the reset signal R is false, the block outputsthe input signal delayed by one sample period. When the enable signal E is on and the reset signalR is true, the block resets the current state to the initial condition, specified by the Initial condi-tion parameter, and outputs that state delayed by one sample period. When the enable signal isoff, the block is disabled, and the state and output do not change except for resets. The enable sig-nal is on when E is not 0, and off when E is 0.

Example 17.8

In the model of Figure 17.15, the Pulse Generator 1 block is specified for a period 2 sec., the PulseGenerator 2 block is specified for a period 3 sec., and the Pulse Generator 3 block is specified for aperiod 4 sec. All other parameters are in their default state. The input and output waveforms areshown in Figure 17.16.



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17.9 The Unit Delay Enabled External IC Block

The Unit Delay Enabled External IC block delays a signal by one sample period when the enable

signal E is on. When the enable is off, the block holds the current state at the same value and out-puts that value. The enable E is on when E is not 0, and off when E is 0. The initial condition of this block is specified by the input signal IC. Essentially, this block is the same as the Unit DelayEnabled block which we described in the previous section of this chapter except that the initialcondition is specified by an external block.

Example 17.9

In the model of Figure 17.17, the Constant 1 block enables the Unit Delay Enabled External ICblock while the Constant 2 block is set to 1 to specify the initial condition. The input and outputwaveforms are shown in Figure 17.18.


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The Unit Delay Enabled Resettable External IC Block



17.10 The Unit Delay Enabled Resettable External IC Block

The Unit Delay Enabled Resettable External IC block is a combination of the functions per-formed by the Unit Delay Enabled, Unit Delay External IC, and Unit Delay Resettable blocks.The block can reset its state based on an external reset signal R. When the enable signal E is onand the reset signal R is false, the block outputs the input signal delayed by one sample period.When the enable signal E is on and the reset signal R is true, the block resets the current state tothe initial condition given by the signal IC, and outputs that state delayed by one sample period.When the enable signal is off, the block is disabled, and the state and output do not changeexcept for resets. The enable signal is on when E is not 0, and off when E is 0.


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Example 17.10

In the model of Figure 17.19, the Pulse Generator 1 block is specified for a period 2 sec., the PulseGenerator 2 block is specified for a period 3 sec., and the Pulse Generator 3 block is specified for aperiod 4 sec. All other parameters are in their default state. The input and output waveforms areshown in Figure 17.20.




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The Unit Delay With Preview Resettable Block

17.11 The Unit Delay With Preview Resettable Block

The Unit Delay With Preview Resettable block can reset its state based on an external reset sig-nal R. The block has two output ports. When the reset R is false, the upper port outputs the signaland the lower port outputs the signal delayed by one sample period. When the reset R is true, theblock resets the current state to the initial condition given by the Initial condition parameter. Theblock outputs that state delayed by one sample time through the lower output port, and outputsthe state without a delay through the upper output port.

Example 17.11

In the model of Figure 17.21, the Pulse Generator 1 block is specified for a period 2 sec. and thePulse Generator 2 block is specified for a period 4 sec. All other parameters are in their defaultstate. The input and output waveforms are shown in Figure 17.22.



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Figure 17.22. Waveforms for the model of Figure 17.21

17.12 The Unit Delay With Preview Resettable External RV Block

The Unit Delay With Preview Resettable External RV block has three input and two outputports. This block can reset its state based on the state of the an external input reset signal R.When the external reset R is false, the upper port outputs the signal and the lower port outputsthe signal delayed by one sample period. When the external reset R is true, the upper output sig-nal is forced to equal the external input reset signal RV. The lower output signal is not affecteduntil one time step later, at which time it is equal to the external reset signal RV at the previoustime step. The block uses the internal Initial condition only when the model starts or when a par-ent enabled subsystem is used. The internal Initial condition only affects the lower output signal.

Example 17.12

In the model of Figure 17.23, the Pulse Generator 1, 2, and 3 blocks are specified for the periodsshown on the model. All other parameters are in their default state. The input and output wave-forms are shown in Figure 17.24.


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The Unit Delay With Preview Enabled Block



17.13 The Unit Delay With Preview Enabled Block

The Unit Delay With Preview Enabled block has two input and two output ports. When theexternal input enable signal E is on, the upper port outputs the signal and the lower port outputs


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The Unit Delay With Preview Enabled Resettable Block

17.14 The Unit Delay With Preview Enabled Resettable Block

The Unit Delay With Preview Enabled Resettable block has three inputs and two outputs. Thisblock can reset its state based on an external input reset signal R. When the external enable sig-nal E is on and the reset R is false, the upper port outputs the signal and the lower port outputsthe signal delayed by one sample period. When the enable input signal E is on and the reset R istrue, the block resets the current state to the initial condition given by the Initial conditionparameter. The block outputs that state delayed by one sample time through the lower output

port, and outputs the state without a delay through the upper output port. When the Enable sig-nal is off, the block is disabled, and the state and output values do not change, except for resets.The enable signal is on when E is not 0, and off when E is 0.

Example 17.14

In the model of Figure 17.27, the Pulse Generator 1, 2, and 3 blocks are specified for the periodshown on the model. All other parameters are in their default state. The input and output wave-forms are shown in Figure 17.28.



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17.15 The Unit Delay With Preview Enabled Resettable External RV Block

The Unit Delay With Preview Enabled Resettable External RV block has four inputs and twooutputs. This block can reset its state based on an external reset signal R. When the externalenable signal E is on and the reset R is false, the upper port outputs the signal and the lower portoutputs the signal delayed by one sample period.

When the enable signal E is on and the reset R is true, the upper output signal is forced to equalthe external input reset signal RV. The lower output signal is not affected until one time steplater, at which time it is equal to the external reset signal RV at the previous time step. The blockuses the internal Initial condition only when the model starts or when a parent enabled subsystemis used. The internal Initial condition only affects the lower output signal. When the Enable signal

is off, the block is disabled, and the state and output values do not change, except for resets. Theenable signal is on when E is not 0, and off when E is 0.


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The Unit Delay With Preview Enabled Resettable External RV Block

Example 17.15

In the model of Figure 17.29, the Pulse Generator 1, 2, and 3 blocks are set for the periods shownon the model. All other parameters are in their default state. The input and output waveforms areshown in Figure 17.30.




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17.16 Summary

• The Transfer Fcn Direct Form II block implements a Direct Form II realization of the trans-fer function specified by the Numerator coefficients and the Denominator coefficients withoutthe leading coefficient in the Denominator.

• The Transfer Fcn Direct Form II Time Varying block implements a Direct Form II realiza-tion of a specified transfer function. Essentially, this block performs the same function as thatof the Transfer Fcn Direct Form II block.

• The Fixed−Point State−Space block implements the system described by

• The Unit Delay External IC (Initial Condition) block delays its input by one sample period.

This block is equivalent to the discrete-time operator. The block accepts one input andgenerates one output, both of which can be scalar or vector. If the input is a vector, all ele-ments of the vector are delayed by the same sample period. The block's output for the firstsample period is equal to the signal IC. The input u and initial condition IC data types must bethe same.

• The Unit Delay Resettable block delays a signal one sample period. If the reset input signal isfalse, the block outputs the input signal delayed by one time step. If the reset signal is true, theblock resets the current state to the initial condition, specified by the Initial condition parame-ter, and outputs that state delayed by one time step.

• The Unit Delay Resettable External IC block delays a signal one sample period. The blockcan be reset by the external reset signal R. The block has two input ports, one for the input sig-nal u and the other for the reset signal R. When the reset signal is false, the block outputs theinput signal delayed by one time step. When the reset signal is true, the block resets the currentstate to the initial condition given by the signal IC and outputs that state delayed by one timestep.

• The Unit Delay Enabled block delays a signal by one sample period when the external enablesignal E is on. When the enable signal E is off, the block is disabled. The block holds the cur-rent state at the same value and outputs that value. The enable signal is on when E is not 0,

and is off when E is 0.

• The Unit Delay Enabled Resettable block delays a signal one sample period, if the externalenable signal is on. This block combines the features of the Unit Delay Enabled and Unit DelayResettable blocks.

• The Unit Delay Enabled External IC block delays a signal by one sample period when theenable signal E is on. When the enable is off, the block holds the current state at the same

x n 1+[ ] Ax n[ ] Bu n[ ]+=

y n[ ] Cx n[ ] Du n[ ]+=

z

1–


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reset R is true, the upper output signal is forced to equal the external input reset signal RV.The lower output signal is not affected until one time step later.

BAB17 - The Additional Discrete Library

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