B5_Fabula 1 PEM Qualification Requirements For Radiation Hardened Non- Hermetic Products Qualifiable for Space Flight Applications.

B5_Fabula 1

PEM Qualification Requirements

For Radiation Hardened Non-Hermetic Products Qualifiable for

Space Flight Applications

B5_Fabula 2

Plastic vs Hermetic

• Moisture Effects

• Weight Differences

• Shock & Vibration

• Outgassing Effects

• Package Qualifications

• Board Qualifications

• Assembly Roadmap

B5_Fabula 3

Moisture Effects

• All Xilinx PEMs are certified according to method JESD20 as Level 3 or better

• JESD20 certification includes three passes of solder simulation to allow for rework

• “POPCORN” is a myth after successful board assembly

• Space is actually a benign, dry environment for PEMs.

B5_Fabula 4

“POPCORN”

• “POPCORN” can only occur during the assembly process if industry standard rules are not followed

• “POPCORN” is caused by liberation of the steam formed during the rapid thermal excursions to 230°C seen in the solder reflow process

• “POPCORN” can only occur when adsorbed moisture is turned to steam faster than it can escape

• “POPCORN” does not occur in operation because temperatures and temperature ramp rates in operation are simply not high enough

B5_Fabula 5

Thermal Comparisontheta Ja

• PLCC84 28.4 °C/watt

• PQ240 12.3 °C/watt

• BGA432 10.7 °C/watt

• BGA560 10.2 °C/watt

• FG680 10.6 °C/watt

• FG900 13.5 °C/watt

• FG1156 13.4 °C/watt

• PG84 32.5 °C/watt

• PG175 21.9 °C/watt

• CB228 17.5 °C/watt

• CG56014.3 °C/watt

• no higher pin count ceramic packages are currently available from Xilinx

B5_Fabula 6

Weight Comparisons

• PLCC84 6.8gr

• PQ240 7.1gr

• BGA432 7.1gr

• BGA560 12.3gr

• FG680 10.6gr

• FG900 4.2gr

• FG1156 6.2gr

• PG84 7.5gr

• PG175 17.7gr

• CB228 17.6gr

• CG560 44.0gr

• no higher pin count ceramic packages are currently available from Xilinx

B5_Fabula 7

Launch Cost Comparisonbased on $10,000/lb to GEO

• CG560 $969.00

• BG560 $270.00

• FG900 $ 92.00

B5_Fabula 8

Shock & Vibration• The lower weight (mass) of PEMs gives them a distinct

advantage in passing board mount vibration tests

• PEMs are solid encapsulation, so ultrasonic cleaning and shock cannot affect bond wire integrity

• PEMs are qualified to all the shock, vibration and life tests utilizing the following standard test methods:– method 1010 T/C condition C

– method 1011 T/S condition C

– method 1005 Steady State Life

– method 2004 Lead Integrity

– method 2005 Vibration

B5_Fabula 9

Shock & Vibration (continued)

• PEMs offer the additional advantages of being manufactured on main stream, high volume commercial manufacturing lines with:– method 2011 bond strength, under SPC control with CpKs > 2.0,

on QML certified lines

– method 2019 die shear, under SPC control with CpKs > 2.0, on QML certified lines

– method 2012 radiography, with die attach coverage and bond sweep under SPC control, on QML certified lines

B5_Fabula 10

Outgassing Effects

• Data Source: NASA Web Sites

• Key Parameters– TML (total material loss)– CVCM (condensable volatiles recovered)

• NASA Specifications– A TML < 1.0% CVCM < 0.1%– B TML < 3.0% CVCM < 1.0%– X TML > 3.0% CVCM > 1.0%

B5_Fabula 11

Packaging Materials

• Injection Molded Packages– PLCC: Nitto MP 8000– PQFP: Nitto MP8000, Sumitomo 7304– PDIP/SO: Sumitomo 6300

• Ball Grid Packages– SBGA: Hysol FP4450, BT Laminate– BGA: Plaskon SMBT-1, BT Laminate

B5_Fabula 12

Outgas DataInjection Molded Packages

• PQFP, PDIP, SO, BGA– Sumitomo 6300 (PDIP, SO, PLCC)

• TML 0.27%

• CVCM 0.00%

– Sumitomo 7304 (PQFP, TQ/VQ)• TML 0.17%

• CVCM 0.00%

– Nitto 8100 (PQFP, PLCC)• TML 0.20%

• CVCM 0.01%

– BT Laminate (BGA substrate)• TML 0.78%

• CVCM 0.01%

– Plaskon SMTB-1 (BGA mold compound)• TML 0.28%

• CVCM 0.00%

B5_Fabula 13

Outgas DataEncapsulated Packages

• SBGA– BT Laminate (SBGA substrate)

• TML 0.78%

• CVCM 0.01%

– Hysol FP4450 (SBGA encapsulate)• TML 0.13%

• CVCM 0.00%

B5_Fabula 14

Circuit Board Outgasfor comparison

• FR-4 (various formulations)– TML 0.22 - 0.41% (range)

– CVCM 0.00 - 0.01% (range)

• Polyimide Laminate– TML 0.78%

– CVCM 0.01%

• Conclusion: The PC board materials have considerably more outgassing potential than the various materials used to fabricate PEMs.

B5_Fabula 15

Possible Indicators of Quality Manufacturing

• ISO9000 Conformance

• DSCC QML Certification

• PURE Approval

• Open Data Communications

• Reliability Monitoring Programs

• SPC Data Availability

• Applications Support

• SPC Control Programs

• TL9000 Certification

• Subcontractor Control Programs

• PCN Process

• Mask Revision Control

• Hardness Assurance Data

• SEU Upset Data

B5_Fabula 16

Typical Wafer Fab SPC Report

B5_Fabula 17

Parametric SPC Report

B5_Fabula 18

Metal Step Coverage of CMP Process

B5_Fabula 19

Metal Step Coverage of Reflow Process

B5_Fabula 20

Bond Integrity and Sweep

B5_Fabula 21

Bond Pull Data on Completed Assemblies

One device was pulled for wire bond pull test.

Minimum = 8.3Maximum = 13.6Average = 10.1Std. Dev. = 1.2

MODE : 1 = Break at Neck

Test # Force (g) Mode Test # Force (g) Mode

1 10.4 1 11 11.1 1

2 13.6 1 12 8.8 1

3 10.4 1 13 8.7 1

4 10.6 1 14 10.2 1

5 10.3 1 15 10.8 1

6 8.6 1 16 9.5 1

7 9.3 1 17 9.1 1

8 8.3 1 18 10.8 1

9 10.3 1 19 10.4 1

10 10 1 20 10.4 1

B5_Fabula 22

Plastic Qualification Tests

• Temperature Cycling (T/C)

• Moisture Resistance (PCT)

• Humidity Temperature Bias (85/85)

• Highly Accelerated Stress Test (HAST)

B5_Fabula 23

Temperature Cycling (T/C)

• Performed to 883 Method 1010

• Moisture Pre-stress to Level 3

• Full Solder Simulation per JESD20

• Condition C (-65°C/+150°C) for Injection Molded Packages (PQFP)

• Condition B for Ball Grid Packages

• Full Production Testing at end of Stress

• Package Decapsulation at End of Test to check for Die Cracking

B5_Fabula 24

Results of Temp Cycle TestingPQFP

Package Test Lots Devices Fails Hrs/Cyc Total Hrs/CycPQFP-100 Temp Cycle 4 304 0 1014 308332PQFP-160 Temp Cycle 6 338 0 991 334806PQFP-208 Temp Cycle 18 849 0 975 828033PQFP-240 Temp Cycle 13 618 0 1012 625526

Package Test Lots Devices Fails Hrs/Cyc Total Hrs/CycBGA-225,256 Temp Cycle 5 187 0 1020 190764BGA-352 Temp Cycle 6 162 0 1004 162638BGA-432 Temp Cycle 4 110 0 1007 110792BGA-560 Temp Cycle 14 387 0 932 360529BGA-728 Temp Cycle 1 26 0 1148 29847FG-256 Temp Cycle 5 165 0 1031 170062FG-456,556 Temp Cycle 6 108 0 1032 111478FG-676 Temp Cycle 1 22 0 1000 22000FG-680 Temp Cycle 1 34 0 1000 34000FG-900 Temp Cycle 3 74 0 1070 79190FG-1156 Temp Cycle 3 38 0 821 31188

49 1313 1302488

B5_Fabula 25

Pressure Pot Testing

• Performed in 121°C Steam at 2 atm

• Moisture Pre-stress to Level 3

• Full Solder Simulation per JESD20

• Minimum of 96 Hours

• Full Production Testing at end of Stress

• Package Decapsulation at End of Test to Examine for Corrosion

B5_Fabula 26

Moisture Resistance Testing

Package Test Lots Devices Fails Hrs/Cyc Total Hrs/CycPQFP-100 PCT 4 302 0 150 45264PQFP-160 PCT 2 89 0 96 8544PQFP-208 PCT 2 80 0 137 10920PQFP-240 PCT 9 399 0 105 42024

17 870 106752

Package Test Lots Devices Fails Hrs/Cyc Total Hrs/CycBGA-225,256 PCT 2 197 0 124 24384BGA-352 PCT 3 32 0 96 3072BGA-432 PCT 2 72 0 96 6912BGA-560 PCT 8 194 0 104 20208BGA-728 PCT 1 29 0 168 4872FG-256 PCT 3 148 0 133 19680FG-456,556 PCT 1 22 0 168 3696FG-676 PCT 1 22 0 96 2112FG-680 PCT 1 31 0 96 2976FG-900 PCT 2 54 0 168 9072FG-1156 PCT 1 22 0 168 3696

25 823 100680

B5_Fabula 27

Temperature Humidity Bias

• Performed to 85°C, 85%RH, Nominal Vcc

• Moisture Pre-stress to Level 3

• Full Solder Simulation per JESD20

• Minimum of 1,000 hours

• Full Production Testing at end of Stress

• Package Decapsulation at End of Test to check for Corrosion

B5_Fabula 28

Temperature Humidity Bias

Package Test Lots Devices Fails Hrs/Cyc Total Hrs/CycPQFP-100 85/85 1 45 0 1117 50265PQFP-160 85/85 3 197 0 1118 220295PQFP-208 85/85 1 45 0 1148 51660PQFP-240 85/85 6 268 0 1003 268832

11 555 591052

Package Test Lots Devices Fails Hrs/Cyc Total Hrs/CycBGA-225,256 85/85 1 74 0 1010 74740BGA-432 85/85 1 16 0 1166 18656BGA-560 85/85 3 50 0 1136 56796

5 140 150192

B5_Fabula 29

Highly Accelerated Stress Test

• Performed at 130°C, 85%RH, 2atm, Vcc

• Moisture Pre-stress to Level 3

• Full Solder Simulation per JESD20

• Minimum of 100 hours

• Full Production Testing at end of Stress

• Package Decapsulation at End of Test to check for Corrosion

B5_Fabula 30

Highly Accelerated Stress Test

Package Test Lots Devices Fails Hrs/Cyc Total Hrs/CycPQFP-160 HAST 1 15 0 300 4500PQFP-208 HAST 1 12 0 300 3600PQFP-240 HAST 6 170 0 135 23000

8 197 31100

Package Test Lots Devices Fails Hrs/Cyc Total Hrs/CycBGA-560 Hast 3 45 0 100 4500BGA-728 Hast 1 21 0 102 2142FG-256 Hast 2 42 0 150 6300FG-456,556 Hast 1 8 0 300 2400FG-900 Hast 3 66 0 100 6600FG-1156 Hast 1 22 0 100 2200

11 204 24142

B5_Fabula 31

Board Level Reliability Test

FG676, FG680, FG860, & FG1156

B5_Fabula 32

P a c k a g e D e t a i l s

M o t h e r b o a r d D e s i g n & A s s e m b l y D e t a i l s– 4 L a y e r , F R - 4 , 1 . 6 m m T h i c k , O S P F i n i s h– 0 . 3 8 m m P a d D i a m e t e r / 0 . 5 3 m m S o l d e r M a s k O p e n i n g ( N S M D P a d s )– 0 . 2 0 m m S S L a s e r C u t S t e n c i l , 0 . 4 3 m m A p e r t u r e O p e n i n g , N o C l e a n P a s t e

T e s t C o n d i t i o n s– T C 1 : - 4 0 < > 1 2 5 o C , 1 5 m i n u t e s r a m p s , 1 5 m i n u t e s d w e l l s , 1 c y c l e / h o u r– T C 2 : - 5 5 < > 1 2 5 o C , 3 m i n u t e s r a m p s , 1 2 m i n u t e s d w e l l s , 2 c y c l e s / h o u r– T C 3 : 0 < > 1 0 0 o C , 1 0 m i n u t e s r a m p s , 5 m i n u t e s d w e l l s , 2 c y c l e s / h o u r

F a i l u r e C r i t e r i a– C o n t i n u o u s S c a n n i n g o f D a i s y C h a i n N e t s ( E v e r y 2 m i n u t e s )– T h r e s h o l d R e s i s t a n c e : 5 0 0 o h m s– O P E N : A n E v e n t w i t h R e s i s t a n c e o f N e t > T h r e s h o l d R e s i s t a n c e– F A I L : A t L e a s t 2 O P E N s w i t h i n a T e m p e r a t u r e C y c l e– L o g 1 5 F A I L U R E S f o r e a c h N e t

P a c k a g e S i z e I / O P i t c h B a l l S i z eP a d

O p e n i n gP a d

T y p eD i e S i z e S u b s t r a t e

F G 8 6 0 ( S B G A ) 4 2 . 5 x 4 2 . 5 8 6 0 1 . 0 0 . 6 0 . 4 8 S M D 2 2 . 4 5 x 2 1 . 4 4 x 0 . 3 0 . 9 8 T h k , 3 L a y e r

F G 1 1 5 6 ( P B G A ) 3 5 x 3 5 1 1 5 6 1 . 0 0 . 6 0 . 4 8 S M D 2 3 . 1 1 x 2 1 . 1 3 x 0 . 3 0 . 5 6 T h k , 4 L a y e r

F G 6 7 6 ( P B G A ) 2 7 x 2 7 6 7 6 1 . 0 0 . 6 0 . 4 8 S M D 1 7 . 8 x 1 7 . 8 x 0 . 3 0 . 5 6 T h k , 4 L a y e r

F G 6 8 0 ( S B G A ) 4 0 x 4 0 6 8 0 1 . 0 0 . 6 0 . 4 8 S M D 2 0 . 3 x 2 0 . 3 x 0 . 3 0 . 9 8 T h k , 3 L a y e rA l l D i m e n s i o n s i n m m

2nd Level Reliability TestXilinx FG676, FG680, FG860, &FG1156

B5_Fabula 33

2nd Level Reliability TestXilinx FG676, FG680, FG860, &FG1156

Summary of Test Results

All Packages Passed at least 1000 cycles of TC1 & TC2 Conditions

TC2 is more Damaging than TC1 for FG680 (Heat Slug Package), NoSignificant Difference for FG676 & FG1156 (PBGA Type Packages)

PackageTest

ConditionCycles

Completed# Tested # Failed

1st Failure (cycles)

Mean Life (cycles)

FG676 TC1 2112 32 27 1341 1830FG676 TC2 2126 32 26 1434 1788FG676 TC3 7029 32 4 5909* N/AFG680 TC1 5222 29 20 4219 4796FG680 TC2 3960 32 16 2883 3891FG680 TC3 6790 32 0 N/A N/AFG860 TC3 5044 32 0 N/A N/A

FG1156 TC1 3108 32 30 1601 2386FG1156 TC2 2507 48 32 1666 2256FG1156 TC3 5044 32 0 N/A N/A

* First failure

B5_Fabula 34

2nd Level Reliability Test - FG676 (PBGA) Package

Motherboard– 1.6mm Thick

– 0.38mm Pad NSMD

Test Data– Failures Primarily

Around Die Edge– No Significant

Difference BetweenTC1 and TC2Results

Package Size I/O Pitch Ball SizePad

OpeningPad Type

Die Size Substrate

FG676 (PBGA) 27x27 676 1.0 0.6 0.48 SMD 17.8x17.8x0.3 0.56 Thk, 4 LayerAll Dimensions in mm

PackageTest

ConditionCycles

Completed# Tested # Failed

1st Failure (cycles)

Mean Life (cycles)

FG676 TC1 2112 32 27 1341 1830FG676 TC2 2126 32 26 1434 1788FG676 TC3 7029 32 4 5909* N/A

1.0

5.0

10.0

50.0

99.0

500.0 5000.0

FG676

Cycles to Failure

Cum

ula

tive

% F

aile

d

WeibullTC1

TC2

B5_Fabula 35

2nd Level Reliability Test - FG680 (SBGA) Package

Motherboard– 1.6mm Thick

– 0.38mm Pad NSMD

Test Data– TC2 is 1.25X More

Damaging

PackageTest

ConditionCycles

Completed# Tested # Failed

1st Failure (cycles)

Mean Life (cycles)

FG680 TC1 5222 29** 20 4219 4796FG680 TC2 3960 32 16 2883 3891FG680 TC3 6790 32 0 N/A N/A

1.0

5.0

10.0

50.0

99.0

1000.0 10000.0

FG680

Cycles to Failure

Cum

ula

tive

% F

aile

d

WeibullTC1

TC2

Package Size I/O Pitch Ball SizePad

OpeningPad Type

Die Size Substrate

FG680 (SBGA) 40x40 680 1.0 0.6 0.48 SMD 20.3x20.3x0.3 0.98 Thk, 3 LayerAll Dimensions in mm

B5_Fabula 36

2nd Level Reliability Test - FG1156 (PBGA) Package

Motherboard– 1.6mm Thick

– 0.38mm Pad NSMD

Test Data– 2 Separate Nets/Device

Inside the DieOutside the Die

– Nets Inside the DieFailed First

Failures PrimarilyUnderneath the Die

– No SignificantDifference BetweenTC1 and TC2 Results

Package Size I/O Pitch Ball SizePad

OpeningPad Type

Die Size Substrate

FG1156 (PBGA) 35x35 1156 1.0 0.6 0.48 SMD 23.11x21.13x0.3 0.56 Thk, 4 LayerAll Dimensions in mm

PackageTest

ConditionCycles

Completed# Tested # Failed

1st Failure (cycles)

Mean Life (cycles)

FG1156 TC1 3108 32 30 1601 2386FG1156 TC2 2507 48 32 1666 2256FG1156 TC3 5044 32 0 N/A N/A

1.0

5.0

10.0

50.0

99.0

1000.0 10000.0

FG1156

Cycles to Failure

Cum

ula

tive

% F

aile

d

Weibull TC1-Die Region

TC1-Perimeter

TC2-Die Region

B5_Fabula 37

2 n d L e v e l R e l i a b i l i t y T e s t - F G 8 6 0 ( S B G A ) P a c k a g e

M o t h e r b o a r d– 1 . 6 m m T h i c k

– 0 . 3 8 m m P a d N S M D

T e s t D a t a– T C 3 O n l y– 5 0 4 4 C y c l e s

C o m p l e t e d– N o F a i l u r e s

P a c k a g e S i z e I / O P i t c h B a l l S i z eP a d

O p e n i n gP a d

T y p eD i e S i z e S u b s t r a t e

F G 8 6 0 ( S B G A ) 4 2 . 5 x 4 2 . 5 8 6 0 1 . 0 0 . 6 0 . 4 8 S M D 2 2 . 4 5 x 2 1 . 4 4 x 0 . 3 0 . 9 8 T h k , 3 L a y e rA l l D i m e n s i o n s i n m m

P a c k a g eT e s t

C o n d i t i o nC y c l e s

C o m p l e t e d# T e s t e d # F a i l e d

1 s t F a i l u r e

( c y c l e s )

M e a n L i f e ( c y c l e s )

F G 8 6 0 T C 3 5 0 4 4 3 2 0 N / A N / A

B5_Fabula 38

Packaging Industry Evolution

1960’s

THRU-HOLE Packages

DIPs2.54 mm Pitch

1980 - 1990

PQFP0.8 - 0.5 mm

PLCC1.27 mm

PERIMETER SMTPackages

SOIC1.27 - 0.5 mm

• High Perform

ance

• High Pincounts / I/Os

• Product Miniaturiz

ation

• Portables

Size and Perfo

rmance

Limita

tions

1991 Millennium

BGA 1.27mm

FBGA 1.0 mm

CSP 0.8 - 0.5 mm

XILINX1999-2000

AREA ARRAY SMTPackages

B5_Fabula 39

560676

11561156 1156

1997 1998 1999 2000 2001 2002

1760

900

1521

2000

900

256 256

Advanced Package and Technology Roadmap

Y1997-Y2002

1010 1010 10102020

30304040

Power Power (Watts)(Watts)

42.5 x 42.542.5 x 42.5 42.5 x 42.542.5 x 42.5 42.5 x 42.542.5 x 42.5 45 x 4545 x 45 45 x 4545 x 45 45 x 4545 x 45

Package SizePackage Size

PincountPincountRangeRange

19 x 21 19 x 2123 x 21

24 x 22

28 x 25 28 x 25

Max Die SizeMax Die Size

Xilinx BGA Packaging Strategy

• Highest Power / Thermal Dissipation• Highest Density / IOs• High Performance Interconnect Enabler• Feature Crammed, High Speed Switching Systems• Advanced High-End Products

• Mid-Range / Mainstream• General Functions• Off-the-Shelf• User Friendly• Cost Effective

• Miniaturization, Light Weight• Wireless Communication• Height Restriction • PCMCIA, Portables• Low Cost and High Volume

Virtex

Spartan

CPLD

0.8-0.5mm

1.0-1.27mm

“SBGA”Cu-Based BGA352-860 pins

• High Power / Thermal Dissipation• High Density / IOs• High Performance / Frequency Design• Feature Crammed, High Speed Switching

Systems

Flip Chip BGA> 900 - 1500 pins

1 . 3 8 m m

“FinePitch BGA”Plastic Molded BGA

256-1156 pins

“CSP”Flex-Based BGA

48-280 pins

1.0mm