B_11_AMSD

M.Sharan kumar goud -11011J6036

E.Abhilash kumar -11011J6019

A.shereesha -11011J6054

Shereesha (2010 batch)

Two stage OP-AMP with biasing

AMSD mini- project

BATCH-11

Aim

To design a two stage operational amplifier using Design galaxy custom designer tool.

Tools used

Synopsys Design galaxy custom designer

Circuit diagram

Schematic Images

Brief explaination of the tool used

Galaxy Custom Designer® SE is the next-generation choice for schematic entry, enabling users to meet the challenges of today’s nanometer designs with little or no learning curve. As with all Custom Designer tools, schematic editing tasks are accomplished with fewer clicks, quicker menu access, and less pop-up menu clutter.

Custom Designer SE utilizes Synopsys’ common simulator use model, allowing access to Synopsys’ leading AMS simulators, including HSPICE and CustomSim.During simulation and debug, Custom Designer SE provides quick access to any simulator through simple pull-down menus.

The Synopsys tools used for this project are integrated in the Synopsys custom design environment, which makes using them in a flow convenient and efficient. Fig. shows our custom design flow and the tools used in each stage.

Steps to create and simulate the design using custom designer

1. Setting Up Your Workspace

Copy the libs.def file to you folder from the saed90nmpdk folder and Define the path in that file as “DEFINE cdesigner ../cdesigner”.After you invoke the cdesigner the screen appears as below

2. Creating the library

Use File -> New -> Library to create a new library.The window appears as follows

Custom Designer SE

Hspice

Analysis Custom waveview

3. Creating the cell

Use File> NewÆ> CellView to create a new Cell View under the library that you create

4. Schematic editor window opens as follows

5. In the above window place all your schematic components and

6. After placing the pmos and nmos transistors, the schematic should look like below.

7. Next add wires to the schematic,

8. Adding Pins

9. Creating the symbol

10. Simulation steps

How to Simulate and Generate Netlist Goto Tools->Simulation->Click ok On it You will find simulation tab on the top side of the panel Select simulation ->initialize->new->click o create Now Goto cdesigner you will find “cell name_tb.HPSICE1”-> open analysis file -> remove comment and change- .trans 0.1m 10m TIME=0->SAVE IT Open params file->remove comment before-.params vdd=1.8 Open Model file and include following path

.lib ‘/home/11011J6031/Desktop/amd/SAED_PDK90nm/hspice/SAED90nm.lib’ TT_12

Simulate and run

Successful simulation status message

11. To see the wave formsGoto cdesigner folder->”cell name_tbhpsice1”->results->open terminal->type wv netlist.tr0

12. To see the netlist Goto cdesigner folder->”cell name_tbhpsice1->netlist->netlist.sp

Explanation of operational amplifier

Operational amplifiers are an integral part of many analog and mixed signal systems. Op amps with vastly different levels of complexity are used to realize functions ranging from dc bias generation to high speed amplification or filtering. Here we are going to see ideal op amp and its parameters values, basic op amp structure and its parameters such as gain bandwidth product, common mode rejection ratio, power supply rejection ratio etc . Ideally op amp is differential amplifier with two inputs and one output, infinite gain, infinite input resistance so that no loading effect can occur and zero output resistance

Figure : 1Standard op amp notation.The Thevenin amplifier model is shown in Fig. 1 below, showing standard op amp notation. It amplifies the voltage difference, Vd= Vp- Vn, on the input port and produces a voltage, Vo, on the output port that is referenced to ground. The ideal op amp model wasderived to simplify circuit calculations and is commonly used by engineers in first order approximation calculations. The ideal model makes three simplifying assumptions: Gain Av= ∞ Input Resistance Ri = ∞ Output Resistance Ro= 0 Common mode gain = 0

op-amp stages We can define as a “high-gain differential amplifier”. By high we mean a value that isadequate for the application, typically in the range of 101to 105. Since op amps are usually employed to implement feedback system, their open loop gain is chosen according to the precision required of the closed loop circuit

A classic op amp architecture is made up of three stage as shown in, even though it is referred to as a “two-stage” op amp, ignoring the buffer stage (third stage). The first stage usually consists of a high-gain differential amplifier. This stage has the most dominant pole of the system. A common source amplifier usually meets the specification of second stage, having a moderate gain. The third stage is most commonly implemented as a unity gain source follower with a high frequency and negligible pole .With the two stage classic op-amp architecture, high gain stages are difficult to achieve with Complementary Metal Oxide Semiconductor (CMOS) technology and basic 8amplifier topologies. A typical CMOS differential amplifier stage is shown aboveDifferential amplifiers are often desired as the first stage in an op amp due to their differential input to single ended output conversation and high gain. The input devices in above are p-channel MOSFETs (PMOS). PMOS input devices are used more because of its improved slew rate and reduced 1/f noise. PMOS input devices also provides reduced power supply rejection due to the current mirror’s low sensitivity to change in power supply voltage

.

Figure : CMOS differential input stage

For the CMOS differential input stage, the gain and bandwidth are calculated as

respectively. Implementation of cascade scheme can increase the moderate gain of this stage to a high value. The stage’s dominant pole has an output capacitance, C out,consisting of mainly, the drain-to-bulk capacitance of M2and M4. Although often negligible, another pole and zero are generated by M1and M3The second stage implementation of a common source amplifier shown in Fig.Similar to the first stage, additional cascade devices can increase gain of this stage. Higher gains are often desirable for this stage when using Miller compensation techniques, although higher gains leads to lower bandwidth and the designer has to decide between these tradeoffs based on the specifications of the system.

For the circuit in Fig. the gain and bandwidth are calculated as.

Figure : Common source amplifier stage.

The output capacitance is dominated by the drain-to-bulk capacitance of M5and M6The final output stage is normally realized with a simple source follower as shown in Fig. With gain less than, but closer to unity, the source follower acts as a buffer for the previous two stages, reducing the overall gain negligibly and barely affecting the overall \bandwidth with its high frequency pole. The gain for the source follower is defined as

Where, G is the load conductance that the stage will drive.

Figure : Source follower

General considerations

As the negative feedback is used widely in application in processing of analog signal, feedback system, however, suffer from potential instability, i.e. they may oscillate. Let usconsider the negative feedback system shown in Fig. 2.7, the closed - loop transfer function as

Figure 2.8: Showing unity gain bandwidth (UGB), gain margin (GM), phase margin (PM). Figure 2.8: Showing unity gain bandwidth (UGB), gain margin (GM), phase margin (PM).

If βH(s = jω 1) = -1, the gain goes to infinity, and the circuit can amplify its own noise and may oscillate at frequency ω 1. This condition can be expressed as | βH( jω 1)| = 1 βH(jω 1) = -180°,which is known as “Barkhausen’s Criteria” (β is assumed constant, less than or equal unity and independent of frequency). As negative feedback itself introduces 180° of phase shift, and the capacitance within amplifier’s gain stages cause the output signal to lag behind the input signal by 90° for each pole they create. If the sum of these phase lags reaches 360° and gain is sufficient, the feedback signal will be add in phase to the original noise to allow oscillation buildup. The conditions can be summarize as excessive loop gain at frequency for which the phase shift reaches -180° or, excessive phase at frequency for which the loop gain drops to unity. So to avoid instability we must have βH more positive than -180° for |βH| = 1.

Figure : Showing unity gain bandwidth (UGB), gain margin (GM), phase margin (PM).

In a stable system, the gain crossover point must occur well before the phase cross over point. If β is reduced (less feedback is applied), then the magnitude plots of Fig.are shifted down, there by moving the gain cross over closer to the origin and making the feedback system more stable. For the worst case stability (β = 1), we often analyze the magnitude and phase plots for βH = H.

Stability ( phase margin)

After designing each op-amp stage and connecting them together, the op amp usually has poor performance and unstable in the unity feedback configuration. The main merit of the stability is the phase margin, the phase shift at unity gain frequency i.e. | βH| must drop to unity before βHcrosses -180°. The phase of βH at the gain crossover frequency can serve as a measure of stability: the smaller | βH| at this point, the more stable the system.

Phase margin (PM), defined as:

where ω 1 is the gain crossover frequency .

For a phase margin less than 0°, the system is considered to be unstable while for a phase margin between 0° and 45°, system is marginally stable.

Y (jω1 )/ X (jω1) = 1/β,

suggesting a negligible frequency peaking i.e. the step response of the feedback system shows little ringing and providing a fast settling for PM = 60°. For a greater PM, the system becomes more stable but time response slows down. Thus PM = 60° is typically considered the optimum value .For a two stage op-amp, the open-loop transfer function is given by

which assume that A3 is close to unity and that ω3\is very high and negligible. The magnitude and phase function are

Screen shots of different widths and lengths of transistors

Nmos – w=5u ,l=.4u

Pmos - w=2u, l=.2u

Results and Screenshots

DC operating point

AC analysis with gain 63.1db

Unity gain bandwidth with stability phase margin 135 degress

Graph of the voltage follower

Operating point 0.2vTail current 500uAGain 63.1dbPhase margin 135degreesBandwidth 48.68MHz

Distribution of work

M.Sharan kumar goud Implementation of two stage opamp and part of documentation

E.Abhilash kumar Study of Differential amplifier and documentationA.Shereesha Analysis of Common source Shereesha Analysis of Current mirror