AVR Microcontroller Family Assembly Language Programming

AVR Microcontroller Family

Assembly Language ProgrammingUniversity of Akron

Dr. Tim Margush

04/09/23 Dr. Tim Margush - Assembly Language Programming

2

AVR

• Atmel AVR 8-Bit Processors come in a variety of configurations and packages› They all share a common core – registers,

instructions, basic I/O capabilities

• Our focus is the ATMega16


3

ATMega16 Specs

• 131 Instructions

• 32 8-bit GP registers

• Throughput up to 16 MIPS

• 16K programmable flash (instructions)

• 512Bytes EEPROM

• 1K internal SRAM

• Timers, serial and parallel I/O, ADC


4

AVR CPU

• PC: address of next instruction

• IR: prefetched instruction

• ID: current instruction• GPR: R0-R31• ALU: Note internal

data path


5

AVR Memory

• Flash: Machine instructions go here

• SRAM: For runtime data› Note bus independence for

data and instructions

• EEPROM: Secondary storage› EEPROM and Flash

memories have a limited lifetime of erase/write cycles


6

Flash Memory

• Programs reside in word addressable flash storage› Word addresses range from 0000-1FFF (PC is 13 bits)› Byte addresses range 0000-3FFF (0x4000=16K)

• Harvard Architecture› It is possible to use this storage area for constant data as

well as instructions, violating the true spirit of this architecture

• Instructions are 16 or 32-bits› Most are 16-bits and are executed in a single clock

cycle


7

SRAM

• The ATMega16 has 1K (1024 bytes) of byte addressable static RAM› This is used for variable storage and stack space

during execution› SRAM addresses start at $0060 and go through

$045F• The reason for not starting at zero will be covered

later


8

EEPROM

• Electrically Erasable Programmable Read Only Memory› Programs can read or write individual bytes› This memory is preserved when power is

removed› Access is somewhat slow; it serves as a form of

secondary storage


9

Clock

• All processors are pushed through their fetch execute cycle by an alternating 0-1 signal, called a clock

• The ATMega16 can use an internal or external clock signal› Clock signals are usually generated by an RC oscillator

or a crystal• The internal clock is an RC oscillator programmable to 1, 2, 4,

or 8 MHz• An external clock signal (crystal controlled) can be more

precise for time critical applications


10

AVR Machine Language

• AVR instructions are 16 or 32-bits• Each instruction contains an opcode

› Opcodes generally are located in the initial bits of an instruction

• Some instructions have operands encoded in the remaining bits› Opcode and operands are numbers, but their containers

are simply some of the bits in the instruction


11

Load Immediate

• LDI Rd, K› Load a constant into a register (Rd = K)› 1110 bbbb rrrr bbbb

• Limitations: 16 <= d <= 31; 0x00 <= K <= 0xFF

› Opcode is 1110› The register number is coded in bits 7-4

• Only the last 4 bits of the register number are present; a leading 1 is assumed (1rrrr)

› The constant is split into two nybbles


12

LDI Examples

• LDI R16, $2C› 1110 0010 0000 1100 or 0xE20C

• LDI R27, $0F› 27 is 11011› 1110 0000 1011 1111 or 0xE0BF

• Note that this instruction always › starts with E, › has the two nybbles of K at positions 2 and 0, › and encodes the register in nybble 1


13

Add Registers

• ADD Rd, Rr› Add the contents of two registers, store result in

Rd (Rd = Rd + Rr)› 0000 11rd dddd rrrr

• Any registers: 0 <= r <= 31; 0 <= d <= 31

› The opcode is 000011› The register numbers are coded in binary

• Rr has its high bit split off from the others


14

ADD Examples

• ADD R16, R3› ddddd is 10000 and rrrrr is 00011› 0000 1101 0000 0011 or 0x0D03

• ADD R27, R17› ddddd is 11011, rrrrr is 10001› 0000 1111 1011 0001 or 0x0FB1

• Note that this instruction always › starts with 0, › followed by C, D, E, or F› and can have any values in the second byte


15

Expanding Opcodes

• The following are not legal opcodes› 1, 11, 111

• No opcode longer than 4 bits starts 1110› Except ser Rd

› 1110 1111 dddd 1111

• Similarly, no prefix of 000011 is an opcode and no opcode longer than 6 begins with this sequence› Except lsl Rd

› 0000 11dd dddd dddd

LDI: 1110011110110011ADD: 0000111100101101

How does the processor "know" where the opcode portion stops?


16

A Machine Language Program

• Load program into memory› At address 0 we place the word $E20C› At address 1 we place the word $E01F› At address 2 we place the word $0F01

• Execute the three instructions in sequence› Set PC to 0 and perform 3 fetch-execute cycles

• Observe result› R16 has the sum of $2C and $0F, $3B


17

A Machine Language Program

0000: $E20C LDI R16, $2C

0001: $E01F LDI R17, $0F

0002: $0F01 ADD R16, R17

R16 = R16 + R17

= $2C + $0F

= $3B


18

AVR Studio

• An integrated development environment › Provides a text editor› Supports the AVR assembler› Supports the gnu C compiler› Provides an AVR simulator and debugger› Provides programming support for the AVR

processors via serial interface


19

AVR Studio: New Project

• Start AVR Studio

• Click New Project

• Select type: Assembler

• Choose a project name

• Select create options and pick a location

• Location should be a folder to hold all project folders

• Each project should be in its own folder


20

AVR Studio: New Project

• On the next dialog, select the Debug platform: AVR Simulator

• Pick the device type: ATMega16

• Finish


21

AVR Studio: Interface

• Enter the program in the assembly source file that is opened for you.

• Click the Assemble button (F7)

Assemble

Workspace

Output

Editor


22

AVR Studio: Assembler Report

• Assembler summary indicates success› 6 bytes of code, no data, no errors


23

AVR Studio: Debugger

• Start the debugging session› Click Start Debugging› Next instruction is shown with yellow arrow

• Choose I/O View› View registers 16-17

• Step through program› F10 is Step Over

Start Debugging


24

AVR Studio: Debugger

• The first 2 instructions are completed› R16 and R17 have the expected values from the

LDI instructions

• The sum is placed in R16› $3B is the sum


25

AVR Studio: Memory

• Memory contents may be viewed (and edited) during debugging› You can view program (flash), data (SRAM),

or EEPROM memory› You can also view the general purpose and I/O

registers using this tool The Program


26

Using Mnemonics

• Rather than code the machine language program as a sequence of numeric word values expressed in hexadecimal, assembly language programmers usually use instruction mnemonics

• This program will assemble and run identically to the first› ldi R16, $2C› ldi R17, $0F› add R16, R17


27

What's Next?

• In our sample program, we executed three instructions, what comes next?› Undefined! Depends

on what is in flash

• How do we terminate a program?› Use a loop!

0000: $E20C LDI R16, $2C

0001: $E01F LDI R17, $0F

0002: $0F01 ADD R16, R17

0003: $???? ???

If a program is to simply stop, add an instruction that jumps to its own address


28

Relative Jump

• RJMP K 1100 kkkk kkkk kkkk› -2048 <= K < 2048

• According to the manufacturer specifications, this instruction causes this action: › PC = PC + 1 + K

• We want K = -1› This will cause a jump to the address from which the

instruction was fetched


29

Relative Jump

• Here: RJMP Here 1100 kkkk kkkk kkkk› K = -1 ($FFF)› 1100 1111 1111 1111 or $CFFF

0000: $E20C LDI R16, $2C

0001: $E01F LDI R17, $0F

0002: $0F01 ADD R16, R17

0003: $CFFF RJMP -1

0004: $???? ???This distance is -1 word

Remember that the program counter is incremented before the instruction is executed

AVR Microcontroller Family Assembly Language Programming

Documents