Avionics_Principles of Digital Systems

8/6/2019 Avionics_Principles of Digital Systems

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LOGIC GATES

THEORY:

Circuit that takes the logical decision and the process are called logic gates.

Each gate has one or more input and only one output.OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as

universal gates. Basic gates form these gates.

AND GATE:

The AND gate performs a logical multiplication commonly known as AND

function. The output is high when both the inputs are high. The output is low level

when any one of the inputs is low.

OR GATE:The OR gate performs a logical addition commonly known as OR function.

The output is high when any one of the inputs is high. The output is low level

when both the inputs are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is

low. The output is low when the input is high.

NAND GATE:The NAND gate is a contraction of AND-NOT. The output is high when

both inputs are low and any one of the input is low .The output is low level when

both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both

inputs are low. The output is low when one or both inputs are high.

X-OR GATE:The output is high when any one of the inputs is high. The output is low

when both the inputs are low and both the inputs are high.


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AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:


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NOT GATE:


X-OR GATE :

SYMBOL : PIN DIAGRAM :


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2-INPUT NAND GATE:


3-INPUT NAND GATE :


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NOR GATE:

ADDER AND SUBTRACTOR

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs

one from the sum S and other from the carry c into the higher adder position.

Above circuit is called as a carry signal from the addition of the less significant

bits sum from the X-OR Gate the carry out from the AND gate.

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of

input; it consists of three inputs and two outputs. A full adder is useful to add three

bits at a time but a half adder cannot do so. In full adder sum output will be taken

from X-OR Gate, carry output will be taken from OR Gate.

HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half

subtractor has two input and two outputs. The outputs are difference and borrow.


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The difference can be applied using X-OR Gate, borrow output can be

implemented using an AND Gate and an inverter.

FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In afull subtractor the logic circuit should have three inputs and two outputs. The two

half subtractor put together gives a full subtractor .The first half subtractor will be

C and A B. The output will be difference output of full subtractor. The expression

AB assembles the borrow output of the half subtractor and the second term is the

inverted difference output of first X-OR.

LOGIC DIAGRAM:

HALF ADDER

TRUTH TABLE:

A B CARRY SUM

0

0

1

1

0

1

0

1

0

0

0

1

0

1

1

0


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K-Map for SUM: K-Map for CARRY:

SUM = AB + AB CARRY = AB

LOGIC DIAGRAM:

FULL ADDER

FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:

A B C CARRY SUM

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

0

0

1

0

1

0

1

1

0

1

0


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1

1

1

1

0

1

1

1

0

1

K-Map for SUM:

SUM = ABC + ABC + ABC + ABC

K-Map for CARRY:

CARRY = AB + BC + AC


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LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:

A B BORROW DIFFERENCE

0

0

1

1

0

1

0

1

0

1

0

0

0

1

1

0

K-Map for DIFFERENCE:

DIFFERENCE = AB + AB

K-Map for BORROW:

BORROW = AB


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LOGIC DIAGRAM:

FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:

A B C BORROW DIFFERENCE

0

0

0

0

11

1

1

0

0

1

1

00

1

1

0

1

0

1

01

0

1

0

1

1

1

00

0

1

0

1

1

0

10

0

1


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K-Map for Difference:

Difference = ABC + ABC + ABC + ABC

K-Map for Borrow:

Borrow = AB + BC + AC

CODE CONVERTOR

THEORY:

The availability of large variety of codes for the same discrete elements of

information results in the use of different codes by different systems. A conversion

circuit must be inserted between the two systems if each uses different codes for

same information. Thus, code converter is a circuit that makes the two systems

compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code

uses four bits to represent a decimal digit. There are four inputs and four outputs.

Gray code is a non-weighted code.


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The input variable are designated as B3, B2, B1, B0 and the output

variables are designated as C3, C2, C1, Co. from the truth table, combinational

circuit is designed. The Boolean functions are obtained from K-Map for each

output variable.

A code converter is a circuit that makes the two systems compatible eventhough each uses a different binary code. To convert from binary code to Excess-3

code, the input lines must supply the bit combination of elements as specified by

code and the output lines generate the corresponding bit combination of code.

Each one of the four maps represents one of the four outputs of the circuit as a

function of the four input variables.

A two-level logic diagram may be obtained directly from the Boolean

expressions derived by the maps. These are various other possibilities for a logic

diagram that implements this circuit. Now the OR gate whose output is C+D has

been used to implement partially each of three outputs.

MULTIPLEXER AND DEMULTIPLEXER

MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a

smaller number of channels or lines. A digital multiplexer is a combinational

circuit that selects binary information from one of many input lines and directs it

to a single output line. The selection of a particular input line is controlled by a setof selection lines. Normally there are 2

ninput line and n selection lines whose bit

combination determine which input is selected.

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It

takes information from one line and distributes it to a given number of output

lines. For this reason, the demultiplexer is also known as a data distributor.

Decoder can also be used as demultiplexer.

In the 1: 4 demultiplexer circuit, the data input line goes to all of the ANDgates. The data select lines enable only one gate at a time and the data on the data

input line will pass through the selected gate to the associated data output line.


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BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

S1 S0 INPUTS Y

0 0 D0 D0 S1 S0

0 1 D1 D1 S1 S0

1 0 D2 D2 S1 S01 1 D3 D3 S1 S0


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TRUTH TABLE:

S1 S0 Y = OUTPUT

0 0 D00 1 D1

1 0 D2

1 1 D3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0

S1 S0 INPUT

0 0 X D0 = X S1 S0

0 1 X D1 = X S1 S0

1 0 X D2 = X S1 S0

1 1 X D3 = X S1 S0


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PIN DIAGRAM FOR IC 74150:



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`ENCODER AND DECODER

ENCODER:

An encoder is a digital circuit that perform inverse operation of a decoder.

An encoder has 2

n

input lines and n output lines. In encoder the output linesgenerates the binary code corresponding to the input value. In octal to binary

encoder it has eight inputs, one for each octal digit and three output that generate

the corresponding binary code. In encoder it is assumed that only one input has a

value of one at any given time otherwise the circuit is meaningless. It has an

ambiguila that when all inputs are zero the outputs are zero. The zero outputs can

also be generated when D0 = 1.

DECODER:

A decoder is a multiple input multiple output logic circuit which convertscoded input into coded output where input and output codes are different. The

input code generally has fewer bits than the output code. Each input code word

produces a different output code word i.e there is one to one mapping can be

expressed in truth table. In the block diagram of decoder circuit the encoded

information is present as n input producing 2n

possible outputs. 2n

output values

are from 0 through out 2n

1.


BCD TO DECIMAL DECODER:


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LOGIC DIAGRAM FOR ENCODER:


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TRUTH TABLE:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 00 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:


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TRUTH TABLE:

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 10 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

SHIFT REGISTER

A register is capable of shifting its binary information in one or both directions is

known as shift register. The logical configuration of shift register consist of a D-

Flip flop cascaded with output of one flip flop connected to input of next flip flop.

All flip flops receive common clock pulses which causes the shift in the output of

the flip flop. The simplest possible shift register is one that uses only flip flop.

The output of a given flip flop is connected to the input of next flip flop of the

register. Each clock pulse shifts the content of register one bit position to right.

Shift registers can have a combination of serial and parallel inputs and outputs,including serial-in, parallel-out (SIPO) and parallel-in, serial-out (PISO) types.

There are also types that have both serial and parallel input and types with serial

and parallel output. There are also bi-directional shift registers which allow you

to vary the direction of the shift register. The serial input and outputs of a register

can also be connected together to create a circular shift register. One could also

create multi-dimensional shift registers, which can perform more complex

computation.


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PIN DIAGRAM:

LOGIC DIAGRAM: SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK

Serial in Serial out

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1


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LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:

TRUTH TABLE:

CLK DATA

OUTPUT

QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1

LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:


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TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 03 0 0 0 0 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

CLK

DATA INPUT OUTPUT

DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

INTRODUCTION TO 8 BIT AND 16 BIT MICROPROCESSORS H/W

ARCHITECTURE

COMPUTER AND ITS ORGANIZATION

A Computeris a programmable machine. It responds to a specific set of instructions

in a well-defined manner. It can execute a prerecorded list of instructions (a

program ).Modern computers are electronic and digital. The actual machinery wires,

transistors, and circuits is called hardware. The instructions and data are called

software.


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All general-purpose computers require the following hardware components:

Memory: Enables a computer to store, at least temporarily, data and programs.

Mass storage device: Allows a computer to permanently retain large amounts of

data. Common mass storage devices include disk drives and tape drives.

Input device: Usually a keyboard and mouse are the input device through whichdata and instructions enter a computer.

Output device: A display screen, printer, or other device that lets you see what the

computer has accomplished.

Central processing unit (CPU): The heart of the computer, this is the component

that actually executes instructions.

In addition to these components, many others make it possible for the basic

components to work together efficiently.

For example, every computer requires a bus that transmits data from one part of

the computer to another.Computers can be generally classified by size and power as follows, though there is

considerable overlap:

Personal computer: A small, single-user computer based on a microprocessor. In

addition to the microprocessor, a personal computer has a keyboard for entering

data, a monitor for displaying information, and a storage device for saving data.

Working station: A powerful, single-user computer. A workstation is like a

personal computer, but it has a more powerful microprocessor and a higherquality

monitor.

Minicomputer: A multi-user computer capable of supporting from 10 to hundredsof users simultaneously.

Mainframe: A powerful multi-user computer capable of supporting many hundreds

or thousands of users simultaneously.

Supercomputer: An extremely fast computer that can perform hundreds of millions

of instructions per second.

Minicomputer:

A midsized computer. In size and power, minicomputers lie between workstations

and mainframes.

A minicomputer, a term no longer much used, is a computer of a size intermediatebetween a microcomputer and a mainframe.

Typically, minicomputers have been stand-alone computers (computer systems with

attached terminals and other devices) sold to small and mid-size businesses for

general business applications and to large enterprises for department-level

operations.


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Workstation:

A type of computer used for engineering applications (CAD/CAM), desktop

publishing, software development, and other types of applications that require a

moderate amount of computing power and relatively high quality graphics

capabilities.Workstations generally come with a large, high- resolution graphics screen, at least

64 MB (mega bytes) of RAM, built-in network support, and a graphical user

interface.

Microcomputer: The term microcomputer is generally synonymous with personal

computer, or a computer that depends on a microprocessor.

Microcomputers are designed to be used by individuals, whether in the form of PCs,

workstations or notebook computers.

A microcomputer contains a CPU on a microchip (the microprocessor), a memory

system (typically ROM and RAM), a bus system and I/O ports, typically housed in amotherboard.

INTRODUCTION TO MICROPROCESSORMicroprocessor: A silicon chip that contains a CPU. In the world of personal

Computers, the terms microprocessor and CPU are used interchangeably. A

microprocessor (sometimes abbreviated P) is a digital electronic component with

miniaturized transistors on a single semiconductor integrated circuit (IC).One or

more microprocessors typically serves as a central processing unit (CPU) in a


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computer system or handheld device. Microprocessors made possible the advent of

the microcomputer. At the heart of all personal computers and most working

stations sits a microprocessor.

Microprocessors also control the logic of almost all digital devices, from clock

radios to fuel-injection systems for automobiles.Three basic characteristics differentiate microprocessors:

Instruction set: The set of instructions that the microprocessor can execute.

Bandwidth: The number of bits processed in a single instruction.

Clock speed: Given in megahertz (MHz), the clock speed determines how many

instructions per second the processor can execute.

Microcontroller:A highly integrated chip that contains all the components comprising a controller.

Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers.

Unlike a general-purpose computer, which also includes all of these components, a

microcontroller is designed for a very specific task - to control a particular system.

A microcontroller differs from a microprocessor, which is a general-purpose chip

that is used to create a multi-function computer or device and requires multiple

chips to handle various tasks. A microcontroller is meant to be more self-contained

and independent, and functions as a tiny, dedicated computer.

The great advantage of microcontrollers, as opposed to using largermicroprocessors, is that the parts-count and design costs of the item being controlled

can be kept to a minimum. They are typically designed using CMOS

(complementary metal oxide semiconductor) technology, an efficient fabrication

technique that uses less power and is more immune to power spikes than other

techniques. Microcontrollers are sometimes called embedded microcontrollers,

which just means that they are part of an embedded system that is, one part of a

larger device or system

Embedded system:An Embedded System is a specialized computer system that is part of a larger

system or machine. Typically, an embedded system is housed on a single

microprocessor board with the programs stored in ROM. Virtually all appliances

that have a digital Interface- watches, microwaves, VCRs, cars -utilize embedded


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systems. Some embedded systems include an operating system, but many are so

specialized that the entire logic can be implemented as a single program.

Address Bus, Data Bus and Control Bus

The preferred method for data/information transfer between system components isby a common data bus. Where point-to-point data transfer is required, the

digital format is the preferred method

Control Bus

The control bus is used by the CPU to direct and monitor the actions of the other

functional areas of the computer. It is used to transmit a variety of individual

signals (read, write, interrupt, acknowledge, and so

forth) necessary to control and coordinate the operations of the computer.The individual signals transmitted over the control bus and their functions are

covered in the appropriate functional area description.

Address Bus

The address bus consists of all the signals necessary to define any of the possible

memory address locations within the computer, or for modular memories any of the

possible memory address locations within a module. An address is defined as a

label, symbol, or other set of characters used to designate a location or register

where information is stored. Before data or instructions can be written into or readfrom memory by the CPU or I/O sections, an address must be transmitted to

memory over the address bus.

Data Bus

The bidirectional data bus, sometimes called the memory bus, handles the transfer

of all data and instructions between functional areas of the computer. The bi

directional data bus can only transmit in one direction at a time. The data bus is

used to transfer instructions from memory to the CPU for execution. It carries data(operands) to and from the CPU and

memory as required by instruction translation. The data bus is also used to

transfer data between memory and the I/O section during input/output operations


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Tristate bus

Three-state, tri-state, or 3-state logic allows an output port to assume a high

impedance state in addition to the 0 and 1 logic levels, effectively removing the

output from the circuit. This allows multiple circuits to share the same output line or

lines (such as a bus).

Three-state outputs are implemented in many registers, bus drivers, and flip-flops in

the 7400 and 4000 series as well as in other types, but also internally in

many integrated circuits. Other typical uses are internal and external buses

in microprocessors, memories, and peripherals. Many devices are controlled by

an active-low input called OE (Output Enable) which dictates whether the outputs

should be held in a high-impedance state or drive their respective loads (to either 0-or 1-level).

Clock generation

A clock generator is a circuit that produces a timing signal (known as a clock

signal and behaves as such) for use in synchronizing a circuit's operation. The signal

can range from a simple symmetrical square wave to more complex arrangements.

The basic parts that all clock generators share are a resonant circuit and an amplifier.

The resonant circuit is usually a quartz piezo-electric oscillator, although

simpler tank circuits and even RC circuits may be used.

The amplifier circuit usually inverts the signal from the oscillator and feeds a

portion back into the oscillator to maintain oscillation.

The generator may have additional sections to modify the basic signal. The 8088 for

example, used a 2/3 duty cycle clock, which required the clock generator to

incorporate logic to convert the 50/50 duty cycle which is typical of raw oscillators.


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Other such optional sections include frequency divider or clock multiplier sections.

Programmable clock generators allow the number used in the divider or multiplier

to be changed, allowing any of a wide variety of output frequencies to be selected

without modifying the hardware.

The clock generator in a motherboard is often changed by computer enthusiasts tocontrol the speed of their CPU, FSB, GPU and RAM. Typically the programmable

clock generator is set by the BIOS at boot time to the value selected by the

enthusiast; although some systems have dynamic frequency scalingthat frequently

re-program the clock generator.

Connecting Microprocessor to I/O devices

Memory-mapped I/O (MMIO) and port I/O (also called isolated I/O or port-

mapped I/O abbreviated PMIO) are two complementary methods ofperforming input/output between the CPU andperipheral devices in a computer. An

alternative approach, not discussed in this article, is using dedicated I/O processors

commonly known as channels on mainframe computers that execute their

own instructions.

Memory-mapped I/O (not to be confused with memory-mapped file I/O) uses the

same address bus to address both memory and I/O devices - the memory and

registers of the I/O devices are mapped to (associated with) address values. So when

an address is used by the CPU it may refer to a portion of physical RAM, or it can

instead refer to memory of the I/O device. Thus, the CPU instructions used to access

the memory are also used for accessing devices. Each I/O device monitors the

CPU's address bus and responds to any of the CPU's access of address space

assigned to that device, connecting the data bus to a desirable device's hardware

register. To accommodate the I/O devices, areas of the addresses used by the CPU

must be reserved for I/O and not be available for normal physical memory. The

reservation might be temporary the Commodore 64 could bank switch between

its I/O devices and regular memory or permanent.

Port-mapped I/O uses a special class of CPU instructions specifically for performingI/O. This is generally found on Intel microprocessors, specifically the IN and OUT

instructions which can read and write one to four bytes (outb, outw, outl) to an I/O

device. I/O devices have a separate address space from general memory, either

accomplished by an extra "I/O" pin on the CPU's physical interface, or an

entire bus dedicated to I/O. Because the address space for I/O is isolated from that

for main memory, this is sometimes referred to as isolated I/O.


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A device's direct memory access (DMA) is not affected by those CPU-to-device

communication methods, especially it is not affected by memory mapping. This is

because by definition, DMA is a memory-to-device communication method that

bypasses the CPU.

Hardware interrupt is yet another communication method between CPU andperipheral devices. However, it is always treated separately for a number of reasons.

It is device-initiated, as opposed to the methods mentioned above, which are CPU-

initiated. It is also unidirectional, as information flows only from device to CPU.

Lastly, each interrupt line carries only one bit of information with a fixed meaning,

namely "an event that requires attention has occurred in a device on this interrupt

line".

DATA TRANSFER SCHEMES

Synchronous Data Transfer:

Synchronous means at the same time. In this format of data transfer transmitter

and receiver device are synchronized with the same clock pulse.

This type of data transfer format is used in between the devices that match in speed.

This method is invariably used in between memory and microprocessor as they are

compatible.

Asynchronous Data Transfer: -

Asynchronous means at a regular interval. In this method data transfer is not

based on predetermined timing pattern in this technique the status of the IO deviceis checked by the microprocessor before the data is transferred. This method is

invariably used in between microprocessor and IO devices

MODES OF DATA TRANSFER

THE MICROPROCESSOR receives or transmits binary data in either of two mode:-

PARALLEL MODE:-In a parallel mode , the entire word is transferred at one time

.the device commonly used for data transfer are keyboards seven segment LEDs

data converters and memory.

SERIAL MODE:-In the serial mode , data are transferred one bit at a time over a

single line between the microprocessors and a peripheral. It is commonly used with

peripherals such as CRT terminals , printers, cassette tapes and modems for

telephone.


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DMA:

Direct Memory Access (DMA) is a method of allowing data to be moved from one

location to another in a computer without intervention from the central processor

(CPU).

The way that the DMA function is implemented varies between computer

architectures, so this discussion will limit itself to the implementation and workings

of the DMA subsystem on the IBM Personal Computer (PC), the IBM PC/AT and

all of its successors and clones.

The PC DMA subsystem is based on the Intel 8237 DMA controller. The 8237

contains four DMA channels that can be programmed independently and any one of

the channels may be active at any moment. These channels are numbered 0, 1, 2 and

3. Starting with the PC/AT, IBM added a second 8237 chip, and numbered those

channels 4, 5, 6 and 7.

The original DMA controller (0, 1, 2 and 3) moves one byte in each transfer. The

second DMA controller (4, 5, 6, and 7) moves 16-bits from two adjacent memory

locations in each transfer, with the first byte always coming from an even-numbered

address. The two controllers are identical components and the difference in transfer

size is caused by the way the second controller is wired into the system.

The 8237 has two electrical signals for each channel, named DRQ and -DACK.There are additional signals with the names HRQ (Hold Request), HLDA (Hold

Acknowledge), -EOP (End of Process), and the bus control signals -MEMR

(Memory Read), -MEMW (Memory Write), -IOR (I/O Read), and -IOW (I/O

Write).

The 8237 DMA is known as a fly-by DMA controller. This means that the data

being moved from one location to another does not pass through the DMA chip and

is not stored in the DMA chip. Subsequently, the DMA can only transfer data

between an I/O port and a memory address, but not between two I/O ports or twomemory location


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Instruction Meaning Notes

AAA ASCII adjust AL after addition used with unpacked binary

coded decimal

AAD ASCII adjust AX before division 8086/8088 datasheetdocuments only base 10

version of the AAD

instruction (opcode 0xD5

0x0A), but any other base

will work. Later Intel's

documentation has the

generic form too. NEC V20

and V30 (and possibly

other NEC V-series CPUs)always use base 10, and

ignore the argument,

causing a number of

incompatibilities

AAM ASCII adjust AX after

multiplication

Only base 10 version is

documented, see notes for

AADAAS ASCII adjust AL after subtraction

ADC Add with carry destination := destination +

source + carry_flag

ADD Add

AND Logical AND

CALL Call procedure

CBW Convert byte to word

CLC Clear carry flag

CLD Clear direction flag

CLI Clear interrupt flag

CMC Complement carry flag

CMP Compare operands

CMPSB Compare bytes in memory

CMPSW Compare words

CWD Convert word to doubleword

DAA Decimal adjust AL after addition (used with packed binary

coded decimal)


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DAS Decimal adjust AL after

subtraction

DEC Decrement by 1

DIV Unsigned divide

ESC Used with floating-point unitHLT Enter halt state

IDIV Signed divide

IMUL Signed multiply

IN Input from port

INC Increment by 1

INT Call to interrupt

INTO Call to interrupt ifoverflow

IRET Return from interrupt

Jxx Jump if condition ( JA, JAE, JB, JBE, JC,

JCXZ, JE, JG, JGE, JL,

JLE, JNA, JNAE, JNB,

JNBE, JNC, JNE, JNG,

JNGE, JNL, JNLE, JNO,

JNP, JNS, JNZ, JO, JP,

JPE, JPO, JS, JZ)

JMP Jump

LAHF Load flags into AH register

LDS Load pointer using DS

LEA Load Effective Address

LES Load ES with pointer

LOCK Assert BUS LOCK# signal (for multiprocessing)

LODSB Loadsigned byte

LODSW Loadsigned word

LOOP/LOOPx Loop control ( LOOPE, LOOPNE,

LOOPNZ, LOOPZ)

MOV MoveMOVSB Move byte from string to string

MOVSW Move word from string to string

MUL Unsigned multiply

NEG Two's complement negation

NOP No operation opcode (0x90) equivalent


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to XCHG EAX, EAX

NOT Negate the operand, logical NOT

OR Logical OR

OUT Output to port

POP Pop data from stack POP CS (opcode 0x0F)works only on 8086/8088.

Later CPUs use 0x0F as a

prefix for newer

instructions.

POPF Pop data into flags register

PUSH Push data onto stack

PUSHF Push flags onto stack

RCL Rotate left (with carry)

RCR Rotate right (with carry)

REPxx Repeat

MOVS/STOS/CMPS/LODS/SCAS

( REP, REPE, REPNE,

REPNZ, REPZ)

RET Return from procedure

RETN Return from near procedure

RETF Return from far procedure

ROL Rotate left

ROR Rotate right

SAHF Store AH into flags

SAL Shift Arithmetically left (signed

shift left)

SAR Shift Arithmetically right (signed

shift right)

SBB Subtraction with borrow

SCASB Compare byte string

SCASW Compare word string

SHL Shift left (unsigned shift left)

SHR Shift right (unsigned shift right)STC Setcarry flag

STD Setdirection flag

STI Setinterrupt flag

STOSB Store byte in string

STOSW Store word in string


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SUB Subtraction

TEST Logical compare (AND)

WAIT Wait until not busy Waits until BUSY# pin is

inactive (used with

floating-point unit)XCHG Exchange data

XLAT Table look-up translation

XOR Exclusive OR


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Intel 8085

Intel 8085

An Intel 8085AH processor.

Produced From 1977 to 1990s

Common

manufacturer(s)

Intel and several

others

Max. CPU clock rate 3, 5 and 6 MHz

Instruction set pre x86

Package(s)40 pin DIP

The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977. It was

binary-compatible with the more-famous Intel 8080 but required less supporting

hardware, thus allowing simpler and less expensive microcomputer systems to be

built.

The "5" in the model number came from the fact that the 8085 requires only a +5-

volt (V) power supply rather than the +5V, -5V and +12V supplies the 8080

needed. Both processors were sometimes used in computers running the CP/M

operating system, and the 8085 later saw use as a microcontroller, by virtue of its

low component count. Both designs were eclipsed for desktop computers by the

compatible Zilog Z80, which took over most of the CP/M computer market as well

as taking a share of the booming home computer market in the early-to-mid-

1980s.

The 8085 had a long life as a controller. Once designed into such products as the

DECtape controller and the VT100 video terminal in the late 1970s, it continued to

serve for new production throughout the life span of those products (generally

longer than the product life of desktop computers)


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Description

The 8085 is a conventional von Neumann design based on the Intel 8080. Unlike

the 8080 it does not multiplex state signals onto the data bus, but the 8-bit data bus

was instead multiplexed with the lower part of the 16-bit address bus to limit the

number of pins to 40. Pin #40 is used for the power supply (+5v) and pin #20 for

ground. Pin #39 is used as the hold pin. Pins #15 to #8 are generally used for


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address buses. The processor was designed using nMOS circuitry and the later "H"

versions were implemented in Intel's enhanced nMOS process called HMOS,

originally developed for fast static RAM products. Only a 5 Volt supply is needed,

like competing processors and unlike the 8080. The 8085 uses approximately

6,500 transistors.

[1]

The 8085 incorporates the functions of the 8224 (clock generator) and the 8228

(system controller), increasing the level of integration. A downside compared to

similar contemporary designs (such as the Z80) was the fact that the buses

required demultiplexing; however, address latches in the Intel 8155, 8355, and

8755 memory chips allowed a direct interface, so an 8085 along with these chips

was almost a complete system.

The 8085 has extensions to support new interrupts, with three maskable interrupts

(RST 7.5, RST 6.5 and RST 5.5), one non-maskable interrupt (TRAP), and one

externally serviced interrupt (INTR). The RST n.5 interrupts refer to actual pins on

the processor, a feature which permitted simple systems to avoid the cost of a

separate interrupt controller.

Like the 8080, the 8085 can accommodate slower memories through externally

generated wait states (pin 35, READY), and has provisions for Direct Memory

Access (DMA) using HOLD and HLDA signals (pins 39 and 38). An

improvement over the 8080 was that the 8085 can itself drive a piezoelectric

crystal directly connected to it, and a built in clock generator generates the internal

high amplitude two-phase clock signals at half the crystal frequency (a 6.14 MHz

crystal would yield a 3.07 MHz clock, for instance).

Programming model

The 8085 is a binary compatible follow up on the 8080, using the same basic

instruction set as the 8080 (developed by Computer Terminal Corporation). Only a

few minor instructions were new to the 8085 above the 8080 set.

Registers

The processor has seven 8-bit registers named A, B, C, D, E, H, and L, where A is

the 8-bit accumulator and the other six can be used as independent byte-registers

or as three 16-bit register pairs, BC, DE, and HL, depending on the particular

instruction. Some instructions use HL as a (limited) 16-bit accumulator. As in the


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8080, the contents of the memory address pointed to by HL could be accessed as

pseudoregister M. It also has a 16-bit stack pointer to memory (replacing the

8008's internal stack), and a 16-bit program counter. HL pair is called the primary

data pointers...

Commands/instructions

As in many other 8-bit processors, all instructions are encoded in a single byte

(including register-numbers, but excluding immediate data), for simplicity. Some

of them are followed by one or two bytes of data, which could be an immediate

operand, a memory address, or a port number. Like larger processors, it has CALL

and RET instructions for multi-level procedure calls and returns (which can be

conditionally executed, like jumps) and instructions to save and restore any 16-bit

register-pair on the machine stack. There are also eight one-byte call instructions

(RST) for subroutines located at the fixed addresses 00h, 08h, 10h,...,38h. These

were intended to be supplied by external hardware in order to invoke a

corresponding interrupt-service routine, but are also often employed as fast system

calls. The most sophisticated command was XTHL, which is used for exchanging

the register pair HL with the value stored at the address indicated by the stack

pointer.

8-bit instructions

Most 8-bit operations work on the 8-bit accumulator (the A register). For two

operand 8-bit operations, the other operand can be either an immediate value,

another 8-bit register, or a memory cell addressed by the 16-bit register pair HL.

Direct copying is supported between any two 8-bit registers and between any 8-bit

register and a HL-addressed memory cell. Due to the regular encoding of the

MOV-instruction (using a quarter of available opcode space) there are redundant

codes to copy a register into itself (MOV B,B, for instance), which are of little use,

except for delays. However, what would have been a copy from the HL-addressed

cell into itself (i.e., MOV M,M) instead encodes the HLT instruction, halting

execution until an external reset or interrupt occurred.

16-bit operations

Although the 8085 is an 8-bit processor, it also has some 16-bit operations. Any of

the three 16-bit register pairs (BC, DE, HL) or SP could be loaded with an


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immediate 16-bit value (using LXI), incremented or decremented (using INX and

DCX), or added to HL (using DAD). LHLD loaded HL from directly-addressed

memory and SHLD stored HL likewise. The XCHG operation exchanges the

values of HL and DE. Adding HL to itself performs a 16-bit arithmetical left shift

with one instruction. The only 16 bit instruction that affects any flag was DAD(adding HL to BC, DE, HL or SP), which updates the carry flag to facilitate 24-bit

or larger additions and left shifts (for a floating point mantissa for instance).

Adding the stack pointer to HL is useful for indexing variables in (recursive) stack

frames. A stack frame can be allocated using DAD SP and SPHL, and a branch to

a computed pointer can be done with PCHL. These abilities make it feasible to

compile languages such as PL/M, Pascal, or C with 16-bit variables and produce

8085 machine code.

Subtraction and bitwise logical operations on 16 bits is done in 8-bit steps.Operations that have to be implemented by program code (subroutine libraries)

included comparisons of signed integers as well as multiply and divide.

Input/output scheme

The 8085 supported up to 256 input/output (I/O) ports, accessed via dedicated I/O

instructionstaking port addresses as operands. This I/O mapping scheme was

regarded as an advantage, as it freed up the processor's limited address space.

Development system

Intel produced a series of development systems for the 8080 and 8085, known as

the MDS-80 Microprocessor System. The original development system had an

8080 processor. Later 8085 and 8086 support was added including ICE (in-circuit

emulators). It was a large and heavy desktop box, about a 20" cube (in the Intel

corporate blue colour) which included a CPU, monitor, and a single 8 inch floppy

disk drive. Later an external box was available with two more floppy drives. It ran

the ISIS operating system and could also operate an emulator pod and an external

EPROM programmer. This unit used the Multibus card cage which was intended

just for the development system. A surprising number of spare card cages and

processors were being sold, leading to the development of the Multibus as a

separate product.


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The later iPDS was a portable unit, about 8" x 16" x 20", with a handle. It had a

small green screen, a keyboard built into the top, a 5 inch floppy disk drive, and

ran the ISIS-II operating system. It could also accept a second 8085 processor,

allowing a limited form of multi-processor operation where both processors ran

simultaneously and independently. The screen and keyboard could be switchedbetween them, allowing programs to be assembled on one processor (large

programs took awhile) while files were edited in the other. It had a bubble

memory option and various programming modules, including EPROM and Intel

8048 and 8051 programming modules which were plugged into the side, replacing

stand-alone device programmers. In addition to an 8080/8085 assembler, Intel

produced a number of compilers including PL/M-80 and Pascal languages, and a

set of tools for linking and statically locating programs to enable them to be burnt

into EPROMs and used in embedded systems. The hardware support changes were

announced and supported, but the software upgrades were not supported by theassembler, user manual or any other means. At times it was claimed they were not

tested when that was false

Applications

For the extensive use of 8085 in various applications, the microprocessor is

provided with an instruction set which consists of various instructions such as

MOV, ADD, SUB, JMP etc. These instructions are written in the form of a

program which is used to perform various operations such as branching, addition,

subtraction, bitwise logical and bit shift operations. More complex operations and

other arithmetic operations must be implemented in software. For example,

multiplication is implemented using a multiplication algorithm.

The 8085 processor was used in a few early personal computers, for example, the

TRS-80 Model 100 line uses a 80C85. The CMOS version 80C85 of the

NMOS/HMOS 8085 processor has several manufacturers. Some maufacturers

provide variants with additional functions such as additional instructions.[citation

needed]The rad-hard version of the 8085 has been in on-board instrument data

processors for several NASA and ESA space physics missions in the 1990s and

early 2000s, including CRRES, Polar, FAST, Cluster, HESSI, the Sojourner Mars

Rover,[2]

and THEMIS. The Swiss company SAIA used the 8085 and the 8085-2

as the CPUs of their PCA1 line of programmable logic controllers during the

1980s.


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Registers

Accumulator or A register is an 8-bit register used for arithmetic, logic,I/O and load/store operations.

Flag is an 8-bit register containing 5 1-bit flags: Sign - set if the most significant bit of the result is set. Zero - set if the result is zero. Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the

result.

Parity - set if the parity (the number of set bits in the result) is even. Carry - set if there was a carry during addition, or borrow during

subtraction/comparison.

Stack pointer is a 16 bit register., it points to a memory location in R/Wmemory canned the stack. The beginning of stack is defined by loading the16 bit address in the stack pointer.

Program counter is a 16-bit register, it points to the memory address fromwhich the next byte is to be fetched, when the next byte is fetched the

counter is incremented by one and point to next location.

General registers:

8-bit B and 8-bit C registers can be used as one 16-bit BC registerpair. When used as a pair the C register contains low-order byte.Some instructions may use BC register as a data pointer.

8-bit D and 8-bit E registers can be used as one 16-bit DE registerpair. When used as a pair the E register contains low-order byte.

Some instructions may use DE register as a data pointer.

8-bit H and 8-bit L registers can be used as one 16-bit HL registerpair. When used as a pair the L register contains low-order byte. HL

register usually contains a data pointer used to reference memory

addresses.

Memory

Program, data and stack memories occupy the same memory space. Thetotal addressable memory size is 64 KB.

Program memory - program can be located anywhere in memory. Jump,branch and call instructions use 16-bit addresses.


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Data memory - the processor always uses 16-bit addresses so that data canbe placed anywhere.

Stack memory is limited only by the size of memory. Stack grows downward

Interrupts

The processor has 5 interrupts. They are presented below in the order of their

priority (from lowest to highest):

1. INTR is maskable 8080A compatible interrupt. When the interrupt occursthe processor fetches from the bus one instruction, usually one of these

instructions:

2. RST5.5 is a maskable interrupt. When this interrupt is received theprocessor saves the contents of the PC register into stack and branches to2Ch (hexadecimal) address.

3. RST6.5 is a maskable interrupt. When this interrupt is received theprocessor saves the contents of the PC register into stack and branches to

34h (hexadecimal) address.


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4. RST7.5 is a maskable interrupt. When this interrupt is received theprocessor saves the contents of the PC register into stack and branches to

3Ch (hexadecimal) address.

5. Trap is a non-maskable interrupt. When this interrupt is received theprocessor saves the contents of the PC register into stack and branches to24h (hexadecimal) address.

I/O ports

256 Input ports

256 Output ports


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Dynamic Random Access Memory (DRAM)

DRAM stores each bit in a storage cell consisting of a capacitor and a

transistor. Capacitors tend to lose their charge rather quickly; thus, the need for

recharging. The presence or absence of charge in the capacitor determines whetherthe cell contains a '1' or a '0'. The Read operation begins by precharging the bit

line to an intermediate value, . The word line is raised to a high potential and the

charge stored on capacitor is shared with that on the bit line. The change in the bit

line voltage is given by the change on the bit line capacitor when the charge stored

on capacitor C is shared with the bit line. Based on the access pattern, RWMs are

classified as random access class and serial memories. FIFO (first-in-first-out) is

an example for serial memories. Most memories belong to the random access

class, which means memory locations can be read or written in random

order. One would expect memories of this class to be called RAM (random accessmemory); nevertheless for historic reasons, RAM has been reserved for random

access RWM memories. That means though most ROM units also provide random

access, but the acronym RAM should not be used for them.

VOLATILE MEMORIES :

Static Random Access Memory (SRAM) and Dynamic Random Access

Memory (DRAM) are volatile memories. SRAM is used as a cache memory in

computers since it offers the fastest write/read (~8ns) speed among all memories.Hardware design of a single SRAM cell consists of 6 transistors. A DRAM cell

consists of one transistor and one capacitor and it is based on the charge stored in a

capacitor. It is superior to SRAM because of its low cost per bit storage;

nevertheless it is slower (`50ns). In DRAM, the stored charge in the capacitor can

be maintained only for few milli-seconds and therefore, an extra hardware circuit

is needed to periodically refresh the data periodically.

NON-VOLATILE MEMORIES:

Based on the programmability of the devices non-volatile memories are

categorized as follows. Writing data into ROMs is possible only at the time of

manufacturing the devices and used only for reading the data stored. Even though

these devices are less in cost the constraint that they are to be programmed at the

time of manufacturing is an inconvenience. PROM devices are one time


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programmable ROM. At the time of device manufacturing every cell is stored with

"1" and can be programmed by customer once. But, single write phase makes them

unattractive. For instance, a single error in the programming process or application

makes the device unusable. EPROM is Erasable PROM. Multiple times

programming feature is added in EPROM. In this case, first whole memory is tobe erased by shining ultraviolet light. The erase process is slow and can take from

seconds to several minutes, depending on the intensity of the UV source.

Programming takes several (5-10) /word. EPROM cell is extremely simple and

dense, making it possible to fabricate large memories at a low cost. EPROMs were

therefore attractive in applications that not require frequent programming.

Electrically-Erasable PROM (EEPROM) can be erased without removing from

board, unlike in UV erasable where memory must be removed from the board. The

voltage approximately applied for programming is 18V. In addition, it is a reverse

process; means by applying high negative voltage at gate can erase the cell.Another advantage over EPROM is that EEPROM can be programmed for 105

cycles.

DIGITAL ELECTRONICS

Advantages

The usual advantages of digital circuits when compared to analog circuits

are:

Digital systems interface well with computers and are easy to control with software.

New features can often be added to a digital system without changing hardware. Often

this can be done outside of the factory by updating the product's software. So, the

product's design errors can be corrected after the product is in a customer's hands.

Information storage can be easier in digital systems than in analog ones. The noise-

immunity of digital systems permits data to be stored and retrieved without degradation.

In an analog system, noise from aging and wear degrade the information stored.

In a digital system, as long as the total noise is below a certain level, the

information can be recovered perfectly.

Robustness

One of the primary advantages of digital electronics is its robustness. Digital

electronics are robust because if the noise is less than the noise margin then the


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system performs as if there were no noise at all. Therefore, digital signals can be

regenerated to achieve lossless data transmission, within certain limits.

Analog signal transmission and processing, by contrast, always introduces

noise.

Disadvantages

In some cases, digital circuits use more energy than analog circuits to

accomplish the same tasks, thus producing more heat as well. In portable or

battery-powered systems this can limit use of digital systems.

For example, battery-powered cellular telephones often use a low-power

analog front-end to amplify and tune in the radio signals from the base station.

However, a base station has grid power and can use power-hungry, but very

flexible software radios. Such base stations can be easily reprogrammed to process

the signals used in new cellular standards.

Digital circuits are sometimes more expensive, especially in small

quantities.

The sensed world is analog, and signals from this world are analog

quantities. For example, light, temperature, sound, electrical conductivity, electric

and magnetic fields are analog. Most useful digital systems must translate from

continuous analog signals to discrete digital signals. This causes quantization

errors.

Quantization error can be reduced if the system stores enough digital data to

represent the signal to the desired degree of fidelity. The Nyquist-Shannon

sampling theorem provides an important guideline as to how much digital data is

needed to accurately portray a given analog signal.


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Even though the decimal system has only 10 symbols, any number of any

magnitude can be expressed by using our system of positional weighting.

Decimal Examples .1410 5210 102410

Numbering System

Many number systems are in use in digital technology. The most common are the

decimal, binary, octal, and hexadecimal systems. The decimal system is clearly the

most familiar to us because it is a tool that we use every day. Examining some of itscharacteristics will help us to better understand the other systems. In the next few

pages we shall introduce four numerical representation systems that are used in the

digital system. There are other systems, which we will look at briefly.

Decimal Binary Octal Hexadecimal

Decimal System

system is composed of 10 numerals or symbols. These 10 symbols are 0, 1, 2,

8, 9. Using these symbols as digits of a number, we can express any quantity. The

m is also called the base-10 system because it has 10 digits.

103 10

2 10

1 10

0 10

-1 10

-2 10

-3

=1000 =100 =10 =1 . =0.1 =0.01 =0.001

Most Significan

DigitDecimal point

Least

Significan

Digit


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Representing Binary Quantities

In digital systems the information that is being processed is usually presented in

binary form. Binary quantities can be represented by any device that has only two

operating states or possible conditions.

E.g.. a switch is only open or closed. We arbitrarily (as we define them) let an open

switch represent binary 0 and a closed switch represent binary 1. Thus we can

represent any binary number by using series of switches.

Typical Voltage Assignment

Binary 1: Any voltage between 2V to 5V

Binary 0: Any voltage between 0V to 0.8V

Not used: Voltage between 0.8V to 2V in 5 Volt CMOS and TTL Logic, this may

cause error in a digital circuit. Today's digital circuits works at 1.8 volts, so thisstatement may not hold true for all logic circuits.


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Octal System

The octal number system has a base of eight, meaning that it has eight possible digits: 0,1,2,3,4,5

83 82 81 80 8-1 8-2 8-3

=512 =64 =8 =1 . =1/8 =1/64 =1/512

Most Significant Digit Octal point

Least

Significan

Digit

Octal to Decimal Conversion

2378 = 2 x (82) + 3 x (81) + 7 x (80) = 15910 24.68 = 2 x (81) + 4 x (80) + 6 x (8-1) = 20.7510 11.18 = 1 x (81) + 1 x (80) + 1 x (8-1) = 9.12510 12.38 = 1 x (81) + 2 x (80) + 3 x (8-1) = 10.37510

Hexadecimal System

The hexadecimal system uses base 16. Thus, it has 16 possible digit symbols. It uses the digits 0

through 9 plus the letters A, B, C, D, E, and F as the 16 digit symbols.

163 16

2 16

1 16

0 16

-1 16

-2 16

-3

=4096 =256 =16 =1 . =1/16 =1/256 =1/4096

Most Significant DigitHexa Decimal

point

Least

Significant

Digit

Hexadecimal to Decimal Conversion

24.616 = 2 x (161) + 4 x (16

0) + 6 x (16

-1) = 36.37510

11.116 = 1 x (161) + 1 x (160) + 1 x (16-1) = 17.062510 12.316 = 1 x (161) + 2 x (160) + 3 x (16-1) = 18.187510


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Code Conversion

Converting from one code form to another code form is called code conversion

like converting from binary to decimal or converting from

Binary-To-Decimal Conversion

Any binary number can be converted to its decimal equivalent simply b

summing together the weights of the various positions in the binary numbe

which contain a 1.

Binary Decimal

110112

24+2

3+0

1+2

1+2

0=16+8+0+2+1

Result 2710

Binary Decimal

101101012

27+0

6+2

5+2

4+0

3+2

2+0

1+2

0=128+0+32+16+0+4+0+1

Result 18110

You should have noticed that the method is to find the weights (i.e., powers o

2) for each bit position that contains a 1, and then to add them up.


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Decimal-To-Binary Conversion

There are 2 methods:

Reverse of Binary-To-Decimal Method Repeat Division

Reverse of Binary-To-Decimal Method

Decimal Binary

4510 =32 + 0 + 8 + 4 +0 + 1

=25+0+2

3+2

2+0+2

0

Result =1011012

Repeat Division-Convert decimal to binary

This method uses repeated division by 2.

Convert 2510 to binary

Division Remainder Binary

25/2 = 12+ remainder of 1 1 (Least Significant Bit)

12/2 = 6 + remainder of 0 0



1/2 = 0 + remainder of 1 1 (Most Significant Bit)

Result 2510 = 110012


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Binary-To-Octal / Octal-To-Binary Conversion

Octal Digit 0 1 2 3 4 5 6 7

Binary

Equivalent000 001 010 011 100 101 110 111

Each Octal digit is represented by three binary digits.

Example:

100 111 0102 = (100) (111) (010)2 = 4 7 28

Repeat Division-Convert decimal to octal

This method uses repeated division by 8.

Example: Convert 17710 to octal and binary

Division Result Binary

177/8 = 22+ remainder of 1 1 (Least Significant Bit)

22/ 8 = 2 + remainder of 6 6

2 / 8 = 0 + remainder of 2 2 (Most Significant Bit)

Result 17710 = 2618

Binary = 0101100012


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Convert 5A816 to Octal.

Hexadecimal Binary/Octal

5A816 = 0101 1010 1000 (Binary)

= 010 110 101 000 (Binary)Result = 2 6 5 0 (Octal)


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Binary Codes

Binary codes are codes which are represented in binary system with modification

from the original ones. Below we will be seeing the following:

Weighted Binary Systems Non Weighted Codes

Weighted Binary Systems

Weighted binary codes are those which obey the positional weighting principles,

each position of the number represents a specific weight. The binary counting

sequence is an example.

Decimal 8421 2421 5211 Excess-3

0 0000 0000 0000 0011

1 0001 0001 0001 0100

2 0010 0010 0011 0101

3 0011 0011 0101 0110

4 0100 0100 0111 0111

5 0101 1011 1000 1000

6 0110 1100 1010 1001

7 0111 1101 1100 1010

8 1000 1110 1110 10119 1001 1111 1111 1100

8421 Code/BCD Code

The BCD (Binary Coded Decimal) is a straight assignment of the binary equivalent. It is

possible to assign weights to the binary bits according to their positions. The weights in the

BCD code are 8,4,2,1.

Example: The bit assignment 1001, can be seen by its weights to represent the decimal 9

because:

1x8+0x4+0x2+1x1 = 9


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2421 Code

This is a weighted code, its weights are 2, 4, 2 and 1. A decimal number is represented in 4-bit

form and the total four bits weight is 2 + 4 + 2 + 1 = 9. Hence the 2421 code represents the

decimal numbers from 0 to 9.

5211 Code

This is a weighted code, its weights are 5, 2, 1 and 1. A decimal number is represented in 4-bit

form and the total four bits weight is 5 + 2 + 1 + 1 = 9. Hence the 5211 code represents the

decimal numbers from 0 to 9.

Reflective Code

A code is said to be reflective when code for 9 is complement for the code for 0, and so is for 8

and 1 codes, 7 and 2, 6 and 3, 5 and 4. Codes 2421, 5211, and excess-3 are reflective, whereas

the 8421 code is not.

Sequential Codes

A code is said to be sequential when two subsequent codes, seen as numbers in binary

representation, differ by one. This greatly aids mathematical manipulation of data. The 8421

and Excess-3 codes are sequential, whereas the 2421 and 5211 codes are not.

Non Weighted Codes

Non weighted codes are codes that are not positionally weighted. That is, each position within

the binary number is not assigned a fixed value.

Excess-3 Code

Excess-3 is a non weighted code used to express decimal numbers. The code derives its name

from the fact that each binary code is the corresponding 8421 code plus 0011(3).

Example: 1000 of 8421 = 1011 in Excess-3

Gray Code

The gray code belongs to a class of codes called minimum change codes, in which only one bit

in the code changes when moving from one code to the next. The Gray code is non-weighted


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code, as the position of bit does not contain any weight. The gray code is a reflective digital

code which has the special property that any two subsequent numbers codes differ by only one

bit. This is also called a unit-distance code. In digital Gray code has got a special place.

Decimal Number Binary Code Gray Code

0 0000 0000

1 0001 0001

2 0010 0011

3 0011 0010

4 0100 0110

5 0101 0111

6 0110 0101

7 0111 0100

8 1000 1100

9 1001 1101

10 1010 1111

11 1011 1110

12 1100 1010

13 1101 1011

14 1110 1001

15 1111 1000


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Binary to Gray Conversion

Gray Code MSB is binary code MSB. Gray Code MSB-1 is the XOR of binary code MSB and MSB-1. MSB-2 bit of gray code is XOR of MSB-1 and MSB-2 bit of binary code. MSB-N bit of gray code is XOR of MSB-N-1 and MSB-N bit of binary code.

Error Detecting and Correction Codes

For reliable transmission and storage of digital data, error detection and correction i

required. Below are a few examples of codes which permit error detection and erro

correction after detection.

Error Detecting CodesWhen data is transmitted from one point to another, like in wireless transmission, or it i

just stored, like in hard disks and memories, there are chances that data may get corrupted

To detect these data errors, we use special codes, which are error detection codes.

Parity

In parity codes, every data byte, or nibble (according to how user wants to use it) is checke

if they have even number of ones or even number of zeros. Based on this information a

additional bit is appended to the original data. Thus if we consider 8-bit data, adding th

parity bit will make it 9 bit long.

At the receiver side, once again parity is calculated and matched with the received parit

(bit 9), and if they match, data is ok, otherwise data is corrupt.

There are two types of parity:

Even parity: Checks if there is an even number of ones; if so, parity bit is zeroWhen the number of ones is odd then parity bit is set to 1.

Odd Parity: Checks if there is an odd number of ones; if so, parity bit is zero. Whenumber of ones is even then parity bit is set to 1.


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Counters in electronics

Toggle flip-flop. Output is not shown. Red=1, blue=0

In electronics, counters can be implemented quite easily using register-type circuits such

as the flip-flop, and a wide variety of designs exist, e.g:

Asynchronous (ripple) counters

Synchronous counters

Johnson counters

Decade counters

Up-Down counters

Ring counters

Each is useful for different applications. Usually, counter circuits are digital in nature,

and count in binary, or sometimes binary coded decimal. Many types of counter circuit

are available as digital building blocks, for example a number of chips in the 4000 series

implement different counters.

Asynchronous (ripple) counters


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Asynchronous Counter created from JK flip-flops.

The simplest counter circuit is a single D-type flip flop, with its D (data) input fed from

its own inverted output. This circuit can store one bit, and hence can count from zero to

one before it overflows (starts over from 0). This counter will increment once for every

clock cycle and takes two clock cycles to overflow, so every cycle it will alternatebetween a transition from 0 to 1 and a transition from 1 to 0. Notice that this creates a

new clock with a 50% duty cycle at exactly half the frequency of the input clock. If this

output is then used as the clock signal for a similarly arranged D flip flop (remembering

to invert the output to the input), you will get another 1 bit counter that counts half as

fast. Putting them together yields a two bit counter:

cycle Q1 Q

0

(Q1:Q0)dec

0 0 0 0

1 0 1 1

2 1 0 2

3 1 1 3

4 0 0 0

You can continue to add additional flip flops, always inverting the output to its own

input, and using the output from the previous flip flop as the clock signal. The result is

called a ripple counter, which can count to 2n-1 where n is the number of bits (flip flop

stages) in the counter. Ripple counters suffer from unstable outputs as the overflows

"ripple" from stage to stage, but they do find frequent application as dividers for clock

signals, where the instantaneous count is unimportant, but the division ratio overall is.

(To clarify this, a 1-bit counter is exactly equivalent to a divide by two circuit - the

output frequency is exactly half that of the input when fed with a regular train of clock

pulses).

Up-Down Counters

It is a combination of up counter and down counter, counting in straight binary

sequence. There is an up-down selector. If this value is kept high, counter

increments binary value and if the value is low, then counter starts decrementing the

count. The Down counters are made by using the complemented output to act as theclock for the next flip-flop in the case of Asynchronous counters. An Up counter is

constructed by linking the Q out of the J-K Flip flop and putting it into a Negative

Edge Triggered Clock input. A Down Counter is constructed by taking the Q output

and putting it into a Positive Edge Triggered inpu


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