Avalon-MM DMA FIFO Example Design User Guide - Intel …€¦ ·  · 2018-05-162014.12.15. UG-01159 Subscribe ... (Avalon-MM) DMA FIFO Example Design provides a FIFO interface to

Avalon-MM DMA FIFO Introduction2014.12.15.

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The Avalon® Memory-Mapped (Avalon-MM) DMA FIFO Example Design provides a FIFO interface to the Data Mover in the V-Series Avalon-MM DMA for PCI Express® IP core. This component is part of a system design that includes a custom, third-party, external descriptor controller. It is available for the V-Series Avalon-MM DMA for PCI Express IP core with a 256-bit interface to the Application Layer.

The DMA FIFO passes the descriptors it receives to the Data Mover requires. The DMA FIFO drivescompletion packets to the DMA Controller on its Avalon-ST source interface. An internal 4 kilobyte (KB)reordering buffer for each descriptor ensures that read completion data is assembled in the correct order.Each

Figure 1: DMA FIFO Example Design System-Level Block Diagram

This figure uses the following abbreviations:

• Src—Avalon-ST source interface• Sink—Avalon-ST sink interface• Mstr—Avalon-MM master interface• Slave—Avalon-MM slave interface

Avalon-MMDMA Data

Mover

PCIeHard IPG3X8

Avalon Streaming256 bits PCIe TLP

DMAController

DMA FIFO

Avalon-MM DMA for PCI Express

Sink

Sink

Src

Slave Mstr

MstrSlave

Src

Src

Sink Src SinkRd & Wr Descriptors

DMA Write Data

DMA Read DataDMA Read Data

DMA Write Data

Sink SrcCompletion Status

Rd & Wr Descriptors

Completion Status

Sink

Src

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Preliminary

The DMA FIFO supports the following operations:

• Accepts up to four read descriptors• Transfers write descriptors that write up to 512 KB of data per descriptor• Transfers read descriptors that read up to 4 KB of data per descriptor• Drives completion status on the Avalon-ST completion status interface

Note: The DMA FIFO Example Design is preliminary in the Quartus II 14.1 release. Both the program‐ming model and top-level signals may change in subsequent releases.

Device Family Support

Table 1: Device Family Support

Device Family Support

Stratix V Final. The IP core is verified with final timingmodels. The IP core meets all functional and timingrequirements for the device family and can be usedin production designs.

Other device families No support.

DMA FIFO Parameters

The DMA FIFO has no parameters.

DMA FIFO InterfacesThe DMA FIFO connection to a DMA controller comprises six Avalon-ST interfaces to transfer read andwrite descriptors, data, and status. The DMA FIFO connection to the Data Mover also comprises sixinterfaces. Four Avalon-ST interfaces transfer read and write descriptors and status. Two Avalon-MMinterfaces transfer DMA data.

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Preliminary

Figure 2: DMA FIFO Top-Level Interfaces

ast_wr_fifo_desc_rx_data_i[159:0]ast_wr_fifo_desc_rx_valid_iast_wr_fifo_desc_rx_ready_o

ast_rd_fifo_desc_rx_data_i[159:0]ast_rd_fifo_desc_rx_valid_iast_rd_fifo_desc_rx_ready_o

ast_wr_fifo_data_rx_data_i[255:0]ast_wr_fifo_data_rx_valid_iast_wr_fifo_data_rx_ready_o

ast_rd_fifo_data_tx_ready_i

ast_rd_fifo_data_tx_data_w_dword_valid_o[263:0]ast_rd_fifo_data_tx_valid_o

ast_wr_dma_desc_rx_data_i[31:0]ast_wr_dma_desc_rx_valid_i

ast_rd_dma_desc_rx_data_i[31:0]ast_rd_dma_desc_rx_valid_i

clk_irstn_i

ast_wr_dma_desc_tx_data_o[159:0]

ast_wr_dma_desc_tx_ready_iast_wr_dma_desc_tx_valid_o

ast_rd_dma_desc_tx_data_o[159:0]ast_rd_dma_desc_tx_valid_oast_rd_dma_desc_tx_ready_i

avmm_wr_dma_slave_read_iavmm_wr_dma_slave_address_i[63:0]

avmm_wr_dma_slave_burst_count_i[4:0]avmm_wr_dma_slave_chip_select_i

avmm_wr_dma_slave_wait_request_oavmm_wr_dma_slave_read_data_valid_o

avmm_wr_dma_slave_read_data_o[255:0]

avmm_rd_dma_slave_write_iavmm_rd_dma_slave_address_i[63:0]

avmm_rd_dma_slave_write_data_i[255:0]avmm_rd_dma_slave_chip_select_i

avmm_rd_dma_slave_wait_request_oavmm_rd_dma_slave_burst_count_i[4:0]

avmm_rd_dma_slave_byte_enable_i[31:0]

ast_wr_fifo_ctrl_tx_desc_status_data_o[31:0]ast_wr_fifo_ctrl_tx_desc_status_valid_o

ast_rd_fifo_ctrl_tx_data_cpl_ctrl_o[31:0]ast_rd_fifo_ctrl_tx_valid_cpl_ctrl_o

DMA FIFO

Avalon-MM WriteDMA Slave

Avalon-MM ReadDMA Slave

Avalon-ST WriteFIFO Data RX

Avalon-ST WriteFIFO Descriptor RX

Avalon-ST ReadFIFO Descriptor RX

Avalon-ST WriteDMA Descriptor TX

Avalon-ST ReadDMA Descriptor TX

Avalon-ST WriteFIFO Status TX

Avalon-ST ReadFIFO Status TX

Avalon-ST ReadFIFO Data TX

Avalon-ST WriteDMA Descriptor RX

Status

Avalon-ST ReadDMA Descriptor RX

Status

Avalon-ST Write and Read FIFO DescriptorsThe DMA FIFO receives write and read FIFO descriptors from the DMA controller on its Avalon-ST sinkinterfaces. The DMA FIFO transmits the descriptors to the Data Mover on its Avalon-ST sourceinterfaces. All interfaces are synchronous to the input clock, clk_i.

Table 2: Avalon-ST Write FIFO Descriptor RX

Signal Name Direction Definition

ast_wr_fifo_desc_rx_data_

i[159:0]

Input Specifies the write descriptor data. Refer Table 6 DMADescriptor Format for the format of this data.

ast_wr_fifo_desc_rx_valid_i Input When asserted, ast_wr_fifo_desc_rx_data_i[159:0]is valid. Readt latency on this interface is 0 cycles. TheDMA FIFO stores data on the rising edge of clk_i whenboth ast_wr_fifo_desc_rx_valid_i and ast_wr_fifo_desc_rx_ready_o are asserted.

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Signal Name Direction Definition

ast_wr_fifo_desc_rx_ready_o Output When asserted, the FIFO can accept the write descriptordata. The ready latency is 0 cycles. Consequently, theDMA FIFO stores data on the rising edge of clk_i whenboth the ast_wr_fifo_desc_rx_valid_i and ast_wr_fifo_desc_rx_read_o are asserted.

Table 3: Avalon-ST Read FIFO Descriptor RX

Signal Name Direction Definition

ast_rd_fifo_desc_rx_data_

i[159:0]

Input Specifies the read descriptor data. Refer to Table 6 DMADescriptor Format for the format of this data.

ast_rd_fifo_desc_rx_valid_i Input When asserted, ast_rd_fifo_desc_rx_data_i[159:0]is valid. Ready latency on this interface is 0 cycles. TheDMA FIFO stores data on the rising edge of clk_i whenboth ast_rd_fifo_desc_rx_valid_i and ast_rd_fifo_desc_rx_ready_o are asserted.

ast_rd_fifo_desc_rx_ready_o Output When asserted, the FIFO stores the read descriptor data.The ready latency is 0 cycles. The DMA FIFO stores dataon the rising edge of clk_i whenever both the ast_rd_fifo_desc_rx_valid_i and ast_rd_fifo_desc_rx_ready_o are asserted.

Table 4: Avalon-ST Write DMA Descriptor TX

Signal Name Direction Definition

ast_wr_dma_desc_tx_data_

o[159:0]

Output Specifies the write descriptor data. Refer Table 6 DMADescriptor Format for the format of this data.

ast_wr_dma_desc_tx_valid_o Output When asserted, ast_wr_dma_desc_tx_data_o[159:0]is valid.

ast_wr_dma_desc_tx_ready_i Input When asserted, the Data Mover stores the writedescriptor data. The ready latency is 3 cycles.Consequently, the DMA FIFO transmits valid data 3cycles after ast_wr_dma_desc_tx_ready_i is asserted.

Table 5: Avalon-ST Read DMA Descriptor TX

Signal Name Direction Definition

ast_rd_dma_desc_tx_data_

o[159:0]

Input Specifies the read descriptor data. Refer Table 6 DMADescriptor Format for the format of this data.

ast_rd_dma_desc_tx_valid_o Input When asserted, ast_rd_dma_desc_tx_data_o[159:0]is valid.

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Signal Name Direction Definition

ast_rd_dma_desc_tx_ready_i Output When asserted, the Data Mover stores the readdescriptor data. The ready latency is 3 cycles.Consequently, the DMA FIFO transmits valid data 3cycles after ast_rd_dma_desc_tx_ready_i is asserted.

Table 6: DMA Descriptor Format

Bits Name Description

[31:0] Source Low Address Low-order 32 bits of the DMA source address. The addressboundary must align to the 32 bits so that the 2 least signifi‐cant bits are 2'b00. For reads, the source address is the PCIedomain address. For writes, this is the Avalon-MM domainaddress as seen by the Data Mover.

Refer to Figure 1 DMA FIFO Example Design System-LevelBlock Diagram.

[63:32] Source High Address High-order 32 bits of the source address.

[95:64] Destination Low Address Low-order 32 bits of the DMA destination address. Theaddress boundary must align to 32 bits so that the 2 leastsignificant bits have the value of 2'b00. For reads, thedestination address is the Avalon-MM domain address asseen by the Data Mover Avalon-MM read master to theDMA FIFO Avalon-MM read slave . For writes, the destina‐tion address is the PCIe domain address.

Refer to Figure 1 DMA FIFO Example Design System-LevelBlock Diagram.

[127:96] Destination High

AddressHigh-order 32 bits of the destination address.

[145:128] DMA Length Specifies data length in dwords. The length must be greaterthan 0. The maximum length for write data is 512 KB. Themaximum length for read data in 8 KB.

[153:146] DMA Descriptor ID Specifies the descriptor ID. The DMA FIFO can process upto 4 outstanding descriptors.

[159:154] Reserved N/A

DMA Write and Read OperationThe DMA FIFO receives write FIFO data on its Avalon-ST sink interface. The Data Mover Avalon-MMmaster interface reads this data from the FIFO's Avalon-MM Write DMA Slave interface using the sourceaddress specified in ast_wr_dma_desc_tx_data_o.

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Table 7: Avalon-ST Write FIFO Data RX

Signal Name Direction Definition

ast_wr_dma_fifo_data_rx_

data[255:0]

Input The DMA FIFO receives data on this bus.

avst_wr_fifo_data_rx_valid_i Input Asserted when the ast_wr_dma_fifo_data_rx_data[255:0] is valid. The ready latency on this interfaceis 0 cycles. The DMA FIFO stores data on the risingedge of clock when ast_wr_fifo_data_rx_ready_oand avst_wr_fifo_data_rx_valid_i are both asserted.

ast_wr_fifo_data_rx_ready_o Output Asserted when the DMA FIFO write queue can acceptwrite data.

Table 8: Avalon-MM Write DMA Slave

Signal Name Direction Definition

avmm_wr_dma_slave_read_i Input The Data Mover asserts avmm_wr_dma_slave_read_i toread data from the DMA FIFO. It transmits this data tothe source address specified in the write descriptor.

avmm_wr_dma_slave_address_

i[63:0]

Input The Data Mover specifies avmm_wr_dma_slave_address_i[63:0]. This is the address offset of the DMAFIFO's write FIFO in the Avalon address domain.

avmm_wr_dma_slave_burst_

count_i[4:0]

Input Specifies the size of the burst per write operation. DMAFIFO supports a write of up to 512 Kbytes.

avmm_wr_dma_slave_chip_

select_i[4:0]

Input When asserted, the Data Mover is accessing the Avalon-MM Write DMA Slave interface.

avmm_wr_dma_slave_wait_

request_o

Output When asserted, this slave interface is not ready torespond. If the Data Mover is accessing this interface, itmust hold the signals constant until avmm_wr_dma_slave_wait_request_o deasserts.

avmm_wr_dma_slave_read_data_

valid_o

Output When asserted, avmm_wr_dma_slave_read_data_o[255:0] is valid.

avmm_wr_dma_slave_read_data_

o[255:0]

Output Drives FIFO data to the Data Mover.

Table 9: Avalon-ST Read FIFO Data TX

Signal Name Direction Definition

ast_rd_dma_fifo_data_tx_

data_w_dword_valid_o[263:0]

Output The DMA FIFO drives data on this bus.The low-order 8bits specify valid dwords. The DMA Controller can useast_rd_dma_fifo_data_tx_data_w_dword_valid_

o[7:0] to align data based of the first and last validdwords of the 256-bit data.

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Signal Name Direction Definition

ast_rd_fifo_data_tx_valid_o Output Asserted when the ast_rd_dma_fifo_data_tx_data_w_dword_valid_o[263:0] is valid. The ready latency onthis interface is 0 cycles. The DMA FIFO stores data onthe rising edge clk_i when ast_rd_fifo_data_tx_ready_i and ast_rd_dma_fifo_data_tx_data_w_dword_valid_o[263:0] are both asserted.

ast_rd_fifo_data_tx_ready_i Input Asserted when the DMA Controller can accept readdata.

Table 10: Avalon-MM Read DMA Slave

The DMA FIFO receives read data from the Data Mover on its Avalon-MM slave read interface. It drives this datato the DMA Controller on its DMA read Avalon-ST source interface.

Signal Name Direction Definition

avmm_rd_dma_slave_write_i Input The Data Mover asserts avmm_rd_dma_slave_write_ito write data to the DMA FIFO.

avmm_rd_dma_slave_address_

i[63:0]

Input The Data Mover specifies avmm_rd_dma_slave_address_i[63:0]. This is the address offset of the DMAFIFO's read FIFO in the Avalon address domain.

avmm_rd_dma_slave_read_data_

o[255:0]

Input Receives data from the PCIe address domain.

avmm_rd_dma_slave_burst_

count_i[4:0]

Input Specifies the size of the read data.

avmm_rd_dma_slave_chip_

select_i[4:0]

Input When asserted, the Data Mover is accessing the Avalon-MM Read DMA Slave interface.

avmm_rd_dma_slave_wait_

request_o

Output When asserted, this DMA FIFO read data FIFO is full.The FIFO stores completion data for up to 4, 4 Kbyteread descriptors. Internal logic restores the correct orderfor out-of-order read completion data.

avmm_rd_dma_slave_read_

burst_count[4:0]

Input Specifies the size of the read burst count.

avmm_rd_dma_slave_byte_

enable[31:0]

Input Specifies the bytes of avmm_rd_dma_slave_read_data_o[255:0] that are valid.

Write DMA and Read DMA Completion StatusThe DMA FIFO receives the completion status from the Data Mover on the Descriptor RX Statusinterfaces. It drives this information to the DMA controller on the FIFO Status TX interfaces.

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Table 11: Avalon-ST Write FIFO Status TX

Signal Name Direction Definition

ast_wr_fifo_ctrl_tx_desc_

status_data_o[31:0]

Output Indicates the status for the descriptor ID specified. Thefollowing fields are defined:

• [31:9]: Reserved.• [8]: Done. When 1'b1, indicates successful completion

of when Descriptor ID when ast_wr_fifo_ctrl_tx_desc_status_valid_o is asserted.

• [7:0]: Descriptor ID.

ast_wr_fifo_ctrl_tx_desc_

status_valid_o

Output When asserted, the data on ast_wr_fifo_ctrl_tx_desc_status_data_o[31:0] is valid.

Table 12: Avalon-ST Read FIFO Status TX

Signal Name Direction Definition

ast_rd_fifo_ctrl_tx_cpl_

ctrl_o[31:0]

Output Indicates status of the descriptor ID specified. Thefollowing fields are defined:

• [31:9]: Reserved. Must be all 0s.• [8]: Done. When 1'b1, indicates successful completion

of Descriptor ID when ast_rd_fifo_ctrl_tx_valid_cpl_ctrl_o is asserted.

• [7:0]: Descriptor ID.

ast_rd_fifo_ctrl_tx_valid_

cpl_ctrl_o

Output When asserted, ast_rd_fifo_ctrl_tx_cpl_ctrl_o[31:0] is valid.

Table 13: Avalon-ST Write DMA Descriptor RX Status

Signal Name Direction Definition

ast_wr_dma_desc_rx_data_

i[31:0]

Input Specifies the status for the descriptor ID specified. Thefollowing fields are defined:

• [31:9]: Reserved. Must be all 0s.• [8]: Done. When 1'b1, indicates successful completion

of the Descriptor ID when ast_wr_dma_desc_rx_valid_i is asserted.

• [7:0]: Descriptor ID

ast_wr_dma_desc_rx_valid_i Input When asserted, the data on ast_wr_dma_desc_rx_data_i[31:0] is valid.

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Table 14: Avalon-ST Read DMA Descriptor RX Status

Signal Name Direction Definition

ast_rd_dma_desc_rx_data_

i[31:0]

Input Specifies the status for the descriptor ID specified. Thefollowing fields are defined:

• [31:9]: Reserved. Must be all 0s.• [8]: Done. When 1'b1, indicates successful completion

of the Descriptor ID when ast_rd_dma_desc_rx_valid_i is asserted.

• [7:0]: Descriptor ID.

ast_rd_dma_desc_rx_valid_i Input When asserted, the data on ast_rd_dma_desc_rx_data_i[31:0] is valid.

Clocks and Reset Interfaces

Table 15: Clock and Reset

Direction

clk_i Input Input clock. Connect the same clock source that drivesthe input clock of the Avalon-MM DMA for PCIExpress IP core. Its frequency is either 125 MHz or 250MHz.

rstn_i Input Active low reset signal. Connect the same reset signalthat drives the reset input of the Avalon-MM DMA forPCI Express IP core.

Revision HistoryDate Version Changes

2014.12.15 14.1 • Initial Release.

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Preliminary