Automatic synthesis and verification of asynchronous interface controllers Jordi Cortadella Universitat Politècnica de Catalunya, Spain Michael Kishinevsky Intel Corporation, USA Alex Kondratyev Theseus Logic, USA Luciano Lavagno Università di Udine, Italy Enric Pastor Universitat Politècnica de Catalunya, Spain Marco A. Peña Universitat Politècnica de Catalunya, Spain
75
Embed
Automatic synthesis and verification of asynchronous interface controllers Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Automatic synthesis and verification of asynchronous
interface controllers
Jordi Cortadella Universitat Politècnica de Catalunya, Spain
Michael Kishinevsky Intel Corporation, USA
Alex Kondratyev Theseus Logic, USA
Luciano Lavagno Università di Udine, Italy
Enric Pastor Universitat Politècnica de Catalunya, Spain
Marco A. Peña Universitat Politècnica de Catalunya, Spain
Alexander Yakovlev University of Newcastle upon Tyne, UK
y-
a+ b+
x+ y+
c+
c-
a-
b-
x-
x+ y-
y+x-
a
b
xy
c
Specification(environment)
Implementation(circuit)
Why and why not?
• Asynchronous circuits: robustness, modularity, less power consumption, low EMI, no clock skew and many other debatable advantages
• Designing correct async circuits is difficult(hazards, testing)
• Designing efficient async circuits is a nightmare (time comes into play)
• Design automation is crucial
How to make it asynchronous ?
Outline
• Synthesis flow with STGs– Specification– State graph and next-state functions– State encoding– Implementability conditions– Logic decomposition
• Synthesis with relative timing assumptions
• Formal verification of timed circuits
Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
VME bus
DeviceLDS
LDTACK
D
DSr
DSw
DTACK
VME BusController
DataTransceiver
BusDSr
LDS
LDTACK
D
DTACK
Read Cycle
STG for the READ cycle
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
LDS
LDTACK
D
DSr
DTACK
VME BusController
Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
Binary encoding of signals
DSr+
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDS-LDS-LDS-
LDTACK- LDTACK- LDTACK-
D-
DSr-DTACK+
D+
LDTACK+
LDS+
State graph
DSr+
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDS-LDS-LDS-
LDTACK- LDTACK- LDTACK-
D-
DSr-DTACK+
D+
LDTACK+
LDS+
10000
10010
10110 01110
01100
0011010110
(DSr , DTACK , LDTACK , LDS , D)
QR (LDS+)QR (LDS+)
QR (LDS-)QR (LDS-)
Excitation / Quiescent Regions
ER (LDS+)ER (LDS+)
ER (LDS-)ER (LDS-)
LDS-LDS-
LDS+
LDS-
Next-state function
0 1
LDS-LDS-
LDS+
LDS-
1 0
0 0
1 1
1011010110
Karnaugh map for LDS
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
LDS = 0 LDS = 1
0 1-0
0 0 0 0 0 0/1?
1
111
-
-
-
---
- - - -
-
- ---
- - -
Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
Concurrency reduction
LDS-LDS-
LDS+
LDS-
1011010110
DSr+
DSr+
DSr+
Concurrency reduction
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
State encoding conflicts
LDS-
LDTACK-
LDTACK+
LDS+
10110
10110
Signal Insertion
LDS-
LDTACK-
D-
DSr-
LDTACK+
LDS+
CSC-
CSC+
101101
101100
Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
Complex-gate implementation
)(csccsc
csc
csc
LDTACKDSr
LDTACKD
DDTACK
DLDS
Implementability conditions
• Consistency + CSC + persistency
• There exists a speed-independent circuit that implements the behavior of the STG
(under the assumption that ay Boolean function can be implemented with one complex gate)
Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
No Hazards
abc
x 0
abcx1000
1100
b+
0100
a-
0110
c+
1
1
0
0
1
1
0
1
0
1
0
0
Decomposition May Lead to Hazards
abcx1000
1100
b+
0100
a-
0110
c+
a
bz
cx
1
0
0
0
0
1000
11001100
0100
0110
1
1
0
0
0
1
1
1
0
0
0
1
1
0
0
0
1
1
1
1
0
1
0
1
0
y-
z- w-
y+ x+
z+
x-
w+
1001 1011
1000
1010
0001
0000 0101
0010 0100
0110 0111
0011
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
Decomposition example
yz=1yz=0
1001 1011
1000
1010
0001
0000 0101
0010 0100
0110 0111
0011
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
1001 1011
1000
1010
0001
0000 0101
0010 0100
0110 0111
0011
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
C
C
x
y
x
y
w
z
xyz
y
zw
z
w
z
y
s-
s+
s-
s-
s=1
s=0
1001 1011
1000
1010
0111
0011y+
x-
w+
z+
z-
0001
0000 0101
0010 0100
0110
x+
w-
w-
w-
z-
z-y+
y+
x+
x+
1001
1000
1010
y+
z-
0111
C
C
x
y
x
y
w
z
x
y
z
w
z
w
z
y
sy-
y-
z- w-
y+ x+
z+
x-
w+
s-
s+
s-
s+
s-
s-
s=1
s=0
1001 1011
1000
1010
0111
0011y+
x-
w+
z+
z-
0001
0000 0101
0010 0100
0110
x+
w-
w-
w-
z-
z-y+
y+
x+
x+
1001
1000
1010
y+
z-
0111
y-
Adding timing assumptions
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
DTACKD
DSr
LDS
LDTACK
csc
map
DTACKD
DSr
LDS
LDTACK
csc
map
DeviceLDS
LDTACK
D
DSr
DTACK
VME BusController
DataTransceiver
Bus
Adding timing assumptions
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
DTACKD
DSr
LDS
LDTACK
csc
map
LDTACK- before DSr+
FAST
SLOW
Adding timing assumptions
DTACKD
DSr
LDS
LDTACK
csc
map
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
LDTACK- before DSr+
State space domain
LDTACK- before DSr+
LDTACK-
DSr+
State space domain
LDTACK- before DSr+
LDTACK-
DSr+
State space domain
LDTACK- before DSr+
LDTACK-
DSr+
Two more unreachable states
Boolean domain
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
LDS = 0 LDS = 1
0 1-0
0 0 0 0 0 0/1?
1
111
-
-
-
---
- - - -
-
- ---
- - -
Boolean domain
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
LDS = 0 LDS = 1
0 1-0
0 0 - 0 0 1
1
111
-
-
-
---
- - - -
-
- ---
- - -
One more DC vector for all signals One state conflict is removed
Netlist with one timing constraint
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
DTACKD
DSr
LDS
LDTACK
csc
map
Netlist with one timing constraint
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
DTACK D
DSr LDS
LDTACK
LDTACK- before DSr+
TIMING CONSTRAINT
Types of timing assumptions
• Environment slower (or faster) than the circuit
• Gate delay shorter than another gate delay
• Speculative enabling (events enabled beforethey must actually occur)
• Indistiguishable firing times of different events
• . . .
Formal verification
• Implementability properties– Consistency, persistency, state coding …