Automatic symbolic analysis of switched-capacitor filtering networks using signal flow graphs

858 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 14, NO. I, JULY 1995

Automatic Symbolic Analysis of Switched-Capacitor Filtering Networks Using Signal Flow Graphs

Maria Helena Fino, Studenr Member, ZEEE, Josi E. Franca, Senior Member, ZEEE, and Adolfo Steiger-Gar@o

Abstruct-Signal flow graphs (SFG’s) are a powerful technique to analyze switched-capacitor (SC) circuits in a way that provides in-depth information about their operation and direct access to the corresponding symbolic z-transfer functions. Due to lengthy and error-prone symbolic manipulations this is manually man- ageable for simple first- or second-order circuits, but becomes unpractical for manipulating higher-order circuits which can not be decomposed into first- and second-order ones. Hence, there is an important need to provide designers with a computer-aided tool for the SFG symbolic analysis of a broad class of SC filtering networks, as described in this paper. Rule-based techniques are employed to capture from arbitrary circuit schematic and timing diagrams the corresponding symbolic SFG leading to the automatic generation of the associated x -transfer function. Symbols can then be instantiated to numerical values to obtain measurable data on a variety of performance indicators such as total capacitor area and capacitance spread as well as the resulting nominal frequency response and its variability against component errors. This is illustrated considering a variety of examples of SC filtering networks including, besides the more traditional filters, both finite and infinite impulse response dec- imators.

I. INTRODUCTION

YMBOLIC tools for the automatic design of analog cir- S cuits have been considered since the mid-seventies [l], [2], but the complexity of the resulting symbolic expres- sions as well as the associated lengthy time needed for their evaluation hindered their full fledge development at those early stages. Although, by contrast, numerical simulators have gained widespread acceptance by permitting evaluating the performance behavior of specific numeric design solutions (e.g., [3]), designers went on confronted with the need of possessing information also in symbolic form to search alter- native design solutions and even obtain more precise in-depth knowledge of the circuits.

In the past few years a growing interest in the development of symbolic tools has reemerged not only due to the lack of qualitative information provided by the numerical simulators but also because symbolic tools are essential to the automatic addition of new topologies to the knowledge-based analog computer aided design systems [4]. Specifically for switched-

Manuscript received May 3, 1993; revised December 20, 1994. This paper was recommended by Associate Editor J. White.

M. H. Fino is with the Universidade Nova de Lisboa, Faculdade de Cisncias e Tecnologia, Department of Electrical Engineering, Quinta da Torre, 2825 Monte da Caparica, Portugal.

J. E. Franca is with the Instituto Superior TBcnico, Department of Electrical and Computer Engineering, Integrated Circuits and Systems Group, 1096 Lisboa Codex, Portugal.

A. S. Gar@o is with the Universidade Nova de Lisboa, Faculdade de Cisncias e Tecnologia, Department of Electrical Engineering, Quinta da Torre, 2825 Monte da Caparica, Portugal.

IEEE Log Number 94 123 16.

capacitor (SC) networks, which have largely dominated analog signal processing in the past fifteen years, the originally pro- posed SC dedicated symbolic simulators could only produce symbolic transfer functions where z is the only acceptable symbolic variable [5]-[7]. New methods for the symbolic analysis of SC circuits with only two phases have also been proposed [8]. Later, an improved SC symbolic simulator was developed capable of producing partially or totally symbolic transfer functions, but where the maximum number of sym- bolic elements is limited to only ten [9]. All these pioneering SC symbolic simulators employed algebraic methods, i.e., their operation is based on the matrix formulation of SC networks. A more recent SC symbolic simulator, SCYMBAL, has been developed which can produce fully symbolic transfer functions based on the topological evaluation of the SC networks [IO]. Due to the exponential growth in memory requirements and computing time associated with direct topological methods, several decompositionhearing algorithms have been consid- ered [11]-[ 131. Other recent symbolic simulators, mainly dedicated to the analysis of analog circuits at circuit level but which also enable the designer to obtain a symbolic z-transfer function characterization of SC circuits, have been developed following matrix based methods [14], [15].

The use of topological methods together with the signal flow graph (SFG) representation of SC circuits is of great importance, for SFG’s provide in-depth information about their discrete-time operation. The SC symbolic simulator described in this paper employs rule-based techniques for capturing the SFG from arbitrary circuit schematic and timing diagrams. Taking advantadge of the regular structure of SC elements, the evaluation of the overall SFG is accomplished by intercon- necting the SFG representation of the SC elements previously recognized and characterized by invoking, respectively, a set of identification rules and another set of characterization rules. Since the SFG representation of the SC elements comprises only one branch, a substantial reduction of the number of nodes of the overall SFG representing the circuit is accom- plished, thus yielding a rather efficient computation capability. From the overall SFG the corresponding symbolic z-transfer function can be automatically generated [ 161. Symbols can then be instantiated to numerical values to obtain measurable data on a variety of performance indicators, including the nominal frequency response and its variability against com- ponent errors, total capacitor area and capacitance spread. As the present version of the program considers only ideal SC networks, the addition of decomposition/tearing techniques has not yet accomplished. This program has been developed in BIM Prolog and runs in a SUN SPARC LX station.

0278-0070/95$04,00 0 1995 IEEE

859 FlNO et ai.: AUTOMATIC SYMBOLIC ANALYSIS OF SWITCHED-CAPACITOR FILTERING NETWORKS

Besides this introduction, the paper comprises five addi- tional sections. In Section 11, the basic SC elements generally comprised in different classes of SC filtering networks are presented together with the associated SFG's. Section I11 describes the automatic rule-based techniques employed for capturing SFG's from arbitrary circuit schematic and timing diagrams. The procedure for automatically generating the corresponding symbolic z-transfer function is also briefly dis- cussed. Those techniques are illustrated in Section IV for the analysis of a variety of SC filtering networks. Finally, Section V discusses the computational efficiency of the symbolic SC simulator using both topological and element-oriented representation of the SC filtering networks. The paper is concluded in Section VI.

,

11. BASIC sc ELEMENTS AND THEIR SFG REPRESENTATION

SC networks generally consist of the interconnection of SC elementary blocks comprising switches, capacitors and operational amplifiers, and whose discrete-time operation can only be characterized with respect to the associated timing diagram. By using classical SC circuit analysis techniques [17], [I81 we can derive, for the various SC elementary blocks usually employed in SC filtering networks, the corresponding SFG representation, as summarized in Fig. 1. Here, we also indicate some icons that are adopted for such SC elements in order to simplify the schematic representation of the SC filtering networks. All SFG's shown in Fig. 1 comprise three different transmission factors that provide some physical in- sight into the operation of the corresponding SC elements. The factors zPa and z + ~ , respectively, represent the time delay (advance) associated with the input and output sampling instants of the SC elements with reference to the associated timing diagram. For example, we can see that in the case of the TSI the input voltage signal is sampled at the end of phase 2 , thus at time instant a , but the output packet of charge is only produced at time instant b in phase y. Here, we should notice that the advance term z + ~ means that the output charge is available before the arbitrary zero time reference. Thus, the overall delay from input to output is in reality ( -a + 6) as can be readily observed from the operation of the SC element. The transmission factor K indicates the relationship between the input and output sampled variables. When the SC element transforms an input sampled voltage signal into an output sampled packet of charge, K represents the equivalent transconductance value (here a capacitance) of that element, as is the case of all quasi-passive' SC elements (TSI, OFR, TSC, PCTSC, and IPCTSC) [19]. In the case of the active SC element K represents the equivalent transimpedance value (here the inverse of a capacitance) describing the transformation of an input sampled packet of charge into an output sampled voltage signal. The sign associated with the transmission factor K indicates the phase of the input (output) variables with respect to the positive reference phases. Positive voltages are defined from a node to ground while positive packets of charge are defined for a flow into an output node or for a flow from an input node.

Ofiese are elements that only contain switches and capacitors

I I LY

a .b b 7 r x d)

I I

Fig. 1 . Library of SC elements residing in the SC-KB of the symbolic analysis tool. (a) Structure. (b) Icons for simplified schematic representation. (c) SFG. (d) Switch timing.

111. AUTOMATIC GENERATION OF SYMBOLIC DISCRETE-TIME TRANSFER FUNCTIONS

A. Circuit Description

In our symbolic generator the SFG description of a given SC circuit is automatically obtained from its structural description in the form of a computer netlist. Such structural circuit description comprises two parts. The first part concerns the physical interconnections of the various SC elements whereas the second part concerns the switch timing that controls the operation of such elements. The two forms of netlist description that can be accepted by the SFG generator are represented in Fig. 2, for the simple example of an SC inte- grator (Fig. 2(a)). While in Fig. 2(bl) the circuit is described in terms of capacitors, switches and amplifiers, in Fig. 2(b2) we employ instead a block level description based on the SC elements discussed in the previous section. In Fig. 2(c) one possible clocking scheme for controlling the operation of the circuit is represented. As we can see, each clocking phase, Pi, is characterized by a rising edge instant, TiPi and a falling edge instant, Topi since the program contemplates only the case of ideal switches.

B. Rule-Based SFG Generation

After obtaining the structural description of a given SC circuit, the generation of the corresponding SFG proceeds as schematically illustrated in Fig. 3. This is based on information that resides in the SC knowledge-base (SC-KB) of the gener-

860 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 14, NO. 7. JULY 1995

Fig. 2. Illustrating the structural description of an SC integrator.

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Fig. 3. An SC-KB signal flow graph generator.

ator containing a set of structural rules used for identifying the constituting circuit elements and another set of evaluation rules for the subsequent definition of the associated SFG's.

For consistency with the 'two alternative circuit descriptions, two levels of structural rules are resident in the SC-KB. At a lower level of abstraction, a structural rule is defined in terms of capacitors, switches and operational amplifiers. This is illustrated below considering the lower level structural rule for the identification of a simple TSI comprising a group of four switches and one capacitor.

Rule I : Structural rule for the identification of a Toggle Switch Inverter.

tsi(N,Inp,Z,PI,P2,C):- /* element level description */ sw(N,Inp,X,Pl), /* switch */

capa(N,X,Y,C), /* capacitor */

sw(N,Y,Z,Pz).

sw(N,X,gnd,Pd,

sw(N,Y,gnd,Pd,

We can see in the above description that the first switch,

ground is another switch operating with phase Pz. Between the same node X and node Y is a capacitor with capacitance value G. A third switch, which also operates with the same phase PI as the one connected to the input node is connected between node Y and ground. Finally, a switch operating in the phase P 2 is connected between node Y and node 2. At a higher level of abstraction we can consider instead a set of elementary block structural rules for identifying a given SC element. For example, we can use the much shorter structural rule for identifying again a simple TSI contained in Netlist N . This is connected between nodes Inp and 2, and includes a capacitor with capacitance value C which is charged during switch phase PI and discharged (for charge transfer) during switch phase P2.

Rule 2: Structural rule for the block level identification of a Toggle Switch Inverter.

tsi(N,Inp,Z,P1,Pz,C):- /* block level description */ member( [ tsi,Inp,Z,Pl ,Pz ,CI,N).

Once an SC elementary block has been identified based on the structural rules discussed above, the corresponding SFG can be evaluated based on two groups of evaluation rules. One such group of evaluation rules is concerned with the calculation of the delay term as a function not only of the switching phases but also of the reference phase, the clock period, Period, and the unit delay, Deluni, to be considered. This is illustrated below in Rule 3 for the simple example of the TSI SC element previously considered. As we can see, the predicate calcdelay starts by obtaining the falling edge instants T0Pl and ToP2 of the phases PI and P 2 that control the operation of the SC elementary block, as well as the falling edge instant Topref of the phase taken for reference, Pref. Then, the predicate delays is invoked so that the delay Dels associated with the input voltage sampling instant is computed. Once the delay Delt related to the charge transfer instant is calculated by the predicate deluyt the total delay factor, Deltotal, is obtained by adding together Dels and Delt. Finally, the Delay term is obtained by normalizing the previously calculated total delay by the unit delay, Deluni (shown at the bottom of the page).

The predicate delays is consubstantiated by Rule 4 and Rule 5 shown below. Rule 4 is applied when the input voltage sampling instant, To PI of the capacitance pertaining to the SC element occurs after the corresponding charge transfer instant, ToP2, as schematically illustrated in Fig. 4.

operating with phase PI is connected between the input node of the structure and node X . Connected between this node and

Rule 4: Rule for evaluating the delay associated to the input voltage sampling of an SC elementary block when the

Rule 3: Rule for the evaluation of the delay term of an SC elementary block.

calcdelay (Period,Tframe,Pref ,PI ,Pz ,Deluni,Delay):- member([PI,T;Pl ,TOP1l,Tframe), /* TOPI- falling edge of phase PI */ member( [P2,T;P2,ToP2],Tframe), /* T0P2 - falling edge of phase PZ */ member([P,,f,T;P,,~,T,P,,f],Tframe), /* Topref - falling edge of the reference phase */ delays(Period,ToP1 ,T,P2,T0P,,f,Dels), /* Delay in input voltage sampling */ delayt(Period,T,P1,T0P2,T,P,,f,Delt), /* Delay in charge transfer */ Deltotal is Dels + Delt, quo(Deltotal,Deluni,Delay). /* Delay =Deltotal/Deluni */

FINO et U/.: AUTOMATIC SYMBOLIC ANALYSIS OF SWITCHED-CAPACITOR FILTERING NETWORKS 86 I

Fig. 4. Illustrating the evaluation of the delay factor for an SC elementary block, when the sampling instant TOPI occurs after the charge transfer instant,

Fig. 6. Illustrating the evaluation of the delay factor for an SC elementary block, when the charge transfer instant ToPz occurs after the reference instant,

To 4. T" Pref '

- Prd hf

T9.r

P1 P1 TOP1

Fig. 5 . Illustrating the evaluation of the delay factor for an SC elementary block, when the sampling instant TOP, occurs prior to the charge transfer instant, To Pz .

sampling instant, TOPl, occurs after the charge transfer instant, ToP2.

delays(Period, ToP~,ToP~ToPrefDels):- TOPI @>ToP2,!,

To is T,P2 + Period, Dels is TOP1- To.

/* sampling phase is after the charge transfer phase */

In this case, the charge transfer process will only take place in the next clock cycle, i.e., at ToP2 + Period, and Dels will be given. by the difference between TOP, and ToP2 + Period. Rule 5 is applied when the sampling instant occurs prior to the charge transfer instant, as illustrated in Fig. 5, and DeZs is given by the difference between TOPI and ToP2.

Rule 5: Rule for evaluating the delay associated to the input voltage sampling of an SC elementary block when the sampling instant, TOPl! occurs prior to the charge transfer instant, To P2.

delays(Period, T,PI ,ToP2 ,T0Pref,Dels):- Dels is TOP1- T0P2.

The predicate for the evaluation of the delay associated to the charge transfer process, Delt, is consubstantiated by Rules 6 and 7 shown below. Rule 6 is applied when the charge transfer instant, ToP2, of the capacitance pertaining to the SC element occurs prior to the reference instant, Topref. Here, Delt is given by the difference between T0P2 and Topref .

Rule 6: Rule for evaluating the delay associated to the charge transfer process of an SC elementary block when the charge transfer instant, ToP2, occurs prior to the reference phase, Topref.

delayt(Period, TOPI ,ToP2,ToPref,Delt):- TOPP @e Topref,!, Delt is ToP2- Topref.

Rule 7: Rule for evaluating the delay associated to the charge transfer process of an SC elementary block when the charge transfer instant, To Pz, occurs after the reference phase,

delayt( Period, ToP1 ,To P2 ,To Pref ,Delt) : - Topref.

Trefz is Topref+ Period, Delt is ToP2- Tref2.

Rule 7 considers the case when the charge transfer instant occurs after the reference phase, so that the reference phase of the next clock cycle, ToPref + Period must be considered, as schematically illustrated in Fig. 6. In this case, Delt will be given by the difference between T,Pz and ToPr,f + Period.

The second group of rules for the SFG evaluation of SC elements concerns the symbolic characterization of the weight factor Y, given the capacitance value, C, of the capacitor pertaining to the SC element and the previously calculated delay, Delay. The simple case for a TSI element is illustrated in Rule 8. As we can see, the transmission factor, K , is firstly evaluated, here K = -C, and then the TSI SFG weight, Y, is obtained by invoking predicated ratFormpf , which returns in the third argument the symbolic representation of the first two arguments ratio.

Rule 8: Rule for evaluating the SFG weight factor of a TSI.

ratpol(tsi,C,Delay,Y):- minus( [C],K), ratFormpf(K*zDelay,[ 11,Y). /* ratFormpf( num, den, nudden) */

/* Y = -C * zDelaJ'/l */

In order to generate the overall symbolic SFG corresponding to a given circuit description the automatic SFG generator first browses the netlist of the circuit so that all the operational amplifiers with a feedback capacitor are recognized and, for each of them, both the phase at which the output voltage of the amplifier is sampled, Pref, and the unit delay are determined. Then, the remaining SC elements in the circuit are identified using the above mentioned structural rules. The SFG of each one of those SC elements is calculated by application of the evaluation rules residing in the SC-KB and taking into account both the reference phase and the unit delay computed for the operational amplifier that is fed by the SC element under consideration.

C. z-transfer Function Generation

After generating the symbolic SFG of the circuit, Mason's rule [20] is applied for determining the corresponding overall

I

862

A = E = 1

C = G = 2.505

I = I = 10.7238

B = 12.0366

D = 29.99

F = H = O

z-transfer function descriDtion

I N= +(-D*I+A*H)*zh2t@*J+D*LAtG).z

D= +(B*D-E'A)*z'-2+(-2*B*DtA*E+ C*A-WF)*Z"-l+(B*D+D*F)

hl t ( -PI)

I I I I 1 I i

20 I

0

-20

4 0

Fig. 7. Automatic symbolic analysis of a lowpass notch SC biquad.

z-domain transfer function. Analytically, this is described by overall determinant A of the SFG is given by

A = 1 - C (transfer function of feedback loops) + C (products of all two non-touching

(1) feedback loops)

- C(products of all three non-touching where the summation of the Pi transfer functions extends to the total number n of forward paths from Input to Output. The feedback loops) + . . .

FINO et al.; AUTOMATIC SYMBOLIC ANALYSIS OF SWITCHED-CAPACITOR FILTERING NETWORKS

(a) (b)

z-transfer function description N=(-clb*c3c*c5c)*zA4 - (clb*c3I9oQa*c5b+clb*c2a*c3a*c5c 4*clWc3c*c5c)*zA-3 - (clWc2a*c3a*c4e *c5b-2*clb*c3c*&*c5b -2*clWc2a*c3a*c5c +6*clb*c3c*c5c)*fl-2 - (clWc3c*da*c5b +clb*c2a*c3a*dc 4*clb*c3c*&)W-l +(clb*c3&5c)

D=+(-l+cld*c3c+c3d*c5c)*zA-5+(5 +cla-clc*c2a +cld*c2a*c3a -c2b*c3a -5*cld*c3c +clc*c2b*c3c - Qb*c4a +c5a eld*c3c*c5a + c3d*c4aLc5b -c4b*c5b +cld*c3c+c4b*c5b -5*c3d*c5c -cla*c3d.c5c +clc*c2aLc3d*cSc +c3Wc4WcSc) * z 4 + (-10 4 * c l a +3*clc'c2a -3*cld*c2a*c3s +3*c2b*c3a +cla*c2Wc3a +10*cld*c3c -3*clc*c2b*c3c +3*c3b*c4a +cla*c3Wc4a clc*c2a*c3b*c4a -a*& - cla*c5a +clc*c2a*c5a -cid+c2a*da*c5a +c2b*c3a*c5a +4*cld*c3c*c5a clc+c2b*c?c*c5a +c3b*da*c5a -3*c3d*c4a*c5b cla*c3d*c4a*c5b+c lc*c2a*c3d*c4a*c5b +3*db*cSb +cla*c4b*c5b - clc*c2a*c4Wc5b +cld*c2a*c3a*c4b*c5b c2b*c3a*&*c5b -3*cld*c3c*c4b*cSb +clc*c2b*c3C.c4~~5b + 10*c3d*c5c +4*cl afc3d*c5c -3*clc*c2a*c3d*c5c -3*c3b*db*c5c - cla*c3b*c4Wc5c +clc*c2a*c3Wc4b*cSc)* 2 - 3 +(lo +6*cla -3*clc*c2a +3*cld*c2a*c3a -3*c2b*c3a- 2+cla*c2b*Qa -1(Pcld*c3c +3*clc*c2b*c3c -3*c3b*& -2*cla*c3b*c4a +clc*c2a*c3b*c4a +6*c5a +3*cla*cSa -2*clC+cZa*c5a +2*cld*c2a*c3a*c5a -2*c2Wc3a*da cla*c2Wc3a*c5a -6*cld+c3I915a +2*clc*c2b*c3c*c5a -2*c3b*da*c5a -cla*c4Wc4a*c5a +clc*c2a*c3Wda*c5a +3*c3d*da*c5b +2*cla*c3d*c4a*c5b -clc*c2a*c3d*c4a*c5b -3*dWc5b -2*cla*c4b*c5b +cl&2a*db*c5b - cld*c2a*c3a*dWc5b +c2b*c3a*c4Wc5b +cl r*c2b*c3a*dWc5b +3+cld*c3c*dWc5b - clc*c2b*c3c*c4Wc5b -1(Pc3d*c5c -6*cla*c3d*c5c +3*cla*cZa*c3d*c5c +3*c3b*db*cSc +Z*clr*cJb*c4b*c5c -clc*c2a*c3Wc4Wc5c)*zA-2 +(-5 4 * c l a +clc*c2a -cld*c2afc3a +c2b*c3a +cla*c2Wc3a +S*cld*c3c -clc*c2b*c3c +c3W& +cla*c3WoQa 4*c5a -3*cla*da +clc*c2a*c5a - cld*c2a*c3a*c5a +c2b*c3a*c5a +cla*c2b*c3a*c5a +4*cld*ck*c5a -clc*c2b*c3c*c5a +c3b*c4a*c5a +c 1 a*c3b*c4a*c5a -c3d*&*c5b -cla*c3d*c4a*c5b +c4b*c5b +cl a*c4Wc5b -c1d*c3cc+b*c5b +5*c3d*CSc + 4*cla*c3d*c5c -clc*c2a*c3d*c5c c3Wc4Wc5c cla*c3Wc4b*c5c)*z~-l +1 +cla- cld*c3c +*c5a+cla*c5a-cld*c3c*c5a -c3d*c5ccla*c3d*c5c

(C)

Fig. 8. Automatic symbolic analysis of a 5th-order lowpass elliptic ladder SC filter.

863

whereas the determinafits Ai are obtained from the SFG after removing all elements that touch the paths yielding transfer functions Pi. The above operations are automatically carried-

out by a prolog program that calculates the symbolic transfer function between any input and output nodes of a given SFG.

864

Fig. 8. Continued.

-

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. VOL. 14, NO. 7, JULY 1995

cl=c2=1.00 c3=c4=1.00 c5=1.00 c l a d . 1245 c 1bco.1343 clc=0.1609 cld=0.1409 cZa4.0805 c2b=O.M45 c3a4.0835 c3b=o.0771 c3c4.7904 c3d4.1286 c48=0.1087 c4w).0634 c5a4.2521 cSbdJ.1143 c5c4.7195

IV. EXAMPLES

A. Example I : Lowpass Notch SC Biquad The purpose of this first example considering a classical

SC biquad section is primarily to illustrate that the various SC elements of the circuit can be recognized even though a minimum switch configuration has been used [21]. The schematic circuit diagram illustrated in Fig. 7(a) generates the circuit netlist indicated in Fig. 7(b) and from which the associ- ated SFG described in Fig. 7(c) and graphically represented in Fig. 7(d) is obtained. The automatically calculated coefficients, in symbolic form, of both the numerator and denominator quadratic functions are indicated in Fig. 7(e). For illustration, these symbolic coefficients are then instantiated according to the values shown in Fig. 7(f) in order to produce a lowpass notch response with a notch frequency at fz = 1800 Hz, a pole Q-factor of Q p = 30 at fp = 1700 Hz and 0 dB dc gain. The resulting amplitude response is illustrated in Fig. 7(g).

B. Example 2: Fifth-Order Lowpass Elliptic SC Ladder Filter

In this second example we consider the fifth-order low- pass elliptic SC ladder filter [22] squematically illustrated in Fig. 8(a). This leads to the symbolic SFG graphically represented in Fig. 8(b). The symbolic functions representing the impulse response coefficients of the z-transfer function are listed in Fig. 8(c). For illustration, these symbolic coefficients are then instantiated according to the values shown in Fig. 8(d) in order to produce the amplitude response illustrated in Fig. 8(e).

C. Example 3: Active-Delayed Block FIR SC Decimator ( N = 19, M = 5: 2 Blocks)

In this third example an FIR SC decimator with active- delayed block (ADB) implementation is considered [23]. As we can see in the schematic diagram of Fig. 9(a), the circuit description is now based on the type of higher level SC elements described in Section 11. This example illustrates in particular the capability of the automatic SFG generator to recognize, and synchronize, two different reference time

instants in the switching pattern of the circuit, namely at the end of switch phase 5 for the array of SC elements connected to amplifier OAI and at the end of switch phase 1 for the array of SC elements connected to amplifier OA2. The resulting SFG is described in Fig. 9(b) and graphically represented in Fig. 9(c). The symbolic functions representing the coefficients of the overall z-transfer function in terms of the capacitance ratios of the circuit are indicated in Fig. 9(d). For illustration, these are instantiated according to the numerical values shown in Fig. 9(e). The lowpass multinotch amplitude response obtained considering the numerical values shown and for a variation of 5 1 % of the capacitance value of Cg is illustrated in Fig. 9(f).

D. Example 4: Second-Order SC Decimator with Optimum Implementation ( M = 4)

Finally, we consider the example of a 2nd order IIR SC decimator, also with optimum implementation [24]. The cor- responding circuit schematic diagram is shown in Fig. 10(a). Then, from the automatically generated SFG described in Fig. 10(b) and graphically represented in Fig. lO(c), we arrive at the symbolic functions shown in Fig. 10(d) that define in terms of the capacitance ratios of the circuit the co- efficients of both the numerator and denominator discrete- time functions. In order to obtain a 2nd order Chebyshev lowpass amplitude response with maximum ripple of 0.05 dB in the passband up to the cut-off frequency of 6 kHz we instantiate the symbols according to the numerical values given in Fig. 10(e). The resulting amplitude response is given in Fig. 1O(f).

V. COMPUTATIONAL EFFICIENCY

In order to evaluate the efficiency of the symbolic simulator described in this paper, we have obtained the CPU times consumed for analyzing the circuits illustrated in the previous section. Firstly, the CPU times consumed for obtaining the fully symbolic SFG representation of the SC circuits have been considered and then the CPU times for generating the corresponding z-transfer function have been evaluated. For

FINO et at.: AUTOMATIC SYMBOLIC ANALYSIS OF SWITCHED-CAPACITOR FILTERING NETWORKS 865

I

I Graphical SFG represenration

L SFG description 1->-2 : -1 /~(1-2".-5) 3 - 2 4 : -1 I b(l-e-5) inp>-3 : c 7 . e - 7 inp-xl : d8V-8 inp->-3 : J l V - 8 inpz-1 : dYzA-9 inp>-3 : 4*zA-9 2>-1 : ab755 inp>-l : d l *zA-l

inp->-3 : cl*zA-l inp>-l : d 3 . e - 3 inp->9 : cOCz"0 inp>-l : 2-2-3 : c W - 9 inp>-1 : d 5 V - 5 inp-5-3 : c2*2".-2 inp->-1 : 46.zA-6 inp>-3 : 43.e-3 inp>-1 : d7.zA-7

inp->-3 : c 6 V - 6

(b) 4->-3: b*zA-5 inp>-1 : d 2 W - 2

..rJ 't t

1 A

654=12.3173 b=351.9198 d4=c5=21.1846 e=lSZ.1076

d3=~6=30.7892

Frequency [MHz]

Fig. 9. Automatic symbolic analysis of an active-delayed block FIR SC decimator (4' = 19. A1 = 5 ) .

the evaluation of the computational efficiency of the symbolic SFG generator two different cases corresponding to the dif- ferent levels of circuit description used were considered. In Table I the CPU times consumed for the SFG generation of several circuits are illustrated both for the case when their description is given at the element level and when an SC elementary block level is employed. From this table we may conclude that the time for the SC block recognition depends not only on the number of SC elementary blocks to be recognized but also on the number of phases of the clocking scheme controlling the operation of the circuit.

In Table 11 the CPU times for the fully symbolic z-transfer function generation, from the corresponding SFG, of the same set of circuits are also illustrated. As the symbolic tool

TABLE I CPU TIME CONSUMED FOR GENERATING THE SYMBOLIC SFG

associates SC elements with simple single-branch SFG's the number of nodes of the overall SFG of the SC network is greatly reduced, and thus leading to very small CPU times for the generation of the symbolic z-transfer function of the circuits.

1. 866 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 14, NO. I , JULY 1995

I -L wavefonno waveforme I n waveform3

n waveform2 n waveform 1 1

waveform 41 4

Graphical SFG representation z--

SFG descriptwn z-tranrfcrfunction description I

y1=1.89417

y3=3.38663

b114338

x1=1.01232 X2= 1.00891

04.07693 d=16.4250 1 I 1 0 9 '18 Freqiiency &I

Fig. 10. Automatic symbolic analysis of a 2nd order SC decimator with optimum implementation ( A f = 4).

VI. CONCLUSIONS

This paper described a computer-aided tool for the symbolic analysis of SC filtering networks. The signal flow graph gener- ation process is based on rule-based techniques, for structural circuit recognition and evaluation. As the construction of the overall SFG of a given SC filtering network is based on the recognition of predefined SC elements characterized by the corresponding z-domain transfer functions, expansion of *the domain of application of the symbolic tool can be achieved simply by adding to the SC-KB the sets of rules that characterize any new element. The block level SFG constkction leads to a significant reduction of the number of

TABLE I1 CPU TIME CONSUMED FOR GENERATING THE SYMBOLIC TRANSFER

FUNCTION OF A CIRCUIT FROM THE CORRESPONDING SFG

0.515

0.485

0.545

nodes of the overall SFG representing the circuit, thus yielding a rather efficient computation capability. From the overall SFG

FINO et al;: AUTOMATIC SYMBOLIC ANALYSIS OF SWITCHED-CAPACITOR FILTERING NETWORKS 867

the symbolic z-transfer function of the SC network can be promptly obtained and then instantiated to numerical values to obtain measurable data on the performance behavior of the circuit.

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pp. 68-71.

Maria Helena Fino (S’95) was born in Lisbon, Por- tugal, in 1958. She received the degree of engineer in electrical engineering in 1982.

From 1982-1984 she worked in the Industry. From 1984-1992 she was with the Computer Sci- ence Department of the Faculty of Science and Technology of the New University of Lisbon as a Research Assistant. Since 1992 she has been a member of the teaching and research staff of the Electrical Department of the same faculty. Presently she is working towards the Ph.D. degree in the area

of computer aided symbolic tools.

Jose E. Franca (A’80-S’82-M’85-SM’90) re- ceived the Licenciado degree in electrical engi- neenng from the Instituto Superior Ticnico (IST), Universidade Ticnica de Lisboa, in 1978, the Ph D degree in electncal engineenng from the Impenal College of Science, Technology and Medicine, University of London, in 1985, and in 1992 obtained the degree of Agregado from IST

He has been with the Department of Electncal and Computer Engineering of IST since 1978 but, from 1980-1982, he held just a part-time position

while being an Engineer with the central research laboratones of Electricidade de Portugal He is currently an Associate Professor (Agregado) of Electrical Engineenng and Head of the Integrated Circuits and Systems Group ot IST He taught at the Continuing Education Center of Impenal College, London, AMs (Austria Mikro Systeme) and at several others Universities and Research Organizations, both in the United States and in Europe He was Director of an advanced course on the design of analog-digital VLSI circuits for telecommunications and signal processing, held in Lisbon, in 1990 Since 1989 he has actively participated and led several joint European cooperative projects in science, technology, and training His research interests are in the areas of integrated circuit design, circuit theory, signal processing, and computer-aided design of analog-digital circuits and systems

Dr Franca has published over 120 papers in international journals and conferences, is Co-Editor of Introduction to Analog VLSI Design Auromation (Norwell, MA Kluwer, 1990) and Co-Editor and Coauthor of Analgoue-Digital ASIC ’s-Circuit Techniques, Design Tools and Applications (Stevenage, U.K Peregnnus on behalf of the IEE, 1991). and Design of Analog-Digital VISI Circuits for Telecommunications and Signal P rocessing (Englewood Cliffs, NJ. Prentice-Hall, 1994) He is also Co-Holder of a US patent on switched-capacitor networks He regularly serves in the Programme Committee of several international conferences, is a member of the Editonal Board of the Kluwer Journal on Analog Integrated Circuits and Signal Processing, and also a member of the Steering Boards of MEDCHIP and NEAR, two ESPRIT funded initiatives For MEDCHIP, he also acts as Chairman of the Executive Board He has represented the Portuguese Ministry of Defense in the European EUCLID programme in science and technology for defense. He is a Member of the Portuguese Professional Asqociation of Engineers and of the Science and Technology Association for Development

Adolfo Steiger-GarqHo received the degree, of En- gineer in electrical engineering in 1968 and the Ph.D. degree in computer science from the faculty of Science and Technology in 1980.

He is with the Department of Electrical En- gineering at the New University of Lisbon as a Full Professor. He is President of the Institute of New Technologies and director of the Center of Intelligent Robotics.