Automated layout synthesis tool for op amp

Automated Layout Synthesis

Tool for Op-Amp

1

Nueraimaiti Aimaier (Nurahmad Omar)

GS 34530

[email protected]

Electrical & Electronic Department

Lecturer: A.P. DR. ROSLINA MOHD SIDEK

DR. FAKHRUL ZAMAN ROKHANI

Op-amp Physical Design

Background

2

Stick Representation

3

d d d s s

1 2 3 4

1 2 1 2 3 2 3 4 3 4

M1 M2 M3

Same width

Source: F.Maloberti – Layout of Analog CMOS IC

Layout Oriented Design

4

Possible stacks:

1 p-channel, 2 n-channel

M3, M4, M6

M1, M2

M5, M7


Stack Design and

Interconnections

5


Layout Template of Op-

Amp

6

Load

(Pmos)

Differential Pair

(Nmos)

Bias

(Nmos)

Differential Pair

7

A A

A A

B B

B B

M1 M2

A

A

B

B

M1 M2

Bias

8

C C A

A B

B

C C

Current Mirror

M5 M8

C A

A B

B

C

Load

9

C C A

A B

B

C C

C

C

C

C

Current Mirror

M3 M4

Design Flow Chart

10

schematic

netlist

Partitioning

matching generator

(Common-centroid)

auto routing

Placement &

Floorplanning

OK?

END

constraints

NO

YES

11

The whole process of the design flow consists of four main components,

which are Partitioning, Matching generator, Placement and Floorplanning, and

Auto routing. These components translate an analog circuit netlist to a fully

routed layout.

Partitioning: In this design flow, partitioning algorithm read the netlist to

select which transistors are belong which sub-block, like differential pair, circuit load

and bias part of the operational amplifier. Generate three sub-blocks.

Matching generator: In analog design, transistor matching deals with identical

used transistors. This step is capable of generating a matched common-centroid

Layout.

12

Placement & Floorplanning: After partioning and matching generator, this step locate

each transistor according to common-centroid pattern and sub-blocks according to the

layout template.

Auto routing: Using channel routing method, which composed of horizontal track

lines and vertical track lines to generate interconnections.

Process algorithm

13

Algorithm

Begin

1 import schematic;

2 while not (stopProcess);

3 generate netlist;

4 get netlist info;

5 while (partitioning)

6 choose type for each sub-block;

7 endwhile;

8 while (genMatch)

9 foreach (sub-block)

10 choose matching;

11 generate Match;

12 generate common-centroid;

13 endfor;

14 endwhile;

14

Detail in each process

Netlist MAIN CELL: Component pathname : /home/nurahmad/soc/opamp/schem/opamp1

*

X_M6 OUT N$39 VDD VDD pm_hp L=0.13u W=8u M=8

X_M9 N$42 N$42 VDD VDD pm_hp L=0.13u W=2u M=1



X_M7 OUT N$42 VSS VSS nm_hp L=0.13u W=8u M=4

X_M8 N$42 N$42 VSS VSS nm_hp L=0.13u W=8u M=2


X_M2 N$39 IN+ N$10 VSS nm_hp L=0.13u W=12u M=4

X_M1 N$14 IN- N$10 VSS nm_hp L=0.13u W=12u M=4

*

1 2 3 4 5 6 7 8 9

Label Drain Gate Source Bulk type length width finger

e.g.


15

Constraints

16

Matching constraints:

M1, M2 ----- Differential pair

M3, M4 ----- Current mirrors

M5, M8 ----- Current mirrors

Given by the user

Partitioning

17

Pmos

Nmos

Nmos

File format

Output:

Array

V1= (M6, M9, M4, M3) # Pmos

V2=(M1,M2) # Nmos

V3=(M7, M8, M5) # Nmos

18

19

Partitioning

INPUT

Netlist

consraints

Vertex V1

load (pmos)

Vertex V2

differential Pair(nmos)

Vertex V3

Bias (nmos)

OUTPUT

Input Output Process

Partitioning process algorithm

20

Algorithm

Begin

1 get netlist info;

2 while (partitioning)

3 foreach (transistor)

4 choose pmos stored into V1;

5 choose differential pair (nmos) stored into V2; #constraints

6 choose remaining nmos stored into V3;

7 endfor;

8 endwhile;

End

Algorithm Workout

21

differential pair

(Constraint)

Vertex V2

pmos

Vertex V1

nmos

Vertex V3

E.g. V1= (M6, M9, M4, M3) V2=(M1,M2) V3=(M7, M8, M5)

Partitioning snapshot

22

Vertex V1

pmos

Vertex V2

nmos

Vertex V3

nmos

Condition/range

23

The op-amp should be conventional two-stage amplifier OTA ( Operational

Transconductance Amplifier), which composed of 3 subblocks like differential pair,

Load and bias blocks

The op-amp inputs are nmos, if the inputs are pmos, the algorithm should be change

accordingly.

In each sub-block it can work any number of transistors. E.g. in the load and bias

block it may contains not only 3 or 4 transistors but the number can reach to 5 or 6

transistors, this is depend on design specification.

Matching generator

Matching

generator

INPUT

1. Netlist

(finger-numbers)

2. Constraints

M3 M4… M6 M6 M6 … (V1A)

M4 M3… M6 M6 M6 … (V1B)

M1 M2

M2 M1 OR

M1 M2 M2 M1… (V2A)

M2 M1 M1 M2… (V2B)

M5 M8… M7 M7 M7 … (V3A)

M8 M5… M7 M7 M7 … (V3B)

OUTPUT

Matching process algorithm

25

Algorithm

Begin

1 get netlist info; # multi-finger info e.g. M=8 means 8 multifinger

2 while (matching)

3 foreach (transistor)

4 choose differential pair; # V2=(M1,M2)

5 get multi finger number M; # The finger numbers should be same

6 if (M=2)

7 copy V2 to V2A; #V2A=(M1,M2)

8 inverse V2 and copy to V2B; #V2B=(M2,M1)

9 endif;

10 if (M=4);

11 copy V2 1st element to 2nd, 0 element to 3rd element and give it V2A;

12 inverse V2 repeat step 11; #V2A=(M1,M2,M2,M1)

13 endif;

26

14 choose pmos V1;

15 choose current mirror;

16 repeat step 5 to 13 to get V1A and V1B;

17 add M/2 numbers of remaining pmos to the end of V1A;

18 repeat 17 to get V1B;

19 choose remaing nmos V3;

20 repeat 15 to 19 to to get V3A and V3B;

22 endforeach;

23 endwhile;

End

File format

27

Matching generator

Array

V1A= (M3,M4…M6,M6,M6…) OR V1A= (M3,M4,M4,M3…M6,M6,M6…)

V1B= (M4,M3…M6,M6,M6…) OR V1B= (M4,M3,M3,M4…M6,M6,M6…)

V2A= (M1,M2,M2,M1…) OR V2A= (M1,M2)

V2B=(M2,M1,M1,M2…) OR V2B= (M2,M1)

V3A= (M8,M5…M7,M7…) OR V3A= (M8,M5,M5,M8…M7,M7…)

V3B= (M5,M8…M7,M7…) OR V3B= (M8,M5,M5,M8…M7,M7…)

Matching generator

snapshot

28

Load Differential Pair Bias

Condition/Range

29

The differential pair and common-centroid transistors are given by the user

The numbers of multi-finger should be even number in order to generate the

common-centroid layout

Placement & Floorplanning

30

Placement &

Floorplanning

INPUT

1. Netlist

2. DRC file

Placement&Floorplanning

process algorithm

31

Algorithm

Begin

1 get netlist info;

2 get DRC info;

3 while (placement)

4 foreach (sub-Vertex) #V1A,V1B,V2A…

5 put current mirror (diff pair) in the middle of sub-vertex;

6 put other transistor on 2 sides of sub-vertex;

6 endforeach; # get common centroid arranged vertex

7 generate diff layout;

8 get Track size and number of tracks from the user;

9 generate load layout ;

10 get distance between diff and load layout;

11 generate bias layout, distance same as step 10;

12 endwhile;

13 End

32

A A

A A

B B

B B

C A C B

C C

A

A B

B C C

C C

C A C B C C

Track Size *

Number Of Tracks

Distance(block1,block2)=Distance(block2,block3)

Inside each sub-block, the distance between 1st

row and 2nd row same as distance between blocks,

for the purpose of routing capacity

block1

block2

block3

Placement

Snapshot

33

34

Placement file format ( for each sub-block)

Array

V1A= (…M6,M6,M3,M4,M6,M6…)

V1B= (…M6,M6,M4,M3,M6,M6…)

V2A= (…M1,M2,M2,M1…)

V2B= (…M2,M1,M1,M2…)

V3A= (…M7,M5,M8,M7…)

V3B= (…M7,M8,M5,M7…)

Common centroid arranged vertex

Routing

35

Placement &

Floorplanning

INPUT

1. Netlist

2. DRC file

OUTPUT

1.Transisors D,G,S coordinate locations

2.Horizontal track lines between each row

and block

3.Vertical track lines two besides of layout

36

A A

A A

B B

B B

A C B

C C

A

A B

B C C

C C

A C B C C

Routing channel

Routing channel

Routing channel

C

C

Routing channel

Routing channel

Track_line_y[$i]

Tra

ck

_lin

e_

x[$

i]

File format

37

Matrix

X_M6

X_M9

X_M4

X_M3

X_M7

X_M8

X_M5

X_M2

X_M1

Drain Gate Source

1 2 3

4 4 3

2 5 3

5 5 3

1 4 6

4 4 6

7 4 6

2 8 7

5 9 7

Same number in the matrix belongs to same net, should be connect together.

Channel routing

FZR Rev 1.0 38

Can be implemented between each blocks and each row inside the block.

Routing algorithm process

39

Horizontal Constraints: This exist when the set of columns spanned by two nets

Intersect, since their trunks cannot be both assigned to the same track on the same

layer.

Vertical Constraints: These are present when terminals for two different nets a

and b, exist at the same column i. If the terminal for net a lies on the top side of the

channel, then we say that net a is above net b, or equivalently net b is below net a.

Algorithm

Begin

1. Let d be the channel density as given by the Horizontal Constraints Graph(HCG);

Let t1,…..td denote the routing tracks.

2. Sort the set of intervals, computed in the construction of the HCG in the ascending

order of abscissas of their left ends.

Let i1, i2, ….in denote the sorted set.

3. Assign i1 to track t1.

3a. For j=2 to n do

Assign net ij to an arbitrary available track tj.

4. Once, the horizontal tracks are assigned, the vertical branches are simply

assigned to either to TOP or BOT layer depending on whether they are upward

or downward directed.

End

FZR Rev 1.0 40

Routing snapshot

41

Condition/Range

42

Channel routing have enough space

Limited metal layer ( two layer)

Result

43

Detail of the software tool:

Reading DRC file

Reading netlist

Partitioning algorithm

Matching algorithm

Placement & Floorplanning algorithm

Routing algorithm

Layout generation

Input value range:

From the screen input:

Track size and number of tracks

From the netlist:

Numbers of muliti-fingers

Transistor width and length

Running the program

44

Load (Block1)

45

Differential pair (Block2)

46

Bias (Block3)

47

Netlist 1 Layout

48

* MAIN CELL: Component pathname : /home/nurahmad/soc/opamp/schem/opamp1

*

CC N$39 OUT 3P










*

.end

FZR Rev 1.0 49

Netlist 1 corresponding layout

Netlist 2 Layout


*

CC N$39 OUT 3P










*

.end

FZR Rev 1.0 50

FZR Rev 1.0 51

Layout works correctly, but the VDD and

VSS metal layer did not change location

correspondly, waste area.

Block1(Pmos) error

FZR Rev 1.0 52

The poly disconnected below 2nd row get

Netlist 3 Layout


*

CC N$39 OUT 3P










*

.end

FZR Rev 1.0 53

54

Layout works correctly, but the VDD and

VSS metal layer did not change location

correspondly, waste area.

Netlist 4 layout

FZR Rev 1.0 55


*

CC N$39 OUT 3P










*

.end

FZR Rev 1.0 56

Multi-finger numbers change, placement

works correctly with symmetry layout, but routing

does not work correctly, routing program still need

to improve

DRC Check

57

Assumption & Design issue

58

i. Condition/range of the tool:

Two-stage OTA (Operational Transconductance Amplifier)

The Multi-finger numbers in netlist should be even number for the purpose of

common-centroid layout.

Conclusion & Future work

59

• In this project, we presented a layout method for operational amplifier.

Our analog placer considers symmetry constraint, common centroid constraint

and device clustering in placement. Furthermore we point out that some methods

used in digital block layout like track size and channel routing are also applicable for

analog layout. Experimental results show that we can generate the analog layout

within minutes.

• Since there are lots of common-centroid layout patterns, possible future works

would be created a multi row ( more than 2 row) common centroid layout, at the

same time the routing become more complex, so reliable “analog” router still

remains to be seen.

Milestone

60

Week Topic

1 Unix

2 Unix & Shell Programming

3 Perl

4 SoC design automation review

5 SoC design automation review

6 Literature review on analog layout generation

7 Algorithms for layout generation

8 Programming for Reading DRC file

9 Programming for Reading netlist

10 Partitioning & Matching generator

11 Placement & Floorplanning

12 Auto routing

13 Layout generation

14 Final Project Presentation

Automated layout synthesis tool for op amp

Engineering

vss vss nm

m2 numbers of remaining

vdd vdd pm

copy v2

matching constraints

inverse v2

analog design

layout template of op