ATTENDANCE MONITORING SYSTEM USING SMART CARD Project Submitted in Partial fulfillment of the requirements For the degree of BACHELOR OF ENGINEERING BY Amit Ramesh Jain Anand K S Maulik Bharat Gandhi Under the guidance of Prof. SUSHMA S KADGE DEPARTMENT OF ELECTRONICS ENGINEERING K. J. SOMAIYA COLLEGE OF ENGINEERING, MUMBAI 1
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
ATTENDANCE MONITORING SYSTEM USING SMART CARD
ProjectSubmitted in Partial fulfillment of the requirements
For the degree of
BACHELOR OF ENGINEERINGBY
Amit Ramesh Jain
Anand K S
Maulik Bharat Gandhi
Under the guidance of
Prof. SUSHMA S KADGE
DEPARTMENT OF ELECTRONICS ENGINEERINGK. J. SOMAIYA COLLEGE OF ENGINEERING, MUMBAI
UNIVERSITY OF MUMBAI
2007-2008
1
Attendance monitoring system using smart card
Submitted by:
Amit Ramesh Jain
Anand K S
Maulik Bharat Gandhi
In Partial fulfillment of the degree of B. E. in Electronics Engineering is approved.
Guide Examiners
------------------------ --------------------
--------------------
-------------------------- ---------------------
Head of Department Principal
Date:
2
Index:
I) Introduction 5
II) Why do we need this project? 6
III) Development
a. Basic requirement 8
b. Sample student’s I card 9
c. Sample teacher’s I card 9
IV) Hardware implementation
a. Smart Card reader 11
b. Development board for 89s8252 13
c. LCD interface 14
d. Interfacing computer using RS232 15
V) Software implementation
a. Old R/W on chip eeprom memory function 19
b. Modified R/W on chip eeprom memory function 22
c. Algorithm 23
d. How the attendance record is maintained? 24-31
VI) Microcontroller programming
a. Main programming 33
b. LCD programming 36
c. Serial programming 39
VII) Visual Basic 41
VIII) Summary and future prospects 43
IX) Components Used 45
X) Acknowledgement 47
XI) References 49
3
XII) Appendix 51-57
Introduction
4
INTRODUCTION
A punch card (or Hollerith card or IBM card), is a piece of stiff paper that contains
digital information represented by the presence or absence of holes in predefined
positions. Punched cards were widely used throughout the 19th century for controlling
textile looms and through the 20th century in unit record machines for input, processing,
and data storage. Early digital computers used punched cards as the primary medium for
input of both computer programs and data, with offline data entry on key punch
machines. Some voting machines have used punched cards.
From the 1900s, into the 1950s, punched cards were the primary medium for data entry,
data storage, and processing in institutional computing.
Punch cards can find applications in maintaining the attendance records. This is the main
idea of our project. Each student, as in this case will be having his own unique punch
card. By using this card along with the reader the attendance record can be updated.
The micro controller 89s8252 is interfaced with the card reader. The database of all the
students is maintained in the internal eeprom memory and the micro controller
intelligently updates their status from time to time. A serial communication device
RS232C is used to interface the micro controller with the computer.
5
Why do we need this project?
The traditional procedure for maintaining the attendance record was to pass the
attendance sheet during the lecture. This attendance sheet could constitute the status for
only 4 – 5 sessions. So in order to calculate the attendance for entire term all such
attendance sheets had to be assimilated. This procedure would require a lot of manual
work.
Our project is designed in such a way that the micro controller would automatically
update the status of the attendance when the reader detects the card. By using this system
it is possible to maintain the attendance for duration of 2 – 3 months and it enables the
user to keep a track of his attendance at any point.
This project would be user friendly as the student is only required to zip his card in order
to mark his attendance. This system will also minimize the malpractice of proxy
attendance.
6
Development
Basic requirement
Sample student’s I card
Sample teacher’s I card
7
Development:
The basic requirement of this project is to design a system that would keep a track of attendance of all the students for a given number of subjects and given number of days.
We are using a punch card i.e. a card with holes at different locations. The card is inserted into the card reader. The reader consists of infra-red sensors i.e. transmitters and receivers. The card is inserted in between the transmitter and receiver. The circuit would break when there are no holes and the resultant output would be logic 0. The slots that are punched would let the rays to reach the receiver and hence close circuit i.e. the output would be logic 1. Thus different sensors in the reader circuit would give different outputs depending on whether the card is punched or not.
Different students will have different I-cards i.e. holes would be punched at different unique locations and thus unique reader output.
The reader is now interfaced with a micro controller. Each student is given a standard memory space inside the internal eeprom which would contain the attendance record. As and when the student enters the class for the lecture and inserts the card in the reader, his/her attendance is marked. The attendance of all the students can be tracked whenever required after a month or so by using serial cable on HyperTerminal. A report consisting of necessary information like a student’s name along with roll no, total number of lectures attended, total number of lectures conducted in a particular month, etc. The percentage present for a student can be calculated and the ones below a particular limit can black listed. No paper work. Reports would be ready on the click of a mouse.
Basic requirements:
The most important requirement was to develop an ID card unique for each student. The
card has to be prepared by us since such cards available in the market won’t necessarily
suit our requirement.
8
The ID card would be unique for each student and teachers. The eeprom memory is
segmented into two parts: student’s space and teacher’s space based upon their unique
ID.
Sample Student’s I-card:
Sample Teacher’s I-card:
0
0
0
10
0
9
Hardware implementation
Smart Card reader
Development board for 89s8252
LCD interface
Interfacing computer using RS232
1
1
1
01
1
10
Hardware implementation:
>> Smart card reader:
The reader consists of a simple IR transmitter receiver circuit, the output of which is
directly given to port 0 of the microcontroller. Initially we had designed the following
circuit with an op amp (LM 324)
11
The above circuit was turning out to be complex as we had to integrate 6 pairs of transmitter & receiver along with an op amp. Moreover as a single IC of LM 324 does not have 6 o/p pins we had to use 2 of them.
So we switched over to a simpler resistance divider network as shown.
12
For this circuit we used a 330Ω resistance in series with the LEDs for their conduction.
As we also knew that the resistance of the IR receiver decreases on sensing the IR signal
we had to select a high valued resistor so as to get the required voltage level for the micro
controller. After trying out different combinations we finally decided to select 5.6k Ω as
the series resistor for the receiver.
Now in case of presence of a hole the IR signal from the transmitter reaches the receiver.
As a result, the receiver offers very low resistance and a desired voltage level for the
microcontroller is achieved (logic 1). When a block is placed in the path of IR signal the
receiver acts as an open circuit and negligible voltage is achieved (logic 0).
>>Development board for 89s8252
13
The second step of hardware implementation was to prepare a development board for our
Microcontroller 89s8252. This development board was easily available in the market
along with the required components. After integrating these components on the
development board we had to make some necessary modifications to suit our
microcontroller. The first step was to isolate Vcc pin of port1 (programming port) and
connect it to reset point of microcontroller (PIN 9). The other necessary precaution we
had to take is to ensure that the other Vcc connections remain undisturbed.
>>LCD interface
14
• 8 data pins D7:D0
Bi-directional data/command pins.
Alphanumeric characters are sent in ASCII format.
• RS: Register Select
RS = 0 -> Command Register is selected
RS = 1 -> Data Register is selected
• R/W: Read or Write
0 -> Write, 1 -> Read
• E: Enable (Latch data)
Used to latch the data present on the data pins.
A high-to-low edge is needed to latch the data.
• VEE : contrast control
>>Interfacing with computer using RS232:
RS-232 Voltage levels
15
1. +3 to +25 volts to signify a "Space" (Logic
0)
2. -3 to -25 volts for a "Mark" (logic 1).
3. Any voltage in between these regions (i.e. between +3 and -3 Volts) is undefined.
The data byte is always transmitted least-significant-bit first.
The bits are transmitted at specific time intervals determined by the baud rate of the
serial signal.
This is the signal present on the RS-232 Port of your computer, shown below.
RS-232 Logic Waveform
RS-232 LEVEL CONVERTER:
Standard serial interfacing of microcontroller (TTL) with PC or any RS232C Standard
device , requires TTL to RS232 Level converter . A MAX232 is used for this purpose. It
provides 2-channel RS232C port and requires external 10uF capacitors.
The driver requires a single supply of +5V .
16
MAX-232 includes a Charge Pump, which generates +10V and -10V from a single 5v
supply.
MICROCONTROLLER INTERFACING WITH RS-232 STANDARD DEVICES
MAX232 (+5V -> +-12V converter)
Serial port male 9 pin connector (SER)
SETTING SERIAL PORT.
SCON
8 bit UART ,RN enabled , TI & RI operated by program. - 50hex
Features Description• Compatible with MCS®51 Products • 8K Bytes of In-System Reprogrammable Downloadable Flash Memory – SPI Serial Interface for Program Downloading – Endurance: 1,000 Write/Erase Cycles • 2K Bytes EEPROM – Endurance: 100,000 Write/Erase Cycles• 4V to 6V Operating Range• Fully Static Operation: 0 Hz to 24 MHz• Three-level Program Memory Lock• 256 x 8-bit Internal RAM• 32 Programmable I/O Lines• Three 16-bit Timer/Counters• Nine Interrupt Sources • Programmable UART Serial Channel• SPI Serial Interface • Low-power Idle and Power-down Modes• Interrupt Recovery from Power-down • Programmable Watchdog Timer
52
• Dual Data Pointer • Power-off Flag
The AT89S8252 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of downloadable Flash programmable and erasable read-only memory and 2K bytes of EEPROM. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip downloadable Flash allows the program memory to be reprogrammed In-System through an SPI serial interface or by a conventional nonvol-atile memory programmer. By combining a versatile 8-bit CPU with downloadable Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcontroller, which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S8252 provides the following standard features: 8K bytes of downloadable Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8252 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. The downloadable Flash can be changed a single byte at a time and is accessible through the SPI serial interface. Holding RESET active forces the SPI bus into a serial programming interface and allows the program memory to be written to or read from unless lock bits have been activated.
Pin Configurations
Pin DescriptionVCC Supply voltage
GND Ground
Port 0 Port 0 is an 8-bit open drain bi-didirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.
53
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are exter-nally being pulled low will source current (IIL) because of the internal pull-ups.
Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are exter-nally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are exter-nally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification.
Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
54
Watchdog and Memory Control Register The WMCON register contains control bits for the Watchdog Timer (shown in Table 3). The EEMEN and EEMWE bits are used to select the 2K bytes on-chip EEPROM, and to enable byte-write. The DPS bit selects one of two DPTR registers available. Table 3. WMCON—Watchdog and Memory Control Register
55
Data Memory – EEPROM and RAM The AT89S8252 implements 2K bytes of on-chip EEPROM for data storage and 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For exam-ple, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space. The on-chip EEPROM data memory is selected by setting the EEMEN bit in the WMCON register at SFR address location 96H. The EEPROM address range is from 000H to 7FFH. The MOVX instructions are used to access the EEPROM. To access off-chip data memory with the MOVX instructions, the EEMEN bit needs to be set to “0”. The EEMWE bit in the WMCON register needs to be set to “1” before any byte location in the EEPROM can be written. User software should reset EEMWE bit to “0” if no fur-ther EEPROM write is required. EEPROM write cycles in the serial programming mode are self-timed and typically take 2.5 ms. The progress of EEPROM write can be moni-tored by reading the RDY/BSY bit (read-only) in SFR WMCON. RDY/BSY = 0 means programming is still in progress and RDY/BSY = 1 means EEPROM write cycle is completed and another write cycle can be initiated. In addition, during EEPROM programming, an attempted read from the
56
EEPROM will fetch the byte being written with the MSB complemented. Once the write cycle is com-pleted, true data are valid at all bit locations.
Interrupts The AT89S8252 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 10 shows that bit position IE.6 is unimplemented. In the AT89C51, bit position IE.5 is also unimplemented. User software should not write 1s to these bit posi-tions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vec-tored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.