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ATmega328/P AVR Microcontroller with picoPower Technology
Introduction
The picoPower ATmega328/P is a low-power CMOS 8-bit
microcontroller based on the AVR enhancedRISC architecture. By
executing powerful instructions in a single clock cycle, the
ATmega328/P achievesthroughputs close to 1 MIPS per MHz. This
empowers system designers to optimize the device for
powerconsumption versus processing speed.
Feature
High Performance, Low-Power AVR 8-Bit Microcontroller Family
Advanced RISC Architecture
131 Powerful instructions Most single clock cycle execution 32 x
8 General purpose working registers Fully static operation Up to 20
MIPS throughput at 20 MHz On-chip 2-cycle multiplier
High Endurance Nonvolatile Memory Segments 32K Bytes of
in-system self-programmable Flash program memory 1K Bytes EEPROM 2K
Bytes internal SRAM Write/erase cycles: 10,000 Flash/100,000 EEPROM
Data retention: 20 years at 85C/100 years at 25C(1)
Optional boot code section with independent lock bits In-system
programming by on-chip boot program True read-while-write
operation
Programming lock for software security QTouch Library
Support
Capacitive touch buttons, sliders and wheels QTouch and QMatrix
acquisition Up to 64 sense channels
Peripheral Features Two 8-bit Timer/counters with separate
prescaler and Compare mode One 16-bit Timer/counter with separate
prescaler, Compare mode, and Capture mode Real time counter with
separate oscillator Six PWM channels
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8-channel 10-bit ADC in TQFP and QFN/MLF package Temperature
measurement
6-channel 10-bit ADC in PDIP package Temperature measurement
Two master/slave SPI serial interface One programmable serial
USART One byte-oriented 2-wire serial interface (Philips I2C
compatible) Programmable watchdog timer with separate on-chip
oscillator One on-chip analog comparator Interrupt and wake-up on
pin change
Special Microcontroller Features Power-on Reset and programmable
Brown-out Detection Internal calibrated oscillator External and
internal interrupt sources Six sleep modes: idle, ADC noise
reduction, power-save, power-down, standby, and extended
standby I/O and Packages
23 Programmable I/O lines 28-pin PDIP, 32-lead TQFP, 28-pad
QFN/MLF and 32-pad QFN/MLF
Operating Voltage: 1.8 - 5.5V
Temperature Range: -40C to 105C
Speed Grade: ATmega328/P: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @
2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Power Consumption at 1 MHz, 1.8V, 25C Active mode: 0.2 mA
Power-Down mode: 0.1 A Power-Save mode: 0.75 A (Including 32 kHz
RTC)
ATmega328/P
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Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................
1
1.
Description.................................................................................................................9
2. Configuration
Summary...........................................................................................10
3. Ordering Information
...............................................................................................113.1.
ATmega328
...............................................................................................................................
113.2. ATmega328P
.............................................................................................................................11
4. Block
Diagram.........................................................................................................
13
5. Pin
Configurations...................................................................................................
145.1.
Pinout.........................................................................................................................................
145.2. Pin
Descriptions.........................................................................................................................
17
6. I/O
Multiplexing........................................................................................................19
7.
Resources...............................................................................................................
21
8. Data
Retention.........................................................................................................22
9. About Code
Examples.............................................................................................23
10. Capacitive Touch
Sensing.......................................................................................
2410.1. QTouch
Library...........................................................................................................................24
11. AVR CPU
Core........................................................................................................
2511.1.
Overview....................................................................................................................................
2511.2. Arithmetic Logic Unit
(ALU)........................................................................................................2611.3.
Status
Register...........................................................................................................................2611.4.
General Purpose Register
File...................................................................................................2911.5.
Stack
Pointer..............................................................................................................................3011.6.
Instruction Execution
Timing......................................................................................................
3211.7. Reset and Interrupt
Handling.....................................................................................................
33
12. AVR
Memories.........................................................................................................3612.1.
Overview....................................................................................................................................
3612.2. In-System Reprogrammable Flash Program
Memory................................................................3612.3.
SRAM Data
Memory..................................................................................................................
3712.4. EEPROM Data
Memory.............................................................................................................
3812.5. I/O
Memory.................................................................................................................................3912.6.
Register
Description...................................................................................................................40
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13. System Clock and Clock
Options............................................................................
4913.1. Clock Systems and Their
Distribution........................................................................................
4913.2. Clock
Sources............................................................................................................................
5013.3. Low-Power Crystal
Oscillator.....................................................................................................
5213.4. Full Swing Crystal
Oscillator.......................................................................................................5413.5.
Low-Frequency Crystal
Oscillator..............................................................................................
5513.6. Calibrated Internal RC
Oscillator................................................................................................5613.7.
128 kHz Internal
Oscillator.........................................................................................................
5713.8. External
Clock............................................................................................................................
5813.9. Timer/Counter
Oscillator.............................................................................................................5913.10.
Clock Output
Buffer....................................................................................................................5913.11.
System Clock
Prescaler.............................................................................................................
5913.12. Register
Description...................................................................................................................60
14. Power Management and Sleep
Modes...................................................................
6414.1.
Overview....................................................................................................................................
6414.2. Sleep
Modes..............................................................................................................................
6414.3. BOD
Disable...............................................................................................................................6514.4.
Idle
Mode....................................................................................................................................6514.5.
ADC Noise Reduction
Mode......................................................................................................
6514.6. Power-Down
Mode.....................................................................................................................6614.7.
Power-Save
Mode......................................................................................................................6614.8.
Standby
Mode............................................................................................................................
6714.9. Extended Standby
Mode............................................................................................................6714.10.
Power Reduction
Register.........................................................................................................
6714.11. Minimizing Power
Consumption.................................................................................................6714.12.
Register
Description...................................................................................................................69
15. System Control and
Reset.......................................................................................7415.1.
Resetting the
AVR......................................................................................................................
7415.2. Reset
Sources............................................................................................................................7415.3.
Power-on
Reset..........................................................................................................................7515.4.
External
Reset............................................................................................................................7615.5.
Brown-out
Detection...................................................................................................................7615.6.
Watchdog System
Reset............................................................................................................7715.7.
Internal Voltage
Reference.........................................................................................................7715.8.
Watchdog
Timer.........................................................................................................................
7815.9. Register
Description...................................................................................................................80
16.
Interrupts.................................................................................................................
8416.1. Interrupt Vectors in
ATmega328/P.............................................................................................
8416.2. Register
Description...................................................................................................................86
17. EXTINT - External
Interrupts...................................................................................
8917.1. Pin Change Interrupt
Timing.......................................................................................................8917.2.
Register
Description...................................................................................................................90
18.
I/O-Ports..................................................................................................................
99
ATmega328/P
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18.1.
Overview....................................................................................................................................
9918.2. Ports as General Digital
I/O......................................................................................................10018.3.
Alternate Port
Functions...........................................................................................................10318.4.
Register
Description.................................................................................................................
115
19. 8-bit Timer/Counter0 (TC0) with
PWM..................................................................
12719.1.
Features...................................................................................................................................
12719.2.
Overview..................................................................................................................................
12719.3. Timer/Counter Clock
Sources..................................................................................................
12919.4. Counter
Unit.............................................................................................................................
12919.5. Output Compare
Unit...............................................................................................................
13019.6. Compare Match Output
Unit.....................................................................................................13219.7.
Modes of
Operation..................................................................................................................13419.8.
Timer/Counter Timing
Diagrams..............................................................................................
13819.9. Register
Description.................................................................................................................140
20. 16-bit Timer/Counter1 (TC1) with
PWM................................................................
15220.1.
Overview..................................................................................................................................
15220.2.
Features...................................................................................................................................
15220.3. Block
Diagram..........................................................................................................................15220.4.
Definitions.................................................................................................................................15320.5.
Registers..................................................................................................................................
15420.6. Accessing 16-bit Timer/Counter
Registers...............................................................................15420.7.
Timer/Counter Clock
Sources..................................................................................................
15720.8. Counter
Unit.............................................................................................................................
15720.9. Input Capture
Unit....................................................................................................................
15820.10. Output Compare
Units.............................................................................................................
16020.11. Compare Match Output
Unit.....................................................................................................16220.12.
Modes of
Operation..................................................................................................................16320.13.
Timer/Counter 0, 1
Prescalers.................................................................................................
17120.14. Timer/Counter Timing
Diagrams..............................................................................................
17120.15. Register
Description.................................................................................................................173
21. Timer/Counter 0, 1
Prescalers...............................................................................18621.1.
Internal Clock
Source...............................................................................................................18621.2.
Prescaler
Reset........................................................................................................................18621.3.
External Clock
Source..............................................................................................................18621.4.
Register
Description.................................................................................................................188
22. 8-bit Timer/Counter2 (TC2) with PWM and Asynchronous
Operation...................19022.1.
Features...................................................................................................................................
19022.2.
Overview..................................................................................................................................
19022.3. Timer/Counter Clock
Sources..................................................................................................
19222.4. Counter
Unit.............................................................................................................................
19222.5. Output Compare
Unit...............................................................................................................
19322.6. Compare Match Output
Unit.....................................................................................................19522.7.
Modes of
Operation..................................................................................................................19622.8.
Timer/Counter Timing
Diagrams..............................................................................................
200
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22.9. Asynchronous Operation of
Timer/Counter2............................................................................20122.10.
Timer/Counter
Prescaler..........................................................................................................
20322.11. Register
Description.................................................................................................................203
23. Serial Peripheral Interface
(SPI)............................................................................21823.1.
Features...................................................................................................................................
21823.2.
Overview..................................................................................................................................
21823.3. SS Pin
Functionality.................................................................................................................
22223.4. Data
Modes..............................................................................................................................22223.5.
Register
Description.................................................................................................................223
24. Universal Synchronous Asynchronous Receiver Transceiver
(USART)............... 22824.1.
Features...................................................................................................................................
22824.2.
Overview..................................................................................................................................
22824.3. Block
Diagram..........................................................................................................................22824.4.
Clock
Generation......................................................................................................................22924.5.
Frame
Formats.........................................................................................................................23224.6.
USART
Initialization.................................................................................................................
23324.7. Data Transmission The USART
Transmitter.........................................................................
23424.8. Data Reception The USART
Receiver..................................................................................
23624.9. Asynchronous Data
Reception.................................................................................................24024.10.
Multi-Processor Communication
Mode....................................................................................
24324.11. Examples of Baud Rate
Setting...............................................................................................
24324.12. Register
Description.................................................................................................................246
25. USART in SPI (USARTSPI)
Mode.........................................................................25625.1.
Features...................................................................................................................................
25625.2.
Overview..................................................................................................................................
25625.3. Clock
Generation......................................................................................................................25625.4.
SPI Data Modes and
Timing.....................................................................................................25725.5.
Frame
Formats.........................................................................................................................25725.6.
Data
Transfer............................................................................................................................25925.7.
AVR USART MSPIM vs. AVR
SPI............................................................................................26025.8.
Register
Description.................................................................................................................261
26. Two-Wire Serial Interface
(TWI)............................................................................
26226.1.
Features...................................................................................................................................
26226.2. Two-Wire Serial Interface Bus
Definition..................................................................................26226.3.
Data Transfer and Frame
Format.............................................................................................26326.4.
Multi-Master Bus Systems, Arbitration, and
Synchronization...................................................26626.5.
Overview of the TWI
Module....................................................................................................26826.6.
Using the
TWI...........................................................................................................................27026.7.
Transmission
Modes................................................................................................................
27326.8. Multi-Master Systems and
Arbitration......................................................................................
29126.9. Register
Description.................................................................................................................292
27. Analog Comparator
(AC).......................................................................................30027.1.
Overview..................................................................................................................................
300
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27.2. Analog Comparator Multiplexed
Input......................................................................................30027.3.
Register
Description.................................................................................................................301
28. Analog-to-Digital Converter
(ADC)........................................................................
30528.1.
Features...................................................................................................................................
30528.2.
Overview..................................................................................................................................
30528.3. Starting a
Conversion...............................................................................................................30728.4.
Prescaling and Conversion
Timing...........................................................................................30828.5.
Changing Channel or Reference
Selection..............................................................................31028.6.
ADC Noise
Canceler................................................................................................................
31228.7. ADC Conversion
Result...........................................................................................................
31528.8. Temperature
Measurement......................................................................................................
31628.9. Register
Description.................................................................................................................316
29. debugWIRE On-chip Debug
System.....................................................................32529.1.
Features...................................................................................................................................
32529.2.
Overview..................................................................................................................................
32529.3. Physical
Interface.....................................................................................................................32529.4.
Software
Breakpoints...............................................................................................................
32629.5. Limitations of
debugWIRE........................................................................................................32629.6.
Register
Description.................................................................................................................326
30. Boot Loader Support Read-While-Write Self-programming
(BTLDR)................ 32830.1.
Features...................................................................................................................................
32830.2.
Overview..................................................................................................................................
32830.3. Application and Boot Loader Flash
Sections............................................................................32830.4.
Read-While-Write and No Read-While-Write Flash
Sections...................................................32930.5.
Boot Loader Lock
Bits..............................................................................................................
33130.6. Entering the Boot Loader
Program...........................................................................................33230.7.
Addressing the Flash During
Self-Programming......................................................................33330.8.
Self-Programming the
Flash.....................................................................................................33430.9.
Register
Description.................................................................................................................342
31. Memory Programming
(MEMPROG).....................................................................34531.1.
Program And Data Memory Lock
Bits......................................................................................34531.2.
Fuse
Bits..................................................................................................................................
34631.3. Signature
Bytes........................................................................................................................34831.4.
Calibration
Byte........................................................................................................................34931.5.
Serial
Number..........................................................................................................................
34931.6. Page
Size.................................................................................................................................34931.7.
Parallel Programming Parameters, Pin Mapping, and
Commands..........................................34931.8. Parallel
Programming...............................................................................................................35131.9.
Serial
Downloading..................................................................................................................
359
32. Electrical
Characteristics.......................................................................................
36432.1. Absolute Maximum
Ratings......................................................................................................36432.2.
Common DC
Characteristics....................................................................................................36432.3.
Speed
Grades..........................................................................................................................
367
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32.4. Clock
Characteristics................................................................................................................36832.5.
System and Reset
Characteristics...........................................................................................
36932.6. SPI Timing
Characteristics.......................................................................................................
37032.7. Two-Wire Serial Interface
Characteristics................................................................................
37132.8. ADC
Characteristics.................................................................................................................37332.9.
Parallel Programming
Characteristics......................................................................................374
33. Typical Characteristics (TA = -40C to
85C).........................................................37733.1.
ATmega328 Typical
Characteristics.........................................................................................
377
34. Typical Characteristics (TA = -40C to
105C).......................................................40234.1.
ATmega328P Typical
Characteristics.......................................................................................402
35. Register
Summary.................................................................................................42735.1.
Note..........................................................................................................................................429
36. Instruction Set
Summary.......................................................................................
431
37. Packaging
Information...........................................................................................43637.1.
32-pin
32A................................................................................................................................43637.2.
32-pin
32M1-A..........................................................................................................................43737.3.
28-pin
28M1.............................................................................................................................
43837.4. 28-pin
28P3..............................................................................................................................438
38.
Errata.....................................................................................................................44038.1.
Errata
ATmega328/P................................................................................................................440
39. Datasheet Revision
History...................................................................................
44139.1. Rev. A
2/2018........................................................................................................................44139.2.
Pre Microchip
Revisions...........................................................................................................441
The Microchip Web
Site..............................................................................................
442
Customer Change Notification
Service........................................................................442
Customer
Support.......................................................................................................
442
Microchip Devices Code Protection
Feature...............................................................
442
Legal
Notice.................................................................................................................443
Trademarks.................................................................................................................
443
Quality Management System Certified by
DNV...........................................................444
Worldwide Sales and
Service......................................................................................445
ATmega328/P
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1. DescriptionThe AVR core combines a rich instruction set with
32 general purpose working registers. All the 32registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers tobe accessed in a single instruction
executed in one clock cycle. The resulting architecture is more
codeefficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The ATmega328/P provides the following features: 32Kbytes of
in-system programmable Flash with read-while-write capabilities,
1Kbytes EEPROM, 2Kbytes SRAM, 23 general purpose I/O lines, 32
generalpurpose working registers, Real Time Counter (RTC), three
flexible timer/counters with Compare modesand PWM, 1 serial
programmable USARTs , 1 byte-oriented 2-wire Serial Interface
(I2C), a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF
packages), a programmable watchdog timer with internaloscillator,
an SPI serial port, and six software selectable power saving modes.
The Idle mode stops theCPU while allowing the SRAM, timer/counters,
SPI port, and interrupt system to continue functioning.
ThePower-Down mode saves the register contents but freezes the
oscillator, disabling all other chip functionsuntil the next
interrupt or hardware Reset. In Power-Save mode, the asynchronous
timer continues to run,allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC NoiseReduction
mode stops the CPU and all I/O modules except asynchronous timer
and ADC to minimizeswitching noise during ADC conversions. In
Standby mode, the crystal/resonator oscillator is runningwhile the
rest of the device is sleeping. This allows very fast start-up
combined with low-powerconsumption. In Extended Standby mode, both
the main oscillator and the asynchronous timer continueto run.
Microchip offers the QTouch library for embedding capacitive
touch buttons, sliders and wheelsfunctionality into AVR
microcontrollers. The patented charge-transfer signal acquisition
offers robustsensing and includes fully debounced reporting of
touch keys and includes Adjacent Key Suppression(AKS) technology
for unambiguous detection of key events. The easy-to-use QTouch
Suite toolchainallows you to explore, develop and debug your own
touch applications.
The device is manufactured using Microchips high density
nonvolatile memory technology. The on-chipISP Flash allows the
program memory to be reprogrammed in-system through an SPI serial
interface, bya conventional nonvolatile memory programmer, or by an
on-chip boot program running on the AVR core.The boot program can
use any interface to download the application program in the
application Flashmemory. Software in the boot Flash section will
continue to run while the application Flash section isupdated,
providing true read-while-write operation. By combining an 8-bit
RISC CPU with in-system self-programmable Flash on a monolithic
chip, the ATmega328/P is a powerful microcontroller that provides
ahighly flexible and cost effective solution to many embedded
control applications.
The ATmega328/P is supported with a full suite of program and
system development tools including: Ccompilers, macro assemblers,
program debugger/simulators, in-circuit emulators, and evaluation
kits.
ATmega328/PDescription
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2. Configuration SummaryFeatures ATmega328/P
Pin Count 28/32
Flash (Bytes) 32K
SRAM (Bytes) 2K
EEPROM (Bytes) 1K
General Purpose I/O Lines 23
SPI 2
TWI (I2C) 1
USART 1
ADC 10-bit 15 kSPS
ADC Channels 8
8-bit Timer/Counters 2
16-bit Timer/Counters 1
ATmega328/PConfiguration Summary
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3. Ordering Information
3.1 ATmega328
Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1)
Operational Range
20 1.8 - 5.5
ATmega328-AUATmega328-AUR(5)ATmega328-MMH(4)ATmega328-MMHR(4)(5)ATmega328-MUATmega328-MUR(5)ATmega328-PU
32A32A28M128M132M1-A32M1-A28P3
Industrial(-40C to 85C)
Note:1. This device can also be supplied in wafer form. Please
contact your local Microchip sales office for
detailed ordering information and minimum quantities.2. Pb-free
packaging, complies to the European Directive for Restriction of
Hazardous Substances
(RoHS directive). Also Halide free and fully Green.3. Please
refer to Speed Grades for Speed vs. VCC4. Tape & Reel.5. NiPdAu
Lead Finish.
Package Type
28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat
No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 28-lead, 0.300 Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat
No-Lead/Micro Lead Frame Package (QFN/MLF)
32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
3.2 ATmega328P
Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1)
Operational Range
20 1.8 - 5.5
ATmega328P-AUATmega328P-AUR(5)ATmega328P-MMH(4)ATmega328P-MMHR(4)(5)ATmega328P-MU
32A32A28M128M132M1-A
Industrial(-40C to 85C)
ATmega328/POrdering Information
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Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1)
Operational Range
ATmega328P-MUR(5)ATmega328P-PU
32M1-A28P3
ATmega328P-ANATmega328P-ANR(5)ATmega328P-MNATmega328P-MNR(5)ATmega328P-PN
32A32A32M1-A32M1-A28P3
Industrial(-40C to 105C)
Note:1. This device can also be supplied in wafer form. Please
contact your local Microchip sales office for
detailed ordering information and minimum quantities.2. Pb-free
packaging, complies to the European Directive for Restriction of
Hazardous Substances
(RoHS directive). Also Halide free and fully Green.3. Please
refer to Speed Grades for Speed vs. VCC4. Tape & Reel.5. NiPdAu
Lead Finish.
Package Type
28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat
No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 28-lead, 0.300 Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat
No-Lead/Micro Lead Frame Package (QFN/MLF)
32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
ATmega328/POrdering Information
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4. Block DiagramFigure 4-1.Block Diagram
CPU
USART
ADCADC[7:0]AREF
RxD0TxD0XCK0
I/OPORTS
DATABUS
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASHNVM
programming
debugWire
IN/OUT
DATABUS
TC 0(8-bit)
SPI
ACAIN0AIN1
ADCMUX
EEPROM
EEPROMIF
TC 1(16-bit)
OC1A/BT1
ICP1
TC 2(8-bit async)
TWI SDA0SCL0
InternalReference
Watchdog Timer
Power management
and clock control
VCC
GND
Clock generation8MHz
Calib RC
128kHz int osc
32.768kHz XOSC
External clock
Power SupervisionPOR/BOD &
RESET
XTAL2 / TOSC2
RESET
XTAL1 /TOSC1
16MHz LP XOSC
PCINT[23:0]INT[1:0]
T0OC0AOC0B
MISO0MOSI0SCK0SS0
OC2AOC2B
PB[7:0]PC[6:0]PD[7:0]
ADC6,ADC7,PC[5:0]AREF
PD[7:0], PC[6:0], PB[7:0]PD3, PD2
PB1, PB2PD5PB0
PB3PD3
PD4PD6PD5
PB4PB3PB5PB2
PD6PD7
ADC6, ADC7PC[5:0]PD0PD1PD4 PC4PC5
ATmega328/PBlock Diagram
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5. Pin Configurations
5.1 PinoutFigure 5-1.28-pin PDIP
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
(PCINT14/RESET) PC6
(PCINT16/RXD) PD0
(PCINT17/TXD) PD1
(PCINT18/INT0) PD2
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/OC2A/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ATmega328/PPin Configurations
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Figure 5-2.28-pin MLF Top View
1
2
3
4
5
6
7
8 9 10 11 12 13 14
PD2
(INT0
/PC
INT1
8)
PD1
(TXD
/PC
INT1
7)
PD0
(RXD
/PC
INT1
6)
PC6
(RES
ET/P
CIN
T14)
PC5
(AD
C5/
SCL/
PCIN
T13)
PC4
(AD
C4/
SDA/
PCIN
T12)
PC3
(AD
C3/
PCIN
T11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
(PCI
NT2
2/O
C0A
/AIN
0) P
D6
(PCI
NT2
3/A
IN1)
PD
7
(PCI
NT0
/CLK
O/IC
P1) P
B0
(PCI
NT1
/OC1
A) P
B1
(PCI
NT2
/SS/
OC1
B) P
B2
(PCI
NT3
/OC2
A/M
OSI
) PB3
(PCI
NT4
/MIS
O) P
B4
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
Bottom pad should be soldered to ground
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
21
20
19
18
17
16
15
28 27 26 25 24 23 22
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Figure 5-3.32-pin TQFP Top View
1
2
3
4
32 31 30 29 28 27 26
5
6
7
8
24
23
22
21
20
19
18
1725
9 10 11 12 13 14 15 16
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
PD2
(INT0
/PCI
NT18
)
PD1
(TXD
/PCI
NT17
)
PD0
(RXD
/PCI
NT16
)
PC6
(RES
ET/P
CINT
14)
PC5
(ADC
5/SC
L/PC
INT1
3)
PC4
(ADC
4/SD
A/PC
INT1
2)
PC3
(ADC
3/PC
INT1
1)
PC2
(ADC
2/PC
INT1
0)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
(PC
INT2
1/O
C0B
/T1)
PD
5
(PC
INT2
2/O
C0A
/AIN
0) P
D6
(PC
INT2
3/AI
N1)
PD
7
(PC
INT0
/CLK
O/IC
P1) P
B0
(PC
INT1
/OC
1A) P
B1
(PC
INT2
/SS/
OC
1B) P
B2
(PC
INT3
/OC
2A/M
OSI
) PB3
(PC
INT4
/MIS
O) P
B4
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Figure 5-4.32-pin MLF Top View
1
2
3
4
32 31 30 29 28 27 26
5
6
7
8
24
23
22
21
20
19
18
17
25
9 10 11 12 13 14 15 16
PD2
(INT0
/PC
INT1
8)
PD1
(TXD
/PC
INT1
7)
PD0
(RXD
/PC
INT1
6)
PC6
(RES
ET/P
CIN
T14)
PC5
(AD
C5/
SCL/
PCIN
T13)
PC4
(AD
C4/
SDA/
PCIN
T12)
PC3
(AD
C3/
PCIN
T11)
PC2
(AD
C2/
PCIN
T10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
(PCI
NT2
1/O
C0B/
T1) P
D5
(PCI
NT2
2/O
C0A
/AIN
0) P
D6
(PCI
NT2
3/A
IN1)
PD
7
(PCI
NT0
/CLK
O/IC
P1) P
B0
(PCI
NT1
/OC1
A) P
B1
(PCI
NT2
/SS/
OC1
B) P
B2
(PCI
NT3
/OC2
A/M
OSI
) PB3
(PCI
NT4
/MIS
O) P
B4
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
Bottom pad should be soldered to ground
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
5.2 Pin Descriptions
5.2.1 VCCDigital supply voltage pin.
5.2.2 GNDGround.
5.2.3 Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2Port B is an 8-bit
bi-directional I/O port with internal pull-up resistors (selected
for each pin). The Port Boutput buffers have symmetrical drive
characteristics with both high sink and source capability. As
inputs,Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The PortB pins are
tri-stated during a Reset condition even if the clock is not
running.
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Depending on the clock selection fuse settings, PB6 can be used
as input to the inverting oscillatoramplifier and input to the
internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used
as output from the inverting oscillatoramplifier.
If the internal calibrated RC oscillator is used as chip clock
source, PB[7:6] is used as TOSC[2:1] input forthe asynchronous
timer/counter2 if the AS2 bit in ASSR is set.
5.2.4 Port C (PC[5:0])Port C is a 7-bit bi-directional I/O port
with internal pull-up resistors (selected for each pin). The
PC[5:0]output buffers have symmetrical drive characteristics with
both high sink and source capability. As inputs,Port C pins that
are externally pulled low will source current if the pull-up
resistors are activated. The PortC pins are tri-stated during a
Reset condition even if the clock is not running.
5.2.5 PC6/RESETIf the RSTDISBL fuse is programmed, PC6 is used
as an I/O pin. Note that the electrical characteristics ofPC6
differ from those of the other pins of Port C.
If the RSTDISBL fuse is unprogrammed, PC6 is used as a Reset
input. A low level on this pin for longerthan the minimum pulse
length will generate a Reset, even if the clock is not running.
Shorter pulses arenot guaranteed to generate a Reset.
The various special features of Port C are elaborated in the
Alternate Functions of Port C section.
5.2.6 Port D (PD[7:0])Port D is an 8-bit bi-directional I/O port
with internal pull-up resistors (selected for each pin). The Port
Doutput buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs,Port D pins that are
externally pulled low will source current if the pull-up resistors
are activated. The PortD pins are tri-stated during a Reset
condition even if the clock is not running.
5.2.7 AVCCAVCC is the supply voltage pin for the A/D Converter
(ADC), PC[3:0], and PE[3:2]. It should be externallyconnected to
VCC, even if the ADC is not used. If the ADC is used, it should be
connected to VCC througha low-pass filter. Note that PC[6:4] use
digital supply voltage, VCC.
5.2.8 AREFAREF is the analog reference pin for the A/D
Converter.
5.2.9 ADC[7:6]In the TQFP and VFQFN package, ADC[7:6] serve as
analog inputs to the A/D converter. These pins arepowered by the
analog supply and serve as 10-bit ADC channels.
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6. I/O MultiplexingEach pin is by default controlled by the PORT
as a general purpose I/O and alternatively it can beassigned to one
of the peripheral functions.
The following table describes the peripheral signals multiplexed
to the PORT I/O pins.
Table 6-1.PORT Function Multiplexing
(32-pinMLF/TQFP)Pin#
(28-pinMLF) Pin#
(28-pinPIPD) Pin#
PAD EXTINT PCINT ADC/AC OSC T/C #0 T/C#1
USART 0 I2C 0 SPI 0
1 1 5 PD3 INT1 PCINT19 OC2B
2 2 6 PD4 PCINT20 T0 XCK0
4 3 7 VCC
3 4 8 GND
6 - - VCC
5 - - GND
7 5 9 PB6 PCINT6 XTAL1/TOSC1
8 6 10 PB7 PCINT7 XTAL2/TOSC2
9 7 11 PD5 PCINT21 OC0B T1
10 8 12 PD6 PCINT22 AIN0 OC0A
11 9 13 PD7 PCINT23 AIN1
12 10 14 PB0 PCINT0 CLKO ICP1
13 11 15 PB1 PCINT1 OC1A
14 12 16 PB2 PCINT2 OC1B SS0
15 13 17 PB3 PCINT3 OC2A MOSI0
16 14 18 PB4 PCINT4 MISO0
17 15 19 PB5 PCINT5 SCK0
18 16 20 AVCC
19 - - ADC6 ADC6
20 17 21 AREF
21 18 22 GND
22 - - ADC7 ADC7
23 19 13 PC0 PCINT8 ADC0
24 20 24 PC1 PCINT9 ADC1
25 21 25 PC2 PCINT10 ADC2
26 22 26 PC3 PCINT11 ADC3
27 23 27 PC4 PCINT12 ADC4 SDA0
28 24 28 PC5 PCINT13 ADC5 SCL0
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(32-pinMLF/TQFP)Pin#
(28-pinMLF) Pin#
(28-pinPIPD) Pin#
PAD EXTINT PCINT ADC/AC OSC T/C #0 T/C#1
USART 0 I2C 0 SPI 0
29 25 1 PC6/RESET PCINT14
30 26 2 PD0 PCINT16 RXD0
31 27 3 PD1 PCINT17 TXD0
32 28 4 PD2 INT0 PCINT18
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7. ResourcesA comprehensive set of development tools,
application notes, and datasheets are available for downloadon
http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.
ATmega328/PResources
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8. Data RetentionReliability qualification results show that the
projected data retention failure rate is much less than 1 PPMover
20 years at 85C.
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9. About Code ExamplesThis documentation contains simple code
examples that briefly show how to use various parts of thedevice.
These code examples assume that the part specific header file is
included before compilation. Beaware that not all C compiler
vendors include bit definitions in the header files and interrupt
handling in Cis compiler dependent. Confirm with the C compiler
documentation for more details.
For I/O registers located in extended I/O map, IN, OUT, SBIS,
SBIC, CBI, and SBI instructions must bereplaced with instructions
that allow access to extended I/O. Typically LDS and STS combined
with SBRS,SBRC, SBR, and CBR.
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10. Capacitive Touch Sensing
10.1 QTouch LibraryThe QTouch library provides a simple to use
solution to realize touch sensitive interfaces on most AVR
microcontrollers. The QTouch library includes support for the
QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the
appropriate QTouch library for the AVRmicrocontroller. This is done
by using a simple set of APIs to define the touch channels and
sensors, andthen calling the touch sensing APIs to retrieve the
channel information and determine the touch sensorstates.
The QTouch library is FREE and downloadable from QTouch Library
. For implementation details andother information, refer to the
QTouch Library User Guide, also available for download from the
Microchipwebsite.
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http://www.microchip.com/developmenttools/productdetails.aspx?partno=atmel+qtouch+library
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11. AVR CPU Core
11.1 OverviewThis section discusses the AVR core architecture in
general. The main function of the CPU core is toensure correct
program execution. The CPU must, therefore, be able to access
memories, performcalculations, control peripherals, and handle
interrupts.
Figure 11-1.Block Diagram of the AVR Architecture
Register file
Flash program memory
Program counter
Instruction register
Instruction decode
Data memory
ALUStatus register
R0R1R2R3R4R5R6R7R8R9
R10R11R12R13R14R15R16R17R18R19R20R21R22R23R24R25
R26 (XL)R27 (XH)R28 (YL)R29 (YH)R30 (ZL)R31 (ZH)
Stack pointer
In order to maximize performance and parallelism, the AVR uses a
Harvard architecture with separatememories and buses for program
and data. Instructions in the program memory are executed with
asingle level pipelining. While one instruction is being executed,
the next instruction is pre-fetched from theprogram memory. This
concept enables instructions to be executed in every clock cycle.
The programmemory is In-System Reprogrammable Flash memory.
The fast-access register file contains 32 x 8-bit general
purpose working registers with a single clockcycle access time.
This allows single-cycle Arithmetic Logic Unit (ALU) operation. In
a typical ALUoperation, two operands are output from the register
file, the operation is executed, and the result isstored back in
the register file in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect
address register pointers for data spaceaddressing enabling
efficient address calculations. One of these address pointers can
be used as an
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address pointer for lookup tables in Flash program memory. These
added function registers are the 16-bitX-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between
registers or between a constant and aregister. Single register
operations can also be executed in the ALU. After an arithmetic
operation, theStatus register is updated to reflect information
about the result of the operation.
Program flow is provided by conditional and unconditional jump
and call instructions, able to directlyaddress the whole address
space. Most AVR instructions have a single 16-bit word format.
Everyprogram memory address contains a 16- or 32-bit
instruction.
Program Flash memory space is divided into two sections, the
Boot Program section and the ApplicationProgram section. Both
sections have dedicated Lock bits for write and read/write
protection. The SPMinstruction that writes into the Application
Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address
Program Counter (PC) is stored on the Stack.The Stack is
effectively allocated in the general data SRAM, and consequently,
the Stack size is onlylimited by the total SRAM size and the usage
of the SRAM. All user programs must initialize the StackPointer
(SP) in the Reset routine (before subroutines or interrupts are
executed). The SP is read/writeaccessible in the I/O space. The
data SRAM can easily be accessed through the five different
addressingmodes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and
regular memory maps.
A flexible interrupt module has its control registers in the I/O
space with an additional global interruptenable bit in the Status
register. All interrupts have a separate interrupt vector in the
interrupt vector table.The interrupts have priority in accordance
with their interrupt vector position. The lower the interruptvector
address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral
functions as Control registers, SPI, andother I/O functions. The
I/O memory can be accessed directly, or as the data space locations
followingthose of the register file, 0x20 - 0x5F. In addition, this
device has extended I/O space from 0x60 - 0xFF inSRAM where only
the ST/STS/STD and LD/LDS/LDD instructions can be used.
11.2 Arithmetic Logic Unit (ALU)The high-performance AVR ALU
operates in direct connection with all the 32 general purpose
workingregisters. Within a single clock cycle, arithmetic
operations between general purpose registers orbetween a register
and an immediate are executed. The ALU operations are divided into
three maincategories: arithmetic, logical, and bit-functions. Some
implementations of the architecture provide apowerful multiplier
supporting both signed/unsigned multiplication and fractional
format. See InstructionSet Summary section for a detailed
description.
Related LinksInstruction Set Summary
11.3 Status RegisterThe Status register contains information
about the result of the most recently executed
arithmeticinstruction. This information can be used for altering
program flow in order to perform conditionaloperations. The Status
register is updated after all ALU operations, as specified in the
instruction setreference. This will in many cases remove the need
for using the dedicated compare instructions,resulting in faster
and more compact code.
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The Status register is not automatically stored when entering an
interrupt routine and restored whenreturning from an interrupt.
This must be handled by software.
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11.3.1 Status Register
Name: SREGOffset: 0x5FReset: 0x00Property: When addressing as
I/O Register: address offset is 0x3F
When addressing I/O registers as data space using LD and ST
instructions, the provided offset must beused. When using the I/O
specific commands IN and OUT, the offset is reduced by 0x20,
resulting in anI/O address offset within 0x00 - 0x3F.
Bit 7 6 5 4 3 2 1 0 I T H S V N Z C
Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 IGlobal Interrupt EnableThe global interrupt enable bit
must be set for the interrupts to be enabled. The individual
interrupt enablecontrol is then performed in separate control
registers. If the Global Interrupt Enable register is cleared,none
of the interrupts are enabled independent of the individual
interrupt enable settings. The I-bit iscleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to
enablesubsequent interrupts. The I-bit can also be set and cleared
by the application with the SEI and CLIinstructions, as described
in the instruction set reference.
Bit 6 TCopy StorageThe bit copy instructions BLD (Bit LoaD) and
BST (Bit STore) use the T-bit as source or destination forthe
operated bit. A bit from a register in the register file can be
copied into T by the BST instruction, and abit in T can be copied
into a bit in a register in the register file by the BLD
instruction.
Bit 5 HHalf Carry FlagThe half carry flag H indicates a half
carry in some arithmetic operations. Half carry flag is useful in
BCDarithmetic. See the Instruction Set Description for detailed
information.
Bit 4 SSign Flag, S = N V
The S-bit is always an exclusive or between the negative flag N
and the twos complement overflow flagV. See the Instruction Set
Description for detailed information.
Bit 3 VTwos Complement Overflow FlagThe twos complement overflow
flag V supports twos complement arithmetic. See the Instruction
SetDescription for detailed information.
Bit 2 NNegative FlagThe negative flag N indicates a negative
result in an arithmetic or logic operation. See the Instruction
SetDescription for detailed information.
Bit 1 ZZero FlagThe zero flag Z indicates a zero result in an
arithmetic or logic operation. See the Instruction SetDescription
for detailed information.
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Bit 0 CCarry FlagThe carry flag C indicates a carry in an
arithmetic or logic operation. See the Instruction Set
Descriptionfor detailed information.
11.4 General Purpose Register FileThe register file is optimized
for the AVR Enhanced RISC instruction set. In order to achieve the
requiredperformance and flexibility, the following input/output
schemes are supported by the register file:
One 8-bit output operand and one 8-bit result input Two 8-bit
output operands and one 8-bit result input Two 8-bit output
operands and one 16-bit result input One 16-bit output operand and
one 16-bit result input
Figure 11-2.AVR CPU General Purpose Working Registers7 0
Addr.
R0 0x00
R1 0x01
R2 0x02
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
Most of the instructions operating on the register file have
direct access to all registers, and most of themare single cycle
instructions. As shown in the figure, each register is also
assigned a data memoryaddress, mapping them directly into the first
32 locations of the user data space. Although not beingphysically
implemented as SRAM locations, this memory organization provides
great flexibility in accessof the registers, as the X-, Y-, and
Z-pointer registers can be set to index any register in the
file.
11.4.1 The X-register, Y-register, and Z-registerThe registers
R26...R31 have some added functions to their general purpose usage.
These registers are16-bit address pointers for indirect addressing
of the data space. The three indirect address registers X,Y, and Z
are defined as described in the figure.
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Figure 11-3.The X-, Y-, and Z-registers15 XH XL 0
X-register 7 0 7 0
R27 R26
15 YH YL 0
Y-register 7 0 7 0
R29 R28
15 ZH ZL 0
Z-register 7 0 7 0
R31 R30
In the different addressing modes, these address registers have
functions as fixed displacement,automatic increment, and automatic
decrement (see the instruction set reference for details).
Related LinksInstruction Set Summary
11.5 Stack PointerThe stack is mainly used for storing temporary
data, local variables, and return addresses after interruptsand
subroutine calls. The stack is implemented as growing from higher
to lower memory locations. TheStack Pointer register always points
to the top of the stack.
The stack pointer points to the data SRAM stack area where the
subroutine and interrupt stacks arelocated. A stack PUSH command
will decrease the stack pointer. The stack in the data SRAM must
bedefined by the program before any subroutine calls are executed
or interrupts are enabled. Initial stackpointer value equals the
last address of the internal SRAM and the stack pointer must be set
to pointabove start of the SRAM. See the table for stack pointer
details.
Table 11-1.Stack Pointer Instructions
Instruction Stack Pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL
Decremented by 2 Return address is pushed onto the stack with a
subroutine call orinterrupt
POP Incremented by 1 Data is popped from the stack
RET
RETI
Incremented by 2 Return address is popped from the stack with
return from subroutine orreturn from interrupt
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The AVR stack pointer is implemented as two 8-bit registers in
the I/O space. The number of bits actuallyused is implementation
dependent. Note that the data space in some implementations of the
AVRarchitecture is so small that only SPL is needed. In this case,
the SPH register will not be present.
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11.5.1 Stack Pointer Register Low and High byte
Name: SPL and SPHOffset: 0x5DReset: 0x4FFProperty: When
addressing I/O registers as data space the offset address is
0x3D
The SPL and SPH register pair represents the 16-bit value, SP.
The low byte [7:0] (suffix L) is accessibleat the original offset.
The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
For more details onreading and writing 16-bit registers, refer to
Accessing 16-bit Timer/Counter Registers.
When using the I/O specific commands IN and OUT, the I/O
addresses 0x00 - 0x3F must be used. Whenaddressing I/O registers as
data space using LD and ST instructions, 0x20 must be added to
these offsetaddresses.
Bit 15 14 13 12 11 10 9 8 SP11 SP10 SP9 SP8
Access R R R R RW RW RW RW Reset 0 0 0 0 0 1 0 0
Bit 7 6 5 4 3 2 1 0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 SPStack Pointer
RegisterSPL and SPH are combined into SP.
Related LinksAccessing 16-bit Timer/Counter Registers
11.6 Instruction Execution TimingThis section describes the
general access timing concepts for instruction execution. The AVR
CPU isdriven by the CPU clock clkCPU, directly generated from the
selected clock source for the chip. No internalclock division is
used. The figure below shows the parallel instruction fetches and
instruction executionsenabled by the Harvard architecture and the
fast-access register file concept. This is the basic
pipeliningconcept to obtain up to 1 MIPS per MHz with the
corresponding unique results for functions per cost,functions per
clocks, and functions per power unit.
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Figure 11-4.The Parallel Instruction Fetches and Instruction
Executions
clk
1st Instruction Fetch1st Instruction Execute
2nd Instruction Fetch2nd Instruction Execute
3rd Instruction Fetch3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
The following figure shows the internal timing concept for the
register file. In a single clock cycle, an ALUoperation using two
register operands is executed and the result is stored back to the
destination register.
Figure 11-5.Single Cycle ALU Operation
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
11.7 Reset and Interrupt HandlingThe AVR provides several
different interrupt sources. These interrupts and the separate
Reset vectoreach have a separate program vector in the program
memory space. All interrupts are assignedindividual enable bits,
which must be written logic one together with the global interrupt
enable bit in theStatus register in order to enable the interrupt.
Depending on the program counter value, interrupts maybe
automatically disabled when Boot Lock bits BLB02 or BLB12 are
programmed. This feature improvessoftware security.
The lowest addresses in the program memory space are by default
defined as the Reset and interruptvectors. They have determined
priority levels: The lower the address the higher is the priority
level.RESET has the highest priority, and next is INT0 the External
Interrupt Request 0. The interrupt vectorscan be moved to the start
of the boot Flash section by setting the IVSEL bit in the MCU
Control Register(MCUCR). The Reset vector can be moved to the start
of the boot Flash section by programming theBOOTRST Fuse.
When an interrupt occurs, the global interrupt enable I-bit is
cleared and all interrupts are disabled. Theuser software can write
logic one to the I-bit to enable nested interrupts. All enabled
interrupts can theninterrupt the current interrupt routine. The
I-bit is automatically set when a return from interrupt instruction
RETI is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the interrupt
flag. For these interrupts, the programcounter is vectored to the
actual interrupt vector in order to execute the interrupt handling
routine, and
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hardware clears the corresponding interrupt flag. Interrupt
flags can be cleared by writing a logic one tothe flag bit
position(s) to be cleared. If an interrupt condition occurs while
the corresponding interruptenable bit is cleared, the interrupt
flag will be set and remembered until the interrupt is enabled, or
theflag is cleared by software. Similarly, if one or more interrupt
conditions occur while the global interruptenable bit is cleared,
the corresponding interrupt flag(s) will be set and remembered
until the globalinterrupt enable bit is set and will then be
executed by order of priority.
The second type of interrupts will trigger as long as the
interrupt condition is present. These interrupts donot necessarily
have interrupt flags. If the interrupt condition disappears before
the interrupt is enabled,the interrupt will not be triggered. When
the AVR exits from an interrupt, it will always return to the
mainprogram and execute one more instruction before any pending
interrupt is served.
The Status register is not automatically stored when entering an
interrupt routine, nor restored whenreturning from an interrupt
routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the
interrupts will be immediately disabled. Nointerrupt will be
executed after the CLI instruction, even if it occurs
simultaneously with the CLIinstruction. The following example shows
how this can be used to avoid interrupts during the timedEEPROM
write sequence.
Assembly Code Example(1)
in r16, SREG ; store SREG valuecli ; disable interrupts during
timed sequencesbi EECR, EEMPE ; start EEPROM writesbi EECR, EEPEout
SREG, r16 ; restore SREG value (I-bit)
C Code Example(1)
char cSREG;cSREG = SREG; /* store SREG value *//* disable
interrupts during timed sequence */_CLI();EECR |= (1
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11.7.1 Interrupt Response TimeThe interrupt execution response
for all the enabled AVR interrupts is four clock cycles minimum.
Afterfour clock cycles, the program vector address for the actual
interrupt handling routine is executed. Duringthis four clock cycle
period, the program counter is pushed onto the stack. The vector is
normally a jumpto the interrupt routine, and this jump takes three
clock cycles. If an interrupt occurs during execution of
amulti-cycle instruction, this instruction is completed before the
interrupt is served. If an interrupt occurswhen the microcontroller
(MCU) is in Sleep mode, the interrupt execution response time is
increased byfour clock cycles. This increase comes in addition to
the start-up time from the selected Sleep mode. Areturn from an
interrupt handling routine takes four clock cycles. During these
four clock cycles, theprogram counter (two bytes) is popped back
from the Stack, the Stack Pointer is incremented by two, andthe
I-bit in SREG is set.
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12. AVR Memories
12.1 OverviewThis section describes the different memory types
in the device. The AVR architecture has two mainmemory spaces, the
Data Memory and the Program Memory space. In addition, the device
features anEEPROM Memory for data storage. All memory spaces are
linear and regular.
12.2 In-System Reprogrammable Flash Program MemoryThe
ATmega328/P contains 32Kbytes on-chip in-system reprogrammable
Flash memory for programstorage. Since all AVR instructions are 16
or 32 bits wide, the Flash is organized as 16 K x 16. Forsoftware
security, the Flash Program memory space is divided into two
sections - Boot Loader Sectionand Application Program Section in
the device .
The ATmega328/P Program Counter (PC) is 14 bits wide, thus
addressing the 16 K program memorylocations. The operation of the
Boot Program section and associated Boot Lock bits for
softwareprotection are described in detail in Boot Loader Support
Read-While-Write Self-Programming. Refer toMemory Programming for
the description of Flash data serial downloading using the SPI
pins.
Constant tables can be allocated within the entire program
memory address space, using the LoadProgram Memory (LPM)
instruction.
Timing diagrams for instruction fetch and execution are
presented in Instruction Execution Timing.
Figure 12-1.Program Memory Map ATmega328/P
0x0000
0x3FFF
Program Memory
Application Flash Section
Boot Flash Section
Related LinksBoot Loader Support Read-While-Write
Self-programming (BTLDR)Memory Programming (MEMPROG)Instruction
Execution Timing
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12.3 SRAM Data MemoryThe following figure shows how the device
SRAM memory is organized.
The device is a complex microcontroller with more peripheral
units than can be supported within the 64locations reserved in the
Opcode for the IN and OUT instructions. For the extended I/O space
from 0x60 -0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The lower 2303 data memory locations address both the register
file, the I/O memory, extended I/Omemory, and the internal data
SRAM. The first 32 locations address the register file, the next 64
locationthe standard I/O memory, then 160 locations of extended I/O
memory, and the next 2 K locations addressthe internal data
SRAM.
The five different addressing modes for the data memory cover:
Direct
The direct addressing reaches the entire data space. Indirect
with Displacement
The indirect with displacement mode reaches 63 address locations
from the base addressgiven by the Y- or Z-register.
Indirect In the register file, registers R26 to R31 feature the
indirect addressing pointer registers.
Indirect with Pre-decrement The address registers X, Y, and Z
are decremented.
Indirect with Post-increment The address registers X, Y, and Z
are incremented.
The 32 general purpose working registers, 64 I/O registers, 160
extended I/O registers, and the 2K bytesof internal data SRAM in
the device are all accessible through all these addressing
modes.
Figure 12-2.Data Memory Map with 2048 Byte Internal Data
SRAMLoad/StoreIN/OUT
0x0000 0x001F
0x0100
0x08FF
160 Ext I/O registers
64 I/O registers
32 registers
Internal SRAM(2048x8)
0x0020 0x005F
0x0060 0x00FF
0x0000 0x001F
12.3.1 Data Memory Access TimesThe internal data SRAM access is
performed in two clkCPU cycles as described in the following
Figure.
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Figure 12-3.On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address Address valid
T1 T2 T3
Compute Address
Rea
dW
rite
CPU
Memory Access Instruction Next Instruction
12.4 EEPROM Data MemoryThe ATmega328/P contains 1KB of data
EEPROM memory. It is organized as a separate data space, inwhich
single bytes can be read and written. The access between the EEPROM
and the CPU is describedin the following, specifying the EEPROM
Address registers, the EEPROM Data register, and theEEPROM Control
register.
See the related links for a detailed description on EEPROM
Programming in SPI or Parallel Programmingmode.
Related LinksMemory Programming (MEMPROG)
12.4.1 EEPROM Read/Write AccessThe EEPROM access registers are
accessible in the I/O space.
The write access time for the EEPROM is given in Table 12-2. A
self-timing function, however, lets theuser software detect when
the next byte can be written. If the user code contains
instructions that writethe EEPROM, some precautions must be taken.
In heavily filtered power supplies, VCC is likely to rise orfall
slowly on power-up/down. This causes the device for some period of
time to run at a voltage lowerthan specified as a minimum for the
clock frequency used. Refer to Preventing EEPROM Corruption
fordetails on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific
write procedure must be followed. Refer tothe description of the
EEPROM Control register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles
before the next instruction isexecuted. When the EEPROM is written,
the CPU is halted for two clock cycles before the next
instructionis executed.
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12.4.2 Preventing EEPROM CorruptionDuring periods of low VCC,
the EEPROM data can be corrupted because the supply voltage is too
low forthe CPU and the EEPROM to operate properly. These issues are
the same as for board level systemsusing EEPROM, and the same
design solutions should be applied.
An EEPROM data corruption can be caused by two situations when
the voltage is too low. First, a regularwrite sequence to the
EEPROM requires a minimum voltage to operate correctly. Secondly,
the CPU itselfcan execute instructions incorrectly, if the supply
voltage is too low.
EEPROM data corruption can easily be avoided by following this
design recommendation:
Keep the AVR RESET active (low) during periods of insufficient
power supply voltage. This can be doneby enabling the internal
Brown-out Detector (BOD). If the detection level of the internal
BOD does notmatch the needed detection level, an external low VCC
Reset protection circuit can be used. If a Resetoccurs while a
write operation is in progress, the write operation will be
completed provided that thepower supply voltage is sufficient.
12.5 I/O MemoryThe I/O space definition of the device is shown
in the Register Summary.
All device I/Os and peripherals are placed in the I/O space. All
I/O locations may be accessed by theLD/LDS/LDD and ST/STS/STD
instructions, transferring data between the 32 general purpose
workingregisters and the I/O space. I/O registers within the
address range 0x00-0x1F are directly bit-accessibleusing the SBI
and CBI instructions. In these registers, the value of single bits
can be checked by usingthe SBIS and SBIC instructions.
When using the I/O specific commands IN and OUT, the I/O
addresses 0x00-0x3F must be used. Whenaddressing I/O registers as
data space using LD and ST instructions, 0x20 must be added to
theseaddresses. The device is a complex microcontroller with more
peripheral units than can be supportedwithin the 64 locations
reserved in Opcode for the IN and OUT instructions. For the
extended I/O spacefrom 0x60..0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be
written to zero if accessed. Reserved I/Omemory addresses should
never be written.
Some of the status flags are cleared by writing a '1' to them;
this is described in the flag descriptions.Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the
specified bit, andcan, therefore, be used on registers containing
such status flags. The CBI and SBI instructions work withregisters
0x00-0x1F only.
The I/O and peripherals control registers are explained in later
sections.
Related LinksMemory Programming (MEMPROG)Register
SummaryInstruction Set Summary
12.5.1 General Purpose I/O RegistersThe device contains three
general purpose I/O registers; General purpose I/O register 0/1/2
(GPIOR0/1/2). These registers can be used for storing any
information, and they are particularly useful for storingglobal
variables and status flags. General purpose I/O registers within
the address range 0x00 - 0x1F aredirectly bit-accessible using the
SBI, CBI, SBIS, and SBIC instructions.
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12.6 Register Description
12.6.1 Accessing 16-Bit RegistersThe AVR data bus is 8-bits
wide, so accessing 16-bit registers requires atomic operations.
Theseregisters must be byte-accessed using two read or write
operations. 16-bit registers are connected to the8-bit bus and a
temporary register using a 16-bit bus.
For a write operation, the high byte of the 16-bit register must
be written before the low byte. The highbyte is then written into
the temporary register. When the low byte of the 16-bit register is
written, thetemporary register is copied into the high byte of the
16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must
be read before the high byte. When the lowbyte register is read by
the CPU, the high byte of the 16-bit register is copied into the
temporary registerin the same clock cycle as the low byte is read.
When the high byte is read, it is then read from thetemporary
register.
This ensures that the low and high bytes of 16-bit registers are
always accessed simultaneously whenreading or writing the
register.
Interrupts can corrupt the timed sequence if an interrupt is
triggered and accesses the same 16-bitregister during an atomic
16-bit read/write operation. To prevent this, interrupts can be
disabled whenwriting or reading 16-bit registers.
The temporary registers can be read and written directly from
user software.
Note: For more information, refer to Accessing 16-bit
Timer/Counter registers.
Related LinksAccessing 16-bit Timer/Counter Registers
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12.6.2 EEPROM Address Register Low and High Byte
Name: EEARL and EEARHOffset: 0x41 [ID-000004d0]Reset:
0xXXProperty: When addressing as I/O Register: address offset is
0x21
The EEARL and EEARH register pair represents the 16-bit value,
EEAR. The low byte [7:0] (suffix L) isaccessible at the original
offset. The high byte [15:8] (suffix H) can be accessed at offset +
0x01. Formore details on reading and writing 16-bit registers,
refer to accessing 16-bit registers in the sectionabove.
When addressing I/O registers as data space using LD and ST
instructions, the provided offset must beused. When using the I/O
specific commands IN and OUT, the offset is reduced by 0x20,
resulting in anI/O address offset within 0x00 - 0x3F.
Bit 15 14 13 12 11 10 9 8 EEAR[9:8]
Access R/W R/W Reset x x
Bit 7 6 5 4 3 2 1 0 EEAR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x
Bits 9:0 EEAR[9:0]EEPROM AddressThe EEPROM Address Registers,
EEARH and EEARL, specify the EEPROM address in the 1KBEEPROM space.
The EEPROM data bytes are addressed linearly between 0 and
255/511/511. The initialvalue of EEAR is undefined. A proper value
must be written before the EEPROM may be accessed.
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12.6.3 EEPROM Data Register
Name: EEDROffset: 0x40 [ID-000004d0]Reset: 0x00Property: When
addressing as I/O Register: address offset is 0x20
When addressing I/O registers as data space using LD and ST
instructions, the provided offset must beused. When using the I/O
specific commands IN and OUT, the offset is reduced by 0x20,
resulting in anI/O address offset within 0x00 - 0x3F.
Bit 7 6 5 4 3 2 1 0 EEDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 7:0 EEDR[7:0]EEPROM DataFor the EEPROM write operation, the
EEDR register contains the data to be written to the EEPROM inthe
address given by the EEAR register. For the EEPROM read operation,
the EEDR contains the dataread out from the EEPROM at the address
given by EEAR.
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