1631 InitializationAfter Reset all standard function device IO pads are connected to the port with outputs tri-stated and input buffersenabled even if there is no clock running
For best power consumption disable the input of unused pins and pins that are used as analog inputs or outputs
Specific pins such as those used for connecting a debugger may be configured differently as required by theirspecial function
1632 Operation
16321 Basic FunctionsEach IO pin Pxn can be controlled by the registers in PORTx Each pin group x has its own set of PORT registersThe base address of the register set for pin n is at the byte address PORT + 0x10 + The index within that registerset is n
To use pin number n as an output only write bit n of the PORTxDIR register to 1 This can be done by writing bit n inthe PORTxDIRSET register to 1 which will avoid disturbing the configuration of other pins in that group The nth bitin the PORTxOUT register must be written to the desired output value
Similarly writing a PORTxOUTSET bit to 1 will set the corresponding bit in the PORTxOUT register to 1 Writing abit in PORTxOUTCLR to 1 will clear that bit in PORTxOUT to zero Writing a bit in PORTxOUTTGL or PORTxIN to1 will toggle that bit in PORTxOUT
To use pin n as an input bit n in the PORTxDIR register must be written to 0 to disable the output driver This canbe done by writing bit n in the PORTxDIRCLR register to 1 which will avoid disturbing the configuration of otherpins in that group The input value can be read from bit n in register PORTxIN as long as the ISC bit is not set toINPUT_DISABLE
Writing a bit to 1 in PORTxDIRTGL will toggle that bit in PORTxDIR and toggle the direction of the correspondingpin
16322 Pin ConfigurationThe Pin n Configuration register (PORTxPINnCTRL) is used to configure inverted IO pullup and input sensing of apin
All input and output on the respective pin n can be inverted by writing a 1 to the Inverted IO Enable bit (INVEN) inPORTxPINnCTRL
Toggling the INVEN bit causes an edge on the pin which can be detected by all peripherals using this pin and isseen by interrupts or Events if enabled
Pullup of pin n is enabled by writing a 1 to the Pullup Enable bit (PULLUPEN) in PORTxPINnCTRL
Changes of the signal on a pin can trigger an interrupt The exact conditions are defined by writing to the InputSensebit field (ISC) in PORTxPINnCTRL
When setting or changing interrupt settings take these points into accountbull If an INVEN bit is toggled in the same cycle as the interrupt setting the edge caused by the inversion toggling
may not cause an interrupt requestbull If an input is disabled while synchronizing an interrupt that interrupt may be requested on re-enabling the input
even if it is re-enabled with a different interrupt settingbull If the interrupt setting is changed while synchronizing an interrupt that interrupt may not be acceptedbull Only a few pins support full asynchronous interrupt detection see IO Multiplexing and Considerations These
limitations apply for waking the system from sleep
Interrupt Type Fully Asynchronous Pins Other Pins
BOTHEDGES Will wake system Will wake system
RISING Will wake system Will not wake system
FALLING Will wake system Will not wake system
LEVEL Will wake system Will wake system
16323 Virtual PortsThe Virtual PORT registers map the most frequently used regular PORT registers into the bit-accessible IO spaceWriting to the Virtual PORT registers has the same effect as writing to the regular registers but allows for memory-specific instructions such as bit-manipulation instructions which are not valid for the extended IO memory spacewhere the regular PORT registers reside
ATmega32083209PORT - IO Pin Configuration
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Table 16-1 Virtual Port Mapping
Regular PORT Register Mapped to Virtual PORT Register
PORTDIR VPORTDIR
PORTOUT VPORTOUT
PORTIN VPORTIN
PORTINTFLAG VPORTINTFLAG
16324 Peripheral OverridePeripherals such as USARTs and timers may be connected to IO pins Such peripherals will usually have a primaryand optionally also alternate IO pin connection selectable by PORTMUX By configuring and enabling suchperipherals the general-purpose IO pin behavior normally controlled by PORT will be overridden by the peripheral ina peripheral-dependent way Some peripherals may not override all of the PORT registers leaving the PORT moduleto control some aspects of the IO pin operation Refer to the description of each peripheral for information on theperipheral override Any pin in a PORT which is not overridden by a peripheral will continue to operate as a general-purpose IO pin
1633 InterruptsTable 16-2 Available Interrupt Vectors and Sources
Name Vector Description Conditions
PORTx PORT interrupt INTn in PORTxINTFLAGS is raised as configured by ISC bit in PORTxPINnCTRL
Each PORT pin n can be configured as an interrupt source Each interrupt can be individually enabled or disabled bywriting to ISC in PORTxPINnCTRL
When an interrupt condition occurs the corresponding Interrupt Flag is set in the Interrupt Flags register of theperipheral (peripheralINTFLAGS)
An interrupt request is generated when the corresponding interrupt source is enabled and the Interrupt Flag is setThe interrupt request remains active until the Interrupt Flag is cleared See the peripherals INTFLAGS register fordetails on how to clear Interrupt Flags
Asynchronous Sensing Pin PropertiesPORT supports synchronous and asynchronous input sensing with interrupts for selectable pin change conditionsAsynchronous pin change sensing means that a pin change can wake the device from all sleep modes includingmodes where no clocks are running
Table 16-3 Behavior Comparison of FullyPartly Asynchronous Sense Pin
Property Synchronous or Partly Asynchronous SenseSupport
Full Asynchronous SenseSupport
Minimum pulse widthto trigger interrupt
Minimum one system clock cycle Less than a system clock cycle
Waking the devicefrom sleep
From all interrupt sense configurations from sleepmodes with Main Clock running Only fromBOTHEDGES or LEVEL interrupt senseconfiguration from sleep modes with Main Clockstopped
From all interrupt senseconfigurations from all sleep modes
Interrupt ldquodead timerdquo No new interrupt for three cycles after the previous Less than a system clock cycle
Minimum Wake-uppulse length
Value on pad must be kept until the system clock hasrestarted
Less than a system clock cycle
ATmega32083209PORT - IO Pin Configuration
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1634 EventsAll PORT pins are asynchronous event system generators PORT has as many event generators as there are PORTpins in the device Each event system output from PORT is the value present on the corresponding pin if the digitalinput driver is enabled If a pin input driver is disabled the corresponding event system output is zero
PORT has no event inputs
1635 Sleep Mode OperationWith the exception of interrupts and input synchronization all pin configurations are independent of sleep modePeripherals connected to the Ports can be affected by sleep modes described in the respective peripheralsdocumentation
The PORT peripheral will always use the Main Clock Input synchronization will halt when this clock stops
ATmega32083209PORT - IO Pin Configuration
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164 Register Summary - PORTx
Offset Name Bit Pos
0x00 DIR 70 DIR[70]0x01 DIRSET 70 DIRSET[70]0x02 DIRCLR 70 DIRCLR[70]0x03 DIRTGL 70 DIRTGL[70]0x04 OUT 70 OUT[70]0x05 OUTSET 70 OUTSET[70]0x06 OUTCLR 70 OUTCLR[70]0x07 OUTTGL 70 OUTTGL[70]0x08 IN 70 IN[70]0x09 INTFLAGS 70 INT[70]0x0A
0x0F
Reserved
0x10 PIN0CTRL 70 INVEN PULLUPEN ISC[20]0x11 PIN1CTRL 70 INVEN PULLUPEN ISC[20]0x12 PIN2CTRL 70 INVEN PULLUPEN ISC[20]0x13 PIN3CTRL 70 INVEN PULLUPEN ISC[20]0x14 PIN4CTRL 70 INVEN PULLUPEN ISC[20]0x15 PIN5CTRL 70 INVEN PULLUPEN ISC[20]0x16 PIN6CTRL 70 INVEN PULLUPEN ISC[20]0x17 PIN7CTRL 70 INVEN PULLUPEN ISC[20]
165 Register Description - Ports
ATmega32083209PORT - IO Pin Configuration
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1651 Data Direction
Name DIROffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DIR[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash DIR[70] Data DirectionThis bit field controls output enable for the individual pins of the PortWriting a lsquo1rsquo to PORTxDIR[n] configures and enables pin n as an output pinWriting a lsquo0rsquo to PORTxDIR[n] configures pin n as an input-only pin Its properties can be configured by writing to theISC bit in PORTxPINnCTRLPORTxDIRn controls only the output enable Setting PORTxDIR[n] to lsquo1rsquo does not disable the pin input
ATmega32083209PORT - IO Pin Configuration
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1652 Data Direction Set
Name DIRSETOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DIRSET[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash DIRSET[70] Data Direction SetThis bit field can be used instead of a read-modify-write to set individual pins as outputWriting a 1 to DIRSET[n] will set the corresponding PORTxDIR[n] bitReading this bit field will always return the value of PORTxDIR
ATmega32083209PORT - IO Pin Configuration
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1653 Data Direction Clear
Name DIRCLROffset 0x02Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DIRCLR[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash DIRCLR[70] Data Direction ClearThis register can be used instead of a read-modify-write to configure individual pins as input-onlyWriting a 1 to DIRCLR[n] will clear the corresponding bit in PORTxDIRReading this bit field will always return the value of PORTxDIR
ATmega32083209PORT - IO Pin Configuration
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1654 Data Direction Toggle
Name DIRTGLOffset 0x03Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DIRTGL[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash DIRTGL[70] Data Direction ToggleThis bit field can be used instead of a read-modify-write to toggle the direction of individual pinsWriting a 1 to DIRTGL[n] will toggle the corresponding bit in PORTxDIRReading this bit field will always return the value of PORTxDIR
ATmega32083209PORT - IO Pin Configuration
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1655 Output Value
Name OUTOffset 0x04Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 OUT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash OUT[70] Output ValueThis bit field defines the data output value for the individual pins of the portIf OUT[n] is written to 1 pin n is driven highIf OUT[n] is written to 0 pin n is driven lowIn order to have any effect the pin direction must be configured as output
ATmega32083209PORT - IO Pin Configuration
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1656 Output Value Set
Name OUTSETOffset 0x05Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 OUTSET[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash OUTSET[70] Output Value SetThis bit field can be used instead of a read-modify-write to set the output value of individual pins to 1Writing a 1 to OUTSET[n] will set the corresponding bit in PORTxOUTReading this bit field will always return the value of PORTxOUT
ATmega32083209PORT - IO Pin Configuration
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1657 Output Value Clear
Name OUTCLROffset 0x06Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 OUTCLR[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash OUTCLR[70] Output Value ClearThis register can be used instead of a read-modify-write to clear the output value of individual pins to 0Writing a 1 to OUTCLR[n] will clear the corresponding bit in PORTxOUTReading this bit field will always return the value of PORTxOUT
ATmega32083209PORT - IO Pin Configuration
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1658 Output Value Toggle
Name OUTTGLOffset 0x07Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 OUTTGL[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash OUTTGL[70] Output Value ToggleThis register can be used instead of a read-modify-write to toggle the output value of individual pinsWriting a 1 to OUTTGL[n] will toggle the corresponding bit in PORTxOUTReading this bit field will always return the value of PORTxOUT
ATmega32083209PORT - IO Pin Configuration
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1659 Input Value
Name INOffset 0x08Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 IN[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash IN[70] Input ValueThis register shows the value present on the pins if the digital input driver is enabled IN[n] shows the value of pin n ofthe Port If the digital input buffers are disabled the input is not sampled and cannot be readWriting to a bit of PORTxIN will toggle the corresponding bit in PORTxOUT
ATmega32083209PORT - IO Pin Configuration
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16510 Interrupt Flags
Name INTFLAGSOffset 0x09Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 INT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash INT[70] Interrupt Pin FlagThe INT Flag is set when a pin changestate matches the pins input sense configurationWriting a 1 to a flags bit location will clear the flagFor enabling and executing the interrupt refer to ISC bit description in PORTxPINnCTRL
ATmega32083209PORT - IO Pin Configuration
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16511 Pin n Control
Name PINCTRLOffset 0x10 + n0x01 [n=07]Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 INVEN PULLUPEN ISC[20]
Access RW RW RW RW RW Reset 0 0 0 0 0
Bit 7 ndash INVEN Inverted IO EnableValue Description0 Input and output values are not inverted1 Input and output values are inverted
Bit 3 ndash PULLUPEN Pullup EnableValue Description0 Pullup disabled for pin n1 Pullup enabled for pin n
Bits 20 ndash ISC[20] InputSense ConfigurationThese bits configure the input and sense configuration of pin n The sense configuration determines how a portinterrupt can be triggered If the input buffer is disabled the input cannot be read in the IN registerValue Name Description0x0 INTDISABLE Interrupt disabled but input buffer enabled0x1 BOTHEDGES Interrupt enabled with sense on both edges0x2 RISING Interrupt enabled with sense on rising edge0x3 FALLING Interrupt enabled with sense on falling edge0x4 INPUT_DISABLE Interrupt and digital input buffer disabled0x5 LEVEL Interrupt enabled with sense on low levelother - Reserved
ATmega32083209PORT - IO Pin Configuration
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166 Register Summary - VPORTx
Offset Name Bit Pos
0x00 DIR 70 DIR[70]0x01 OUT 70 OUT[70]0x02 IN 70 IN[70]0x03 INTFLAGS 70 INT[70]
167 Register Description - Virtual Ports
ATmega32083209PORT - IO Pin Configuration
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1671 Data Direction
Name DIROffset 0x00Reset 0x00Property -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers but allows for memory-specific instructions such as bit-manipulation instructions which are not valid for the extended IO memory spacewhere the regular PORT registers reside
Bit 7 6 5 4 3 2 1 0 DIR[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash DIR[70] Data DirectionThis bit field controls output enable for the individual pins of the Port
ATmega32083209PORT - IO Pin Configuration
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1672 Output Value
Name OUTOffset 0x01Reset 0x00Property -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers but allows for memory-specific instructions such as bit-manipulation instructions which are not valid for the extended IO memory spacewhere the regular PORT registers reside
Bit 7 6 5 4 3 2 1 0 OUT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash OUT[70] Output ValueThis bit field selects the data output value for the individual pins in the Port
ATmega32083209PORT - IO Pin Configuration
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1673 Input Value
Name INOffset 0x02Reset 0x00Property -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers but allows for memory-specific instructions such as bit-manipulation instructions which are not valid for the extended IO memory spacewhere the regular PORT registers reside
Bit 7 6 5 4 3 2 1 0 IN[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash IN[70] Input ValueThis bit field holds the value present on the pins if the digital input buffer is enabledWriting to a bit of VPORTxIN will toggle the corresponding bit in VPORTxOUT
ATmega32083209PORT - IO Pin Configuration
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1674 Interrupt Flag
Name INTFLAGSOffset 0x03Reset 0x00Property -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers but allows for memory-specific instructions such as bit-manipulation instructions which are not valid for the extended IO memory spacewhere the regular PORT registers reside
Bit 7 6 5 4 3 2 1 0 INT[70]
Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bits 70 ndash INT[70] Interrupt Pin FlagThe INT flag is set when a pin changestate matches the pins input sense configuration and the pin is configured assource for port interruptWriting a 1 to this flags bit location will clear the flagFor enabling and executing the interrupt refer to the ISC bits in PORTxPINnCTRL
ATmega32083209PORT - IO Pin Configuration
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17 BOD - Brown-out Detector
171 Featuresbull Brown-out Detection monitors the power supply to avoid operation below a programmable levelbull There are three modes
ndash Enabledndash Sampledndash Disabled
bull Separate selection of mode for Active and Sleep modesbull Voltage Level Monitor (VLM) with Interruptbull Programmable VLM Level Relative to the BOD Level
172 OverviewThe Brown-out Detector (BOD) monitors the power supply and compares the voltage with two programmable brown-out threshold levels The brown-out threshold level defines when to generate a Reset A Voltage Level Monitor (VLM)monitors the power supply and compares it to a threshold higher than the BOD threshold The VLM can thengenerate an interrupt request as an early warning when the supply voltage is about to drop below the VLMthreshold The VLM threshold level is expressed as a percentage above the BOD threshold level
The BOD is mainly controlled by fuses The mode used in Standby Sleep mode and Power-Down Sleep mode can bealtered in normal program execution The VLM part of the BOD is controlled by IO registers as well
When activated the BOD can operate in Enabled mode where the BOD is continuously active and in Sampledmode where the BOD is activated briefly at a given period to check the supply voltage level
ATmega32083209BOD - Brown-out Detector
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1721 Block DiagramFigure 17-1 BOD Block Diagram
+
-
+
-
Bandgap
Bandgap
BOD Level and
Calibration
VLM Interrupt Level
Brown-out Detection
VDD
VLM InterruptDetection
173 Functional Description
1731 InitializationThe BOD settings are loaded from fuses during Reset The BOD level and operating mode in Active and Idle Sleepmode are set by fuses and cannot be changed by the CPU The operating mode in Standby and Power-Down Sleepmode is loaded from fuses and can be changed by software
The Voltage Level Monitor function can be enabled by writing a 1 to the VLM Interrupt Enable bit (VLMIE) in theInterrupt Control register (BODINTCTRL) The VLM interrupt is configured by writing the VLM Configuration bits(VLMCFG) in BODINTCTRL An interrupt is requested when the supply voltage crosses the VLM threshold eitherfrom above from below or from any direction
The VLM functionality will follow the BOD mode If the BOD is turned OFF the VLM will not be enabled even if theVLMIE is 1 If the BOD is using Sampled mode the VLM will also be sampled When enabling VLM interrupt theinterrupt flag will always be set if VLMCFG equals 0x2 and may be set if VLMCFG is configured to 0x0 or 0x1
The VLM threshold is defined by writing the VLM Level bits (VLMLVL) in the Control A register (BODVLMCTRLA)
1732 InterruptsTable 17-1 Available Interrupt Vectors and Sources
Name Vector Description Conditions
VLM Voltage Level Monitor Supply voltage crossing the VLM threshold as configured by VLMCFG inBODINTCTRL
The VLM interrupt will not be executed if the CPU is halted in debug mode
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When an interrupt condition occurs the corresponding interrupt flag is set in the Interrupt Flags register of theperipheral (peripheralINTFLAGS)
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheralrsquos InterruptControl (peripheralINTCTRL) register
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is setThe interrupt request remains active until the interrupt flag is cleared See the peripheralrsquos INTFLAGS register fordetails on how to clear interrupt flags
1733 Sleep Mode OperationThere are two separate fuses defining the BOD configuration in different sleep modes One fuse defines the modeused in Active mode and Idle Sleep mode (ACTIVE in FUSEBODCFG) and is written to the ACTIVE bits in theControl A register (BODCTRLA) The second fuse (SLEEP in FUSEBODCFG) selects the mode used in StandbySleep mode and Power-Down Sleep mode and is loaded into the SLEEP bits in the Control A register (BODCTRLA)
The operating mode in Active mode and Idle Sleep mode (ie ACTIVE in BODCTRLA) cannot be altered bysoftware The operating mode in Standby Sleep mode and Power-Down Sleep mode can be altered by writing to theSLEEP bits in the Control A register (BODCTRLA)
When the device is going into Standby Sleep mode or Power-Down Sleep mode the BOD will change operationmode as defined by SLEEP in BODCTRLA When the device is waking up from Standby or Power-Down Sleepmode the BOD will operate in the mode defined by the ACTIVE bit field in BODCTRLA
1734 Configuration Change ProtectionThis peripheral has registers that are under Configuration Change Protection (CCP) To write to these registers acertain key must first be written to the CPUCCP register followed by a write access to the protected bits within fourCPU instructions
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves theprotected register unchanged
The following registers are under CCP
Table 17-2 Registers Under Configuration Change Protection
Register Key
SLEEP in BODCTRLA IOREG
ATmega32083209BOD - Brown-out Detector
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174 Register Summary - BOD
Offset Name Bit Pos
0x00 CTRLA 70 SAMPFREQ ACTIVE[10] SLEEP[10]0x01 CTRLB 70 LVL[20]0x02
0x07
Reserved
0x08 VLMCTRLA 70 VLMLVL[10]0x09 INTCTRL 70 VLMCFG[10] VLMIE0x0A INTFLAGS 70 VLMIF0x0B STATUS 70 VLMS
175 Register Description
ATmega32083209BOD - Brown-out Detector
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1751 Control A
Name CTRLAOffset 0x00Reset Loaded from fuseProperty Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 SAMPFREQ ACTIVE[10] SLEEP[10]
Access R R R RW RW Reset x x x x x
Bit 4 ndash SAMPFREQ Sample FrequencyThis bit selects the BOD sample frequencyThe Reset value is loaded from the SAMPFREQ bit in FUSEBODCFG This bit is under Configuration ChangeProtection (CCP)Value Description0x0 Sample frequency is 1 kHz0x1 Sample frequency is 125 Hz
Bits 32 ndash ACTIVE[10] ActiveThese bits select the BOD operation mode when the device is in Active or Idle modeThe Reset value is loaded from the ACTIVE bits in FUSEBODCFGValue Description0x0 Disabled0x1 Enabled0x2 Sampled0x3 Enabled with wake-up halted until BOD is ready
Bits 10 ndash SLEEP[10] SleepThese bits select the BOD operation mode when the device is in Standby or Power-Down Sleep mode The Resetvalue is loaded from the SLEEP bits in FUSEBODCFGThese bits are under Configuration Change Protection (CCP)Value Description0x0 Disabled0x1 Enabled0x2 Sampled0x3 Reserved
ATmega32083209BOD - Brown-out Detector
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1752 Control B
Name CTRLBOffset 0x01Reset Loaded from fuseProperty -
Bit 7 6 5 4 3 2 1 0 LVL[20]
Access R R R R R R R R Reset 0 0 0 0 0 x x x
Bits 20 ndash LVL[20] BOD LevelThese bits select the BOD threshold levelThe Reset value is loaded from the BOD Level bits (LVL) in the BOD Configuration Fuse (FUSEBODCFG)Value Name Description0x0 BODLEVEL0 18V0x2 BODLEVEL2 26V0x7 BODLEVEL7 43V
Note bull Refer to the BOD and POR Characteristics in Electrical Characteristics for further detailsbull Values in the description are typical values
ATmega32083209BOD - Brown-out Detector
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1753 VLM Control A
Name VLMCTRLAOffset 0x08Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 VLMLVL[10]
Access RW RW Reset 0 0
Bits 10 ndash VLMLVL[10] VLM LevelThese bits select the VLM threshold relative to the BOD threshold (LVL in BODCTRLB)Value Description0x0 VLM threshold 5 above BOD threshold0x1 VLM threshold 15 above BOD threshold0x2 VLM threshold 25 above BOD thresholdother Reserved
ATmega32083209BOD - Brown-out Detector
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1754 Interrupt Control
Name INTCTRLOffset 0x09Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 VLMCFG[10] VLMIE
Access RW RW RW Reset 0 0 0
Bits 21 ndash VLMCFG[10] VLM ConfigurationThese bits select which incidents will trigger a VLM interruptValue Description0x0 Voltage crosses VLM threshold from above0x1 Voltage crosses VLM threshold from below0x2 Either direction is triggering an interrupt requestOther Reserved
Bit 0 ndash VLMIE VLM Interrupt EnableWriting a 1 to this bit enables the VLM interrupt
ATmega32083209BOD - Brown-out Detector
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1755 VLM Interrupt Flags
Name INTFLAGSOffset 0x0AReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 VLMIF
Access RW Reset 0
Bit 0 ndash VLMIF VLM Interrupt FlagThis flag is set when a trigger from the VLM is given as configured by the VLMCFG bit in the BODINTCTRL registerThe flag is only updated when the BOD is enabled
ATmega32083209BOD - Brown-out Detector
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1756 VLM Status
Name STATUSOffset 0x0BReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 VLMS
Access R Reset 0
Bit 0 ndash VLMS VLM StatusThis bit is only valid when the BOD is enabledValue Description0 The voltage is above the VLM threshold level1 The voltage is below the VLM threshold level
ATmega32083209BOD - Brown-out Detector
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18 VREF - Voltage Reference
181 Featuresbull Programmable Voltage Reference Sources
ndash For ADC0 peripheralndash For AC0 peripheral
bull Each Reference Source Supports Different Voltagesndash 055Vndash 11Vndash 15Vndash 25Vndash 43Vndash AVDD
182 OverviewThe Voltage Reference buffer (VREF) provides control registers for selecting between multiple internal referencelevels The internal references are generated from the internal bandgap
When a peripheral that requires a voltage reference is enabled the corresponding voltage reference buffer andbandgap is automatically enabled
1821 Block DiagramFigure 18-1 VREF Block Diagram
Reference se lect
Bandgap ReferenceGenerator
InternalReferenceBUF
11V15V25V43V
055V
Reference enable
Reference request
Bandgapenable
183 Functional Description
1831 InitializationThe output level from the reference buffer should be selected (ADC0REFSEL and AC0REFSEL in VREFCTRLA)before the respective modules are enabled The reference buffer is then automatically enabled when requested by aperipheral Changing the reference while these modules are enabled could lead to unpredictable behavior
The VREF module and reference voltage sources can be forced to be ON independent of being required by aperipheral by writing to the respective Force Enable bits (ADC0REFEN AC0REFEN) in the Control B(VREFCTRLB) register This can be used to remove the reference start-up time at the cost of increased powerconsumption
ATmega32083209VREF - Voltage Reference
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184 Register Summary - VREF
Offset Name Bit Pos
0x00 CTRLA 70 ADC0REFSEL[20] AC0REFSEL[20]0x01 CTRLB 70 ADC0REFEN AC0REFEN
185 Register Description
ATmega32083209VREF - Voltage Reference
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1851 Control A
Name CTRLAOffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 ADC0REFSEL[20] AC0REFSEL[20]
Access RW RW RW RW RW RW Reset 0 0 0 0 0 0
Bits 64 ndash ADC0REFSEL[20] ADC0 Reference SelectThese bits select the reference voltage for ADC0Value Name Description0x0 0V55 055V internal reference0x1 1V1 11V internal reference0x2 2V5 25V internal reference0x3 4V3 43V internal reference0x4 1V5 15V internal referenceOther - Reserved
Note Refer to VREF in the Electrical Characteristics section for further details
Bits 20 ndash AC0REFSEL[20] AC0 Reference SelectThese bits select the reference voltage for AC0Value Name Description0x0 0V55 055V internal reference0x1 1V1 11V internal reference0x2 2V5 25V internal reference0x3 4V3 43V internal reference0x4 1V5 15V internal reference0x5 - Reserved0x6 - Reserved0x7 AVDD AVDD
Note Refer to VREF in the Electrical Characteristics section for further details
ATmega32083209VREF - Voltage Reference
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 174
1852 Control B
Name CTRLBOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 ADC0REFEN AC0REFEN
Access RW RW Reset 0 0
Bit 1 ndash ADC0REFEN ADC0 Reference Force EnableWriting a lsquo1rsquo to this bit forces the voltage reference for ADC0 to be enabled even if it is not requestedWriting a lsquo0rsquo to this bit allows to automatic enabledisable the reference source when not requested
Bit 0 ndash AC0REFEN AC0 DACREF Reference Force EnableWriting a lsquo1rsquo to this bit forces the voltage reference for AC0 DACREF to be enabled even if it is not requestedWriting a lsquo0rsquo to this bit allows to automatic enabledisable the reference source when not requested
ATmega32083209VREF - Voltage Reference
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 175
19 WDT - Watchdog Timer
191 Featuresbull Issues a System Reset if the Watchdog Timer is not Cleared Before its Time-out Periodbull Operating Asynchronously from System Clock Using an Independent Oscillatorbull Using the 1 KHz Output of the 32 KHz Ultra Low-Power Oscillator (OSCULP32K)bull 11 Selectable Time-out Periods from 8 ms to 8sbull Two Operation modes
ndash Normal modendash Window mode
bull Configuration Lock to Prevent Unwanted Changesbull Closed Period Timer Activation After First WDT Instruction for Easy Setup
192 OverviewThe Watchdog Timer (WDT) is a system function for monitoring correct program operation It allows the system torecover from situations such as runaway or deadlocked code by issuing a Reset When enabled the WDT is aconstantly running timer configured to a predefined time-out period If the WDT is not reset within the time-out periodit will issue a system Reset The WDT is reset by executing the WDR (Watchdog Timer Reset) instruction fromsoftware
The WDT has two modes of operation Normal mode and Window mode The settings in the Control A register(WDTCTRLA) determine the mode of operation
A Window mode defines a time slot or window inside the time-out period during which the WDT must be reset If theWDT is reset outside this window either too early or too late a system Reset will be issued Compared to the Normalmode the Window mode can catch situations where a code error causes constant WDR execution
When enabled the WDT will run in Active mode and all Sleep modes It is asynchronous (ie running from a CPUindependent clock source) For this reason it will continue to operate and be able to issue a system Reset even if themain clock fails
The CCP mechanism ensures that the WDT settings cannot be changed by accident For increased safety aconfiguration for locking the WDT settings is available
ATmega32083209WDT - Watchdog Timer
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 176
1921 Block DiagramFigure 19-1 WDT Block Diagram
COUNT
=
=
Inside closed window
Enable open window and clear count
CLK_WDT
WDR(instruction)
SystemReset
CTRLA
CTRLA
WINDOW
PERIOD
1922 Signal DescriptionNot applicable
193 Functional Description
1931 Initializationbull The WDT is enabled when a non-zero value is written to the Period bits (PERIOD) in the Control A register
(WDTCTRLA)bull Optional Write a non-zero value to the Window bits (WINDOW) in WDTCTRLA to enable Window mode
operation
All bits in the Control A register and the Lock bit (LOCK) in the STATUS register (WDTSTATUS) are write protectedby the Configuration Change Protection mechanism
The Reset value of WDTCTRLA is defined by a fuse (FUSEWDTCFG) so the WDT can be enabled at boot time Ifthis is the case the LOCK bit in WDTSTATUS is set at boot time
1932 ClocksA 1 KHz Oscillator Clock (CLK_WDT_OSC) is sourced from the internal Ultra Low-Power Oscillator OSCULP32KDue to the ultra low-power design the oscillator is not very accurate and so the exact time-out period may vary fromdevice to device This variation must be kept in mind when designing software that uses the WDT to ensure that thetime-out periods used are valid for all devices
The Counter Clock CLK_WDT_OSC is asynchronous to the system clock Due to this asynchronicity writing to theWDT Control register will require synchronization between the clock domains
1933 Operation
19331 Normal ModeIn Normal mode operation a single time-out period is set for the WDT If the WDT is not reset from software using theWDR any time before the time-out occurs the WDT will issue a system Reset
A new WDT time-out period will be started each time the WDT is reset by WDR
There are 11 possible WDT time-out periods (TOWDT) selectable from 8 ms to 8s by writing to the Period bit field(PERIOD) in the Control A register (WDTCTRLA)
ATmega32083209WDT - Watchdog Timer
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 177
Figure 19-2 Normal Mode Operation
t [ms]
WDT Count
5 10 15 20 25 30 35
Timely WDT Reset (WDR)
TOWDT
WDT TimeoutSystem Reset
TO WDT = 16 msHere
Normal mode is enabled as long as the WINDOW bit field in the Control A register (WDTCTRLA) is 0x0
19332 Window ModeIn Window mode operation the WDT uses two different time-out periods a closed Window Time-out period(TOWDTW) and the normal time-out period (TOWDT)
bull The closed window time-out period defines a duration from 8 ms to 8s where the WDT cannot be reset If theWDT is reset during this period the WDT will issue a system Reset
bull The normal WDT time-out period which is also 8 ms to 8s defines the duration of the open period during whichthe WDT can (and should) be reset The open period will always follow the closed period so the total duration ofthe time-out period is the sum of the closed window and the open window time-out periods
When enabling Window mode or when going out of Debug mode the first closed period is activated after the first WDRinstruction
If a second WDR is issued while a previous WDR is being synchronized the second one will be ignored
Figure 19-3 Window Mode Operation
t [ms]
WDT Count
5 10 15 20 25 30 35
Timely WDT Reset (WDR)
Clo
sed
TOWDTW
Ope
n
TOWDT
System ResetWDR too early
TOWDTW =TOWDT = 8 msHere
The Window mode is enabled by writing a non-zero value to the WINDOW bit field in the Control A register(WDTCTRLA) and disabled by writing WINDOW=0x0
19333 Configuration Protection and LockThe WDT provides two security mechanisms to avoid unintentional changes to the WDT settings
The first mechanism is the Configuration Change Protection mechanism employing a timed write procedure forchanging the WDT control registers
The second mechanism locks the configuration by writing a 1 to the LOCK bit in the STATUS register(WDTSTATUS) When this bit is 1 the Control A register (WDTCTRLA) cannot be changed Consequently theWDT cannot be disabled from software
ATmega32083209WDT - Watchdog Timer
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 178
LOCK in WDTSTATUS can only be written to 1 It can only be cleared in Debug mode
If the WDT configuration is loaded from fuses LOCK is automatically set in WDTSTATUS
1934 Sleep Mode OperationThe WDT will continue to operate in any sleep mode where the source clock is active
1935 Debug OperationWhen run-time debugging this peripheral will continue normal operation Halting the CPU in Debugging mode willhalt the normal operation of the peripheral
When halting the CPU in Debug mode the WDT counter is reset
When starting the CPU again and the WDT is operating in Window mode the first closed window time-out period willbe disabled and a Normal mode time-out period is executed
1936 SynchronizationDue to asynchronicity between the main clock domain and the peripheral clock domain the Control A register(WDTCTRLA) is synchronized when written The Synchronization Busy flag (SYNCBUSY) in the STATUS register(WDTSTATUS) indicates if there is an ongoing synchronization
Writing to WDTCTRLA while SYNCBUSY=1 is not allowed
The following registers are synchronized when writtenbull PERIOD bits in Control A register (WDTCTRLA)bull Window Period bits (WINDOW) in WDTCTRLA
The WDR instruction will need two to three cycles of the WDT clock in order to be synchronized Issuing a new WDRinstruction while a WDR instruction is being synchronized will be ignored
1937 Configuration Change ProtectionThis peripheral has registers that are under Configuration Change Protection (CCP) To write to these registers acertain key must first be written to the CPUCCP register followed by a write access to the protected bits within fourCPU instructions
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves theprotected register unchanged
The following registers are under CCP
Table 19-1 WDT - Registers Under Configuration Change Protection
Register Key
WDTCTRLA IOREG
LOCK bit in WDTSTATUS IOREG
List of bitsregisters protected by CCP
bull Period bits in Control A register (CTRLAPERIOD)bull Window Period bits in Control A register (CTRLAWINDOW)bull LOCK bit in STATUS register (STATUSLOCK)
ATmega32083209WDT - Watchdog Timer
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 179
194 Register Summary - WDT
Offset Name Bit Pos
0x00 CTRLA 70 WINDOW[30] PERIOD[30]0x01 STATUS 70 LOCK SYNCBUSY
195 Register Description
ATmega32083209WDT - Watchdog Timer
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 180
1951 Control A
Name CTRLAOffset 0x00Reset From FUSEWDTCFGProperty Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 WINDOW[30] PERIOD[30]
Access RW RW RW RW RW RW RW RW Reset x x x x x x x x
Bits 74 ndash WINDOW[30] WindowWriting a non-zero value to these bits enables the Window mode and selects the duration of the closed periodaccordinglyThe bits are optionally lock-protected
bull If LOCK bit in WDTSTATUS is 1 all bits are change-protected (Access = R)bull If LOCK bit in WDTSTATUS is 0 all bits can be changed (Access = RW)
Value Name Description0x0 OFF -0x1 8CLK 0008s0x2 16CLK 0016s0x3 32CLK 0032s0x4 64CLK 0064s0x5 128CLK 0128s0x6 256CLK 0256s0x7 512CLK 0512s0x8 1KCLK 1024s0x9 2KCLK 2048s0xA 4KCLK 4096s0xB 8KCLK 8192sother - Reserved
Bits 30 ndash PERIOD[30] PeriodWriting a non-zero value to this bit enables the WDT and selects the time-out period in Normal mode accordingly InWindow mode these bits select the duration of the open windowThe bits are optionally lock-protected
bull If LOCK in WDTSTATUS is 1 all bits are change-protected (Access = R)bull If LOCK in WDTSTATUS is 0 all bits can be changed (Access = RW)
Value Name Description0x0 OFF -0x1 8CLK 0008s0x2 16CLK 0016s0x3 32CLK 0032s0x4 64CLK 0064s0x5 128CLK 0128s0x6 256CLK 0256s0x7 512CLK 0512s0x8 1KCLK 10s0x9 2KCLK 20s0xA 4KCLK 41s0xB 8KCLK 82sother - Reserved
ATmega32083209WDT - Watchdog Timer
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 181
1952 Status
Name STATUSOffset 0x01Reset 0x00Property Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 LOCK SYNCBUSY
Access RW R Reset 0 0
Bit 7 ndash LOCK LockWriting this bit to 1 write-protects the WDTCTRLA registerIt is only possible to write this bit to 1 This bit can be cleared in Debug mode onlyIf the PERIOD bits in WDTCTRLA are different from zero after boot code the lock will automatically be setThis bit is under CCP
Bit 0 ndash SYNCBUSY Synchronization BusyThis bit is set after writing to the WDTCTRLA register while the data is being synchronized from the system clockdomain to the WDT clock domainThis bit is cleared by the system after the synchronization is finishedThis bit is not under CCP
ATmega32083209WDT - Watchdog Timer
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 182
20 TCA - 16-bit TimerCounter Type A
201 Featuresbull 16-Bit TimerCounterbull Three Compare Channelsbull Double-Buffered Timer Period Settingbull Double-Buffered Compare Channelsbull Waveform Generation
ndash Frequency generationndash Single-slope PWM (Pulse-Width Modulation)ndash Dual-slope PWM
bull Count on Eventbull Timer Overflow InterruptsEventsbull One Compare Match per Compare Channelbull Two 8-Bit TimerCounters in Split Mode
202 OverviewThe flexible 16-bit PWM TimerCounter type A (TCA) provides accurate program execution timing frequency andwaveform generation and command execution
A TCA consists of a base counter and a set of compare channels The base counter can be used to count clockcycles or events or let events control how it counts clock cycles It has direction control and period setting that canbe used for timing The compare channels can be used together with the base counter to do compare match controlfrequency generation and pulse-width waveform modulation
Depending on the mode of operation the counter is cleared reloaded incremented or decremented at each timercounter clock or event input
A timercounter can be clocked and timed from the peripheral clock with optional prescaling or from the EventSystem The Event System can also be used for direction control or to synchronize operations
By default the TCA is a 16-bit timercounter The timercounter has a Split mode feature that splits it into two 8-bittimercounters with three compare channels each
A block diagram of the 16-bit timercounter with closely related peripheral modules (in grey) is shown in the figurebelow
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 183
Figure 20-1 16-bit TimerCounter and Closely Related Peripherals
CounterControl Logic
Timer Period
TimerCounterBase Counter Prescaler
EventSystem
CLK_PER
POR
TS
Comparator
Buffer
Compare Channel 2Compare Channel 1
Compare Channel 0
WaveformGeneration
2021 Block DiagramThe figure below shows a detailed block diagram of the timercounter
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 184
Figure 20-2 TimerCounter Block Diagram
Base Counter
Compare Unit n
Counter
=
CMPn
CMPnBUF
WaveformGeneration
BV
=
PERBUF
PER
CNT
BV
= 0
lsquolsquocountrsquorsquolsquolsquoclearrsquorsquo
lsquolsquodirectionrsquorsquolsquolsquoloadrsquorsquo
Control Logic
OVF(INT Req and Event)
TOP
lsquolsquomatchrsquorsquo CMPn(INT Req and Event)
Control Logic
Clock Select
UPD
ATE
BOTTOM
WOn Out
Event
CTRLA
CTRLB
EVCTRL
Mode
EventAction
The Counter register (TCAnCNT) Period and Compare registers (TCAnPER and TCAnCMPm) and theircorresponding buffer registers (TCAnPERBUF and TCAnCMPBUFm) are 16-bit registers All buffer registers have aBuffer Valid (BV) flag that indicates when the buffer contains a new value
During normal operation the counter value is continuously compared to zero and the period (PER) value todetermine whether the counter has reached TOP or BOTTOM
The counter value is also compared to the TCAnCMPm registers These comparisons can be used to generateinterrupt requests The Waveform Generator modes use these comparisons to set the waveform period or pulsewidth
A prescaled peripheral clock and events from the Event System can be used to control the counter as shown in thefigure below
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 185
Figure 20-3 TimerCounter Clock Logic
CLKSEL
CNTxEI
CLK_PER
Event
Event SystemPrescaler
CNT
(Encoding)EVACTCLK_TCA
2022 Signal Description
Signal Description Type
WOn Digital output Waveform output
203 Functional Description
2031 DefinitionsThe following definitions are used throughout the documentation
Table 20-1 TimerCounter Definitions
Name Description
BOTTOM The counter reaches BOTTOM when it becomes 0x0000
MAX The counter reaches MAXimum when it becomes all ones
TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence
UPDATEThe update condition is met when the timercounter reaches BOTTOM or TOP depending on theWaveform Generator mode Buffered registers with valid buffer values will be updated unless the LockUpdate bit (LUPD) in TCAnCTRLE has been set
CNT Counter register value
CMP Compare register value
In general the term timer is used when the timercounter is counting periodic clock ticks The term counter is usedwhen the input signal has sporadic or irregular ticks The latter can be the case when counting events
2032 InitializationTo start using the timercounter in a basic mode follow these steps
1 Write a TOP value to the Period register (TCAnPER)2 Enable the peripheral by writing a lsquo1rsquo to the ENABLE bit in the Control A register (TCAnCTRLA)
The counter will start counting clock ticks according to the prescaler setting in the Clock Select bit field(CLKSEL) in TCAnCTRLA
3 Optional By writing a lsquo1rsquo to the Enable Count on Event Input bit (CNTEI) in the Event Control register(TCAnEVCTRL) events are counted instead of clock ticks
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 186
4 The counter value can be read from the Counter bit field (CNT) in the Counter register (TCAnCNT)
2033 Operation
20331 Normal OperationIn normal operation the counter is counting clock ticks in the direction selected by the Direction bit (DIR) in theControl E register (TCAnCTRLE) until it reaches TOP or BOTTOM The clock ticks are given by the peripheral clock(CLK_PER) prescaled according to the Clock Select bit field (CLKSEL) in the Control A register (TCAnCTRLA)
When TOP is reached while the counter is counting up the counter will wrap to lsquo0rsquo at the next clock tick Whencounting down the counter is reloaded with the Period register value (TCAnPER) when BOTTOM is reached
Figure 20-4 Normal OperationCNT written
lsquolsquoupdatersquorsquo
CNT
DIR
MAX
TOP
BOTTOM
It is possible to change the counter value in the Counter register (TCAnCNT) when the counter is running The writeaccess to TCAnCNT has higher priority than count clear or reload and will be immediate The direction of thecounter can also be changed during normal operation by writing to DIR in TCAnCTRLE
20332 Double BufferingThe Period register value (TCAnPER) and the Compare n register values (TCAnCMPn) are all double-buffered(TCAnPERBUF and TCAnCMPnBUF)
Each buffer register has a Buffer Valid flag (PERBV CMPnBV) in the Control F register (TCAnCTRLF) whichindicates that the buffer register contains a valid (new) value that can be copied into the corresponding Period orCompare register When the Period register and Compare n registers are used for a compare operation the BV flagis set when data are written to the buffer register and cleared on an UPDATE condition This is shown for a Compareregister (CMPn) in the figure below
Figure 20-5 Period and Compare Double Buffering
UPDATE
lsquolsquowrite enablersquorsquo lsquolsquodata writersquorsquo
CNT
lsquolsquomatchrsquorsquo
EN
EN
CMPnBUF
CMPn
BV
=
Both the TCAnCMPn and TCAnCMPnBUF registers are available as IO registers This allows initialization andbypassing of the buffer register and the double-buffering function
20333 Changing the PeriodThe Counter period is changed by writing a new TOP value to the Period register (TCAnPER)
No Buffering If double-buffering is not used any period update is immediate
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 187
Figure 20-6 Changing the Period Without Buffering
CNT
MAX
BOTTOM
Counter wraparound
lsquolsquoupdatersquorsquo
lsquolsquowritersquorsquo
New TOP written toPER that is higherthan current CNT
New TOP written toPER that is lowerthan current CNT
A counter wraparound can occur in any mode of operation when counting up without buffering as the TCAnCNT andTCAnPER registers are continuously compared If a new TOP value is written to TCAnPER that is lower than thecurrent TCAnCNT the counter will wrap first before a compare match occursFigure 20-7 Unbuffered Dual-Slope Operation
Counter wraparound
lsquolsquoupdatersquorsquo
lsquolsquowritersquorsquo
MAX
BOTTOM
CNT
New TOP written toPER that is higherthan current CNT
New TOP written toPER that is lowerthan current CNT
With Buffering When double-buffering is used the buffer can be written at any time and still maintain correctoperation The TCAnPER is always updated on the UPDATE condition as shown for dual-slope operation in thefigure below This prevents wraparound and the generation of odd waveformsFigure 20-8 Changing the Period Using Buffering
CNT
BOTTOM
MAX
lsquolsquoupdatersquorsquo
lsquolsquowritersquorsquo
New Period written toPERB that is higherthan current CNT
New Period written toPERB that is lowerthan current CNT
New PER is updatedwith PERB value
Note Buffering is used in figures illustrating TCA operation if not otherwise specified
20334 Compare ChannelEach Compare Channel n continuously compares the counter value (TCAnCNT) with the Compare n register(TCAnCMPn) If TCAnCNT equals TCAnCMPn the Comparator n signals a match The match will set the CompareChannelrsquos interrupt flag at the next timer clock cycle and the optional interrupt is generated
The Compare n Buffer register (TCAnCMPnBUF) provides double-buffer capability equivalent to that for the periodbuffer The double-buffering synchronizes the update of the TCAnCMPn register with the buffer value to either theTOP or BOTTOM of the counting sequence according to the UPDATE condition The synchronization prevents theoccurrence of odd-length non-symmetrical pulses for glitch-free output
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 188
203341 Waveform GenerationThe compare channels can be used for waveform generation on the corresponding port pins The followingrequirements must be met to make the waveform visible on the connected port pin
1 A Waveform Generation mode must be selected by writing the WGMODE bit field in TCAnCTRLB2 The TCA is counting clock ticks not events (CNTEI = 0 in TCAnEVCTRL)3 The compare channels used must be enabled (CMPnEN = 1 in TCAnCTRLB) This will override the output
value for the corresponding pin An alternative pin can be selected by configuring the Port Multiplexer(PORTMUX) Refer to the PORTMUX chapter for details
4 The direction for the associated port pin n must be configured as an output (PORTxDIR[n] = 1)5 Optional Enable the inverted waveform output for the associated port pin n (INVEN = 1 in PORTxPINnCTRL)
203342 Frequency (FRQ) Waveform GenerationFor frequency generation the period time (T) is controlled by the TCAnCMP0 register instead of the Period register(TCAnPER) The corresponding waveform generator output is toggled on each compare match between theTCAnCNT and TCAnCMPm registers
Figure 20-9 Frequency Waveform Generation
CNT
WG Output
MAX
TOP
BOTTOM
Period (T) Direction change CNT written
lsquolsquoupdatersquorsquo
The waveform frequency (fFRQ) is defined by the following equationFRQ = fCLK_PER2 CMPn+1where N represents the prescaler divider used (CLKSEL in TCAnCTRLA) and fCLK_PER is the peripheral clockfrequency
The maximum frequency of the waveform generated is half of the peripheral clock frequency (fCLK_PER2) whenTCAnCMP0 is written to 0x0000 and no prescaling is used (N = 1 CLKSEL = 0x0 in TCAnCTRLA)
203343 Single-Slope PWM GenerationFor single-slope Pulse-Width Modulation (PWM) generation the period (T) is controlled by TCAnPER while thevalues of the TCAnCMPm registers control the duty cycles of the generated waveforms The figure below showshow the counter counts from BOTTOM to TOP and then restarts from BOTTOM The waveform generator output isset at BOTTOM and cleared on the compare match between the TCAnCNT and TCAnCMPm registers
CMPn = BOTTOM will produce a static low signal on WOn while CMPn gt TOP will produce a static high signal onWOn
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 189
Figure 20-10 Single-Slope Pulse-Width Modulation
CNT
Output WOn
MAXTOP
CMPn
BOTTOM
Period (T) CMPn=BOTTOM CMPngtTOP lsquolsquoupdatersquorsquolsquolsquomatchrsquorsquo
The TCAnPER register defines the PWM resolution The minimum resolution is 2 bits (TCAPER = 0x0002) and themaximum resolution is 16 bits (TCAPER = MAX-1)
The following equation calculates the exact resolution in bits for single-slope PWM (RPWM_SS)PWM_SS = log PER+2log 2The single-slope PWM frequency (fPWM_SS) depends on the period setting (TCA_PER) the systemrsquos peripheral clockfrequency fCLK_PER and the TCA prescaler (CLKSEL in TCAnCTRLA) It is calculated by the following equationwhere N represents the prescaler divider usedPWM_SS = CLK_PER PER+1
203344 Dual-Slope PWMFor dual-slope PWM generation the period (T) is controlled by TCAnPER while the values of TCAnCMPm controlthe duty cycle of the WG output
The figure below shows how for dual-slope PWM the counter counts repeatedly from BOTTOM to TOP and thenfrom TOP to BOTTOM The waveform generator output is set on BOTTOM cleared on compare match when up-counting and set on compare match when down-counting
CMPn = BOTTOM will produce a static low signal on WOn while CMPn = TOP will produce a static high signal onWOn
Figure 20-11 Dual-Slope Pulse-Width Modulation
MAX
TOP
BOTTOM
CNT
Waveform Output WOn
Period (T) CMPn=BOTTOM CMPn=TOP lsquolsquoupdatersquorsquolsquolsquomatchrsquorsquo
CMPn
Using dual-slope PWM results in half the maximum operation frequency compared to single-slope PWM operationdue to twice the number of timer increments per period
The period register (TCAnPER) defines the PWM resolution The minimum resolution is 2 bits (TCAnPER =0x0003) and the maximum resolution is 16 bits (TCAnPER = MAX)
The following equation calculates the exact resolution in bits for dual-slope PWM (RPWM_DS)
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 190
PWM_DS = log PER+1log 2The PWM frequency depends on the period setting (TCAnPER) the peripheral clock frequency (fCLK_PER) and theprescaler divider used (CLKSEL in TCAnCTRLA) It is calculated by the following equationPWM_DS = CLK_PER2 sdot PERN represents the prescaler divider used
203345 Port Override for Waveform GenerationTo make the waveform generation available on the port pins the corresponding port pin direction must be set asoutput (PORTxDIR[n] = 1) The TCA will override the port pin values when the compare channel is enabled(CMPnEN = 1 in TCAnCTRLB) and a Waveform Generation mode is selected
The figure below shows the port override for TCA The timercounter compare channel will override the port pinoutput value (OUT) on the corresponding port pin Enabling inverted IO on the port pin (INVEN = 1 in PORTPINn)inverts the corresponding WG output
Figure 20-12 Port Override for TimerCounter Type A
Waveform
OUT
CMPnEN INVEN
WOn
20335 TimerCounter CommandsA set of commands can be issued by software to immediately change the state of the peripheral These commandsgive direct control of the UPDATE RESTART and RESET signals A command is issued by writing the respectivevalue to the Command bit field (CMD) in the Control E register (TCAnCTRLESET)
An UPDATE command has the same effect as when an UPDATE condition occurs except that the UPDATEcommand is not affected by the state of the Lock Update bit (LUPD) in the Control E register (TCAnCTRLE)
The software can force a restart of the current waveform period by issuing a RESTART command In this case thecounter direction and all compare outputs are set to lsquo0rsquo
A RESET command will set all timercounter registers to their initial values A RESET command can be issued onlywhen the timercounter is not running (ENABLE = 0 in TCAnCTRLA)
20336 Split Mode - Two 8-Bit TimerCounters
Split Mode OverviewTo double the number of timers and PWM channels in the TCA a Split mode is provided In this Split mode the 16-bittimercounter acts as two separate 8-bit timers which each have three compare channels for PWM generation TheSplit mode will only work with single-slope down-count Event controlled operation is not supported in Split mode
Activating Split mode results in changes to the functionality of some registers and register bits The modifications aredescribed in a separate register map (see 206 Register Summary - TCAn in Split Mode)
Split Mode Differences Compared to Normal Modebull Count
ndash Down-count onlyndash Low Byte Timer Counter Register (TCAnLCNT) and High Byte Timer Counter Register (TCAnHCNT) are
independentbull Waveform Generation
ndash Single-slope PWM only (WGMODE = SINGLESLOPE in TCAnCTRLB)bull Interrupt
ndash No change for Low Byte Timer Counter Register (TCAnLCNT)ndash Underflow interrupt for High Byte Timer Counter Register (TCAnHCNT)
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 191
ndash No compare interrupt or flag for High Byte Compare Register n (TCAnHCMPn)bull Event Actions Not Compatiblebull Buffer Registers and Buffer Valid Flags Unusedbull Register Access Byte Access to All Registers
Block DiagramFigure 20-13 TimerCounter Block Diagram Split ModeBase Counter
Counter
= 0
Control LogicHUNF(INT Req and Event)
BOTTOML
Compare Unit n
Waveform
LCMPn
WOn Out
= lsquolsquomatchrsquorsquo
BOTTOMH
lsquolsquocount lowrsquorsquo
= lsquolsquomatchrsquorsquo
WO[n+3] Out
= 0
lsquolsquocount highrsquorsquo
LUNF
HPER CTRLALPER
LCMPn
LCNTHCNT
HCMPn
lsquolsquoload highrsquorsquo
lsquolsquoload lowrsquorsquo
Clock Select
Waveform
Compare Unit n
(INT Req and Event)
(INT Req and Event)
Generation
Generation
Split Mode InitializationWhen shifting between Normal mode and Split mode the functionality of some registers and bits changes but theirvalues do not For this reason disabling the peripheral (ENABLE = 0 in TCAnCTRLA) and doing a hard Reset (CMD= RESET in TCAnCTRLESET) is recommended when changing the mode to avoid unexpected behavior
To start using the timercounter in basic Split mode after a hard Reset follow these steps1 Enable Split mode by writing a lsquo1rsquo to the Split mode enable bit in the Control D register (SPLITM in
TCAnCTRLD)2 Write a TOP value to the Period registers (TCAnPER)3 Enable the peripheral by writing a lsquo1rsquo to the ENABLE bit in the Control A register (TCAnCTRLA)
The counter will start counting clock ticks according to the prescaler setting in the Clock Select bit field(CLKSEL) in TCAnCTRLA
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 192
4 The counter values can be read from the Counter bit field in the Counter registers (TCAnCNT)
2034 EventsThe TCA can generate the events described in the table below All event generators except TCAn_HUNF are sharedbetween Normal mode and Split mode operationTable 20-2 Event Generators in TCA
Generator NameDescription Event
TypeGenerating
Clock Domain Length of EventPeripheral Event
TCAn
OVF_LUNFNormal mode Overflow
Split mode Low byte timer underflowPulse CLK_PER One CLK_PER
period
HUNFNormal mode Not available
Split mode High byte timer underflowPulse CLK_PER One CLK_PER
period
CMP0
Normal mode Compare Channel 0match
Split mode Low byte timer CompareChannel 0 match
Pulse CLK_PER One CLK_PERperiod
CMP1
Normal mode Compare Channel 1match
Split mode Low byte timer CompareChannel 1 match
Pulse CLK_PER One CLK_PERperiod
CMP2
Normal mode Compare Channel 2match
Split mode Low byte timer CompareChannel 2 match
Pulse CLK_PER One CLK_PERperiod
Note The conditions for generating an event are identical to those that will raise the corresponding interrupt flag inthe TCAnINTFLAGS register for both Normal mode and Split mode
The TCA has one event user for detecting and acting upon input events The table below describes the event userand the associated functionalityTable 20-3 Event User in TCA
User Name Description Input Detection AsyncSync
TCAn
Count on positive eventedge Edge Sync
Count on any event edge Edge Sync
Count while event signal ishigh Level Sync
Event level controls countdirection up when low anddown when high
Level Sync
The specific actions described in the table above are selected by writing to the Event Action bits (EVACT) in theEvent Control register (TCAnEVCTRL) Input events are enabled by writing a lsquo1rsquo to the Enable Count on Event Inputbit (CNTEI in TCAnEVCTRL)
Event inputs are not used in Split mode
Refer to the Event System (EVSYS) chapter for more details regarding event types and Event System configuration
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 193
2035 InterruptsTable 20-4 Available Interrupt Vectors and Sources in Normal Mode
Name Vector Description Conditions
OVF Overflow or underflow interrupt The counter has reached TOP or BOTTOM
CMP0 Compare Channel 0 interrupt Match between the counter value and the Compare 0 register
CMP1 Compare Channel 1 interrupt Match between the counter value and the Compare 1 register
CMP2 Compare Channel 2 interrupt Match between the counter value and the Compare 2 register
Table 20-5 Available Interrupt Vectors and Sources in Split Mode
Name Vector Description Conditions
LUNF Low-byte Underflow interrupt Low byte timer reaches BOTTOM
HUNF High-byte Underflow interrupt High byte timer reaches BOTTOM
LCMP0 Compare Channel 0 interrupt Match between the counter value and the low byte of the Compare 0register
LCMP1 Compare Channel 1 interrupt Match between the counter value and the low byte of the Compare 1register
LCMP2 Compare Channel 2 interrupt Match between the counter value and the low byte of the Compare 2register
When an interrupt condition occurs the corresponding interrupt flag is set in the Interrupt Flags register of theperipheral (peripheralINTFLAGS)
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheralrsquos InterruptControl (peripheralINTCTRL) register
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is setThe interrupt request remains active until the interrupt flag is cleared See the peripheralrsquos INTFLAGS register fordetails on how to clear interrupt flags
2036 Sleep Mode OperationThe timercounter will continue operation in Idle Sleep mode
ATmega32083209TCA - 16-bit TimerCounter Type A
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204 Register Summary - TCAn in Normal Mode
Offset Name Bit Pos
0x00 CTRLA 70 CLKSEL[20] ENABLE0x01 CTRLB 70 CMP2EN CMP1EN CMP0EN ALUPD WGMODE[20]0x02 CTRLC 70 CMP2OV CMP1OV CMP0OV0x03 CTRLD 70 SPLITM0x04 CTRLECLR 70 CMD[10] LUPD DIR0x05 CTRLESET 70 CMD[10] LUPD DIR0x06 CTRLFCLR 70 CMP2BV CMP1BV CMP0BV PERBV0x07 CTRLFSET 70 CMP2BV CMP1BV CMP0BV PERBV0x08 Reserved 0x09 EVCTRL 70 EVACT[20] CNTEI0x0A INTCTRL 70 CMP2 CMP1 CMP0 OVF0x0B INTFLAGS 70 CMP2 CMP1 CMP0 OVF0x0C
0x0D
Reserved
0x0E DBGCTRL 70 DBGRUN0x0F TEMP 70 TEMP[70]0x10
0x1F
Reserved
0x20 CNT70 CNT[70]158 CNT[158]
0x22
0x25Reserved
0x26 PER70 PER[70]158 PER[158]
0x28 CMP070 CMP[70]158 CMP[158]
0x2A CMP170 CMP[70]158 CMP[158]
0x2C CMP270 CMP[70]158 CMP[158]
0x2E
0x35Reserved
0x36 PERBUF70 PERBUF[70]158 PERBUF[158]
0x37 PERBUFH 70 PERBUF[158]
0x38 CMP0nBUF70 CMPBUF[70]158 CMPBUF[158]
0x3A CMP1nBUF70 CMPBUF[70]158 CMPBUF[158]
0x3C CMP2nBUF70 CMPBUF[70]158 CMPBUF[158]
205 Register Description - Normal Mode
ATmega32083209TCA - 16-bit TimerCounter Type A
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2051 Control A
Name CTRLAOffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CLKSEL[20] ENABLE
Access RW RW RW RW Reset 0 0 0 0
Bits 31 ndash CLKSEL[20] Clock SelectThese bits select the clock frequency for the timercounterValue Name Description0x0 DIV1 fTCA = fCLK_PER0x1 DIV2 fTCA = fCLK_PER20x2 DIV4 fTCA = fCLK_PER40x3 DIV8 fTCA = fCLK_PER80x4 DIV16 fTCA = fCLK_PER160x5 DIV64 fTCA = fCLK_PER640x6 DIV256 fTCA = fCLK_PER2560x7 DIV1024 fTCA = fCLK_PER1024
Bit 0 ndash ENABLE EnableValue Description0 The peripheral is disabled1 The peripheral is enabled
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 196
2052 Control B - Normal Mode
Name CTRLBOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CMP2EN CMP1EN CMP0EN ALUPD WGMODE[20]
Access RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0
Bits 4 5 6 ndash CMPEN Compare n EnableIn the FRQ and PWM Waveform Generation modes the Compare n Enable bits (CMPnEN) will make the waveformoutput available on the pin corresponding to WOn overriding the value in the corresponding PORT output registerThe corresponding pin direction must be configured as an output in the PORT peripheralValue Description0 Waveform output WOn will not be available on the corresponding pin1 Waveform output WOn will override the output value of the corresponding pin
Bit 3 ndash ALUPD Auto-Lock UpdateThe Auto-Lock Update bit controls the Lock Update (LUPD) bit in the TCAnCTRLE register When ALUPD is writtento lsquo1rsquo LUPD will be set to lsquo1rsquo until the Buffer Valid (CMPnBV) bits of all enabled compare channels are lsquo1rsquo Thiscondition will clear LUPDIt will remain cleared until the next UPDATE condition where the buffer values will be transferred to the CMPnregisters and LUPD will be set to lsquo1rsquo again This makes sure that the CMPnBUF register values are not transferred tothe CMPn registers until all enabled compare buffers are writtenValue Description0 LUPD in TCACTRLE is not altered by the system1 LUPD in TCACTRLE is set and cleared automatically
Bits 20 ndash WGMODE[20] Waveform Generation ModeThese bits select the Waveform Generation mode and control the counting sequence of the counter TOP valueUPDATE condition Interrupt condition and the type of waveform generatedNo waveform generation is performed in the Normal mode of operation For all other modes the waveform generatoroutput will only be directed to the port pins if the corresponding CMPnEN bit has been set The port pin direction mustbe set as outputTable 20-6 Timer Waveform Generation Mode
Value Group Configuration Mode of Operation TOP UPDATE OVF
0x0 NORMAL Normal PER TOP(1) TOP(1)
0x1 FRQ Frequency CMP0 TOP(1) TOP(1)
0x2 - Reserved - - -
0x3 SINGLESLOPE Single-slope PWM PER BOTTOM BOTTOM
0x4 - Reserved - - -
0x5 DSTOP Dual-slope PWM PER BOTTOM TOP
0x6 DSBOTH Dual-slope PWM PER BOTTOM TOP and BOTTOM
0x7 DSBOTTOM Dual-slope PWM PER BOTTOM BOTTOM
Note 1 When counting up
ATmega32083209TCA - 16-bit TimerCounter Type A
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2053 Control C - Normal Mode
Name CTRLCOffset 0x02Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CMP2OV CMP1OV CMP0OV
Access RW RW RW Reset 0 0 0
Bit 2 ndash CMP2OV Compare Output Value 2See CMP0OV
Bit 1 ndash CMP1OV Compare Output Value 1See CMP0OV
Bit 0 ndash CMP0OV Compare Output Value 0The CMPnOV bits allow direct access to the waveform generatorrsquos output compare value when the timercounter isnot enabled This is used to set or clear the WG output value when the timercounter is not running
ATmega32083209TCA - 16-bit TimerCounter Type A
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2054 Control D
Name CTRLDOffset 0x03Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 SPLITM
Access RW Reset 0
Bit 0 ndash SPLITM Enable Split ModeThis bit sets the timercounter in Split mode operation It will then work as two 8-bit timercounters The register mapwill change compared to normal 16-bit mode
ATmega32083209TCA - 16-bit TimerCounter Type A
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2055 Control Register E Clear - Normal Mode
Name CTRLECLROffset 0x04Reset 0x00Property -
This register can be used instead of a Read-Modify-Write (RMW) to clear individual bits by writing a lsquo1rsquo to its bitlocation
Bit 7 6 5 4 3 2 1 0 CMD[10] LUPD DIR
Access RW RW RW RW Reset 0 0 0 0
Bits 32 ndash CMD[10] CommandThese bits are used for software control of update restart and Reset of the timercounter The command bits arealways read as lsquo0rsquoValue Name Description0x0 NONE No command0x1 UPDATE Force update0x2 RESTART Force restart0x3 RESET Force hard Reset (ignored if the timercounter is enabled)
Bit 1 ndash LUPD Lock UpdateLock update can be used to ensure that all buffers are valid before an update is performedValue Description0 The buffered registers are updated as soon as an UPDATE condition has occurred1 No update of the buffered registers is performed even though an UPDATE condition has occurred
Bit 0 ndash DIR Counter DirectionNormally this bit is controlled in hardware by the Waveform Generation mode or by event actions but it can also bechanged from softwareValue Description0 The counter is counting up (incrementing)1 The counter is counting down (decrementing)
ATmega32083209TCA - 16-bit TimerCounter Type A
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2056 Control Register E Set - Normal Mode
Name CTRLESETOffset 0x05Reset 0x00Property -
This register can be used instead of a Read-Modify-Write (RMW) to set individual bits by writing a lsquo1rsquo to its bitlocation
Bit 7 6 5 4 3 2 1 0 CMD[10] LUPD DIR
Access RW RW RW RW Reset 0 0 0 0
Bits 32 ndash CMD[10] CommandThese bits are used for software control of update restart and Reset the timercounter The command bits are alwaysread as lsquo0rsquoValue Name Description0x0 NONE No command0x1 UPDATE Force update0x2 RESTART Force restart0x3 RESET Force hard Reset (ignored if the timercounter is enabled)
Bit 1 ndash LUPD Lock UpdateLocking the update ensures that all buffers are valid before an update is performedValue Description0 The buffered registers are updated as soon as an UPDATE condition has occurred1 No update of the buffered registers is performed even though an UPDATE condition has occurred
Bit 0 ndash DIR Counter DirectionNormally this bit is controlled in hardware by the Waveform Generation mode or by event actions but it can also bechanged from softwareValue Description0 The counter is counting up (incrementing)1 The counter is counting down (decrementing)
ATmega32083209TCA - 16-bit TimerCounter Type A
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2057 Control Register F Clear
Name CTRLFCLROffset 0x06Reset 0x00Property -
This register can be used instead of a Read-Modify-Write (RMW) to clear individual bits by writing a lsquo1rsquo to its bitlocation
Bit 7 6 5 4 3 2 1 0 CMP2BV CMP1BV CMP0BV PERBV
Access RW RW RW RW Reset 0 0 0 0
Bit 3 ndash CMP2BV Compare 2 Buffer ValidSee CMP0BV
Bit 2 ndash CMP1BV Compare 1 Buffer ValidSee CMP0BV
Bit 1 ndash CMP0BV Compare 0 Buffer ValidThe CMPnBV bits are set when a new value is written to the corresponding TCAnCMPnBUF register These bits areautomatically cleared on an UPDATE condition
Bit 0 ndash PERBV Period Buffer ValidThis bit is set when a new value is written to the TCAnPERBUF register This bit is automatically cleared on anUPDATE condition
ATmega32083209TCA - 16-bit TimerCounter Type A
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2058 Control Register F Set
Name CTRLFSETOffset 0x07Reset 0x00Property -
This register can be used instead of a Read-Modify-Write (RMW) to set individual bits by writing a lsquo1rsquo to its bitlocation
Bit 7 6 5 4 3 2 1 0 CMP2BV CMP1BV CMP0BV PERBV
Access RW RW RW RW Reset 0 0 0 0
Bit 3 ndash CMP2BV Compare 2 Buffer ValidSee CMP0BV
Bit 2 ndash CMP1BV Compare 1 Buffer ValidSee CMP0BV
Bit 1 ndash CMP0BV Compare 0 Buffer ValidThe CMPnBV bits are set when a new value is written to the corresponding TCAnCMPnBUF register These bits areautomatically cleared on an UPDATE condition
Bit 0 ndash PERBV Period Buffer ValidThis bit is set when a new value is written to the TCAnPERBUF register This bit is automatically cleared on anUPDATE condition
ATmega32083209TCA - 16-bit TimerCounter Type A
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2059 Event Control
Name EVCTRLOffset 0x09Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 EVACT[20] CNTEI
Access RW RW RW RW Reset 0 0 0 0
Bits 31 ndash EVACT[20] Event ActionThese bits define what action the counter will take upon certain event conditionsValue Name Description0x0 EVACT_POSEDGE Count on positive event edge0x1 EVACT_ANYEDGE Count on any event edge0x2 EVACT_HIGHLVL Count prescaled clock cycles while the event signal is high0x3 EVACT_UPDOWN Count prescaled clock cycles The event signal controls the count direction up
when low and down when highOther Reserved
Bit 0 ndash CNTEI Enable Count on Event InputValue Description0 Count on Event input is disabled1 Count on Event input is enabled according to EVACT bit field
ATmega32083209TCA - 16-bit TimerCounter Type A
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20510 Interrupt Control Register - Normal Mode
Name INTCTRLOffset 0x0AReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CMP2 CMP1 CMP0 OVF
Access RW RW RW RW Reset 0 0 0 0
Bit 6 ndash CMP2 Compare Channel 2 Interrupt EnableSee CMP0
Bit 5 ndash CMP1 Compare Channel 1 Interrupt EnableSee CMP0
Bit 4 ndash CMP0 Compare Channel 0 Interrupt EnableWriting the CMPn bit to lsquo1rsquo enables the interrupt from Compare Channel n
Bit 0 ndash OVF Timer OverflowUnderflow Interrupt EnableWriting the OVF bit to lsquo1rsquo enables the overflowunderflow interrupt
ATmega32083209TCA - 16-bit TimerCounter Type A
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20511 Interrupt Flag Register - Normal Mode
Name INTFLAGSOffset 0x0BReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CMP2 CMP1 CMP0 OVF
Access RW RW RW RW Reset 0 0 0 0
Bit 6 ndash CMP2 Compare Channel 2 Interrupt FlagSee the CMP0 flag description
Bit 5 ndash CMP1 Compare Channel 1 Interrupt FlagSee the CMP0 flag description
Bit 4 ndash CMP0 Compare Channel 0 Interrupt FlagThe Compare Interrupt flag (CMPn) is set on a compare match on the corresponding compare channelFor all modes of operation the CMPn flag will be set when a compare match occurs between the Count register(CNT) and the corresponding Compare register (CMPn) The CMPn flag is not cleared automatically It will be clearedonly by writing a lsquo1rsquo to its bit location
Bit 0 ndash OVF OverflowUnderflow Interrupt FlagThis flag is set either on a TOP (overflow) or BOTTOM (underflow) condition depending on the WGMODE settingThe OVF flag is not cleared automatically It will be cleared only by writing a lsquo1rsquo to its bit location
ATmega32083209TCA - 16-bit TimerCounter Type A
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20512 Debug Control Register
Name DBGCTRLOffset 0x0EReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DBGRUN
Access RW Reset 0
Bit 0 ndash DBGRUN Run in DebugValue Description0 The peripheral is halted in Break Debug mode and ignores events1 The peripheral will continue to run in Break Debug mode when the CPU is halted
ATmega32083209TCA - 16-bit TimerCounter Type A
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20513 Temporary Bits for 16-Bit Access
Name TEMPOffset 0x0FReset 0x00Property -
The Temporary register is used by the CPU for single-cycle 16-bit access to the 16-bit registers of this peripheral Itcan be read and written by software Refer to 16-bit access in the AVR CPU chapter There is one commonTemporary register for all the 16-bit registers of this peripheral
Bit 7 6 5 4 3 2 1 0 TEMP[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash TEMP[70] Temporary Bits for 16-bit Access
ATmega32083209TCA - 16-bit TimerCounter Type A
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20514 Counter Register - Normal Mode
Name CNTOffset 0x20Reset 0x00Property -
The TCAnCNTL and TCAnCNTH register pair represents the 16-bit value TCAnCNT The low byte [70] (suffix L) isaccessible at the original offset The high byte [158] (suffix H) can be accessed at offset + 0x01
CPU and UPDI write access has priority over internal updates of the register
Bit 15 14 13 12 11 10 9 8 CNT[158]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 CNT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 158 ndash CNT[158] Counter High ByteThese bits hold the MSB of the 16-bit Counter register
Bits 70 ndash CNT[70] Counter Low ByteThese bits hold the LSB of the 16-bit Counter register
ATmega32083209TCA - 16-bit TimerCounter Type A
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20515 Period Register - Normal Mode
Name PEROffset 0x26Reset 0xFFFFProperty -
TCAnPER contains the 16-bit TOP value in the timercounter in all modes of operation except Frequency WaveformGeneration (FRQ)
The TCAnPERL and TCAnPERH register pair represents the 16-bit value TCAnPER The low byte [70] (suffix L)is accessible at the original offset The high byte [158] (suffix H) can be accessed at offset + 0x01
Bit 15 14 13 12 11 10 9 8 PER[158]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0 PER[70]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bits 158 ndash PER[158] Periodic High ByteThese bits hold the MSB of the 16-bit Period register
Bits 70 ndash PER[70] Periodic Low ByteThese bits hold the LSB of the 16-bit Period register
ATmega32083209TCA - 16-bit TimerCounter Type A
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20516 Compare n Register - Normal Mode
Name CMPnOffset 0x28 + n0x02 [n=02]Reset 0x00Property -
This register is continuously compared to the counter value Normally the outputs from the comparators are used togenerate waveforms
TCAnCMPn registers are updated with the buffer value from their corresponding TCAnCMPnBUF register when anUPDATE condition occurs
The TCAnCMPnL and TCAnCMPnH register pair represents the 16-bit value TCAnCMPn The low byte [70](suffix L) is accessible at the original offset The high byte [158] (suffix H) can be accessed at offset + 0x01
Bit 15 14 13 12 11 10 9 8 CMP[158]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 CMP[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 158 ndash CMP[158] Compare High ByteThese bits hold the MSB of the 16-bit Compare register
Bits 70 ndash CMP[70] Compare Low ByteThese bits hold the LSB of the 16-bit Compare register
ATmega32083209TCA - 16-bit TimerCounter Type A
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20517 Period Buffer Register
Name PERBUFOffset 0x36Reset 0xFFFFProperty -
This register serves as the buffer for the Period register (TCAnPER) Writing to this register from the CPU or UPDIwill set the Period Buffer Valid bit (PERBV) in the TCAnCTRLF register
The TCAnPERBUFL and TCAnPERBUFH register pair represents the 16-bit value TCAnPERBUF The low byte[70] (suffix L) is accessible at the original offset The high byte [158] (suffix H) can be accessed at offset + 0x01
Bit 15 14 13 12 11 10 9 8 PERBUF[158]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0 PERBUF[70]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bits 158 ndash PERBUF[158] Period Buffer High ByteThese bits hold the MSB of the 16-bit Period Buffer register
Bits 70 ndash PERBUF[70] Period Buffer Low ByteThese bits hold the LSB of the 16-bit Period Buffer register
ATmega32083209TCA - 16-bit TimerCounter Type A
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20518 Period Buffer Register High
Name PERBUFHOffset 0x37Reset 0xFFProperty -
Bit 7 6 5 4 3 2 1 0 PERBUF[158]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bits 70 ndash PERBUF[158] Period Buffer High ByteThese bits hold the MSB of the 16-bit Period Buffer register Refer to TCAnPERBUFL register description for details
ATmega32083209TCA - 16-bit TimerCounter Type A
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20519 Compare n Buffer Register
Name CMPnBUFOffset 0x38 + n0x02 [n=02]Reset 0x00Property -
This register serves as the buffer for the associated Compare register (TCAnCMPn) Writing to this register from theCPU or UPDI will set the Compare Buffer valid bit (CMPnBV) in the TCAnCTRLF register
The TCAnCMPnBUFL and TCAnCMPnBUFH register pair represents the 16-bit value TCAnCMPnBUF The lowbyte [70] (suffix L) is accessible at the original offset The high byte [158] (suffix H) can be accessed at offset+ 0x01
Bit 15 14 13 12 11 10 9 8 CMPBUF[158]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 CMPBUF[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 158 ndash CMPBUF[158] Compare High ByteThese bits hold the MSB of the 16-bit Compare Buffer register
Bits 70 ndash CMPBUF[70] Compare Low ByteThese bits hold the LSB of the 16-bit Compare Buffer register
ATmega32083209TCA - 16-bit TimerCounter Type A
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206 Register Summary - TCAn in Split Mode
Offset Name Bit Pos
0x00 CTRLA 70 CLKSEL[20] ENABLE0x01 CTRLB 70 HCMP2EN HCMP1EN HCMP0EN LCMP2EN LCMP1EN LCMP0EN0x02 CTRLC 70 HCMP2OV HCMP1OV HCMP0OV LCMP2OV LCMP1OV LCMP0OV0x03 CTRLD 70 SPLITM0x04 CTRLECLR 70 CMD[10] CMDEN[10]0x05 CTRLESET 70 CMD[10] CMDEN[10]0x06
0x09
Reserved
0x0A INTCTRL 70 LCMP2 LCMP1 LCMP0 HUNF LUNF0x0B INTFLAGS 70 LCMP2 LCMP1 LCMP0 HUNF LUNF0x0C
0x0D
Reserved
0x0E DBGCTRL 70 DBGRUN0x0F
0x1F
Reserved
0x20 LCNT 70 LCNT[70]0x21 HCNT 70 HCNT[70]0x22
0x25
Reserved
0x26 LPER 70 LPER[70]0x27 HPER 70 HPER[70]0x28 LCMP0 70 LCMP[70]0x29 HCMP0 70 HCMP[70]0x2A LCMP1 70 LCMP[70]0x2B HCMP1 70 HCMP[70]0x2C LCMP2 70 LCMP[70]0x2D HCMP2 70 HCMP[70]
207 Register Description - Split Mode
ATmega32083209TCA - 16-bit TimerCounter Type A
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2071 Control A
Name CTRLAOffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CLKSEL[20] ENABLE
Access RW RW RW RW Reset 0 0 0 0
Bits 31 ndash CLKSEL[20] Clock SelectThese bits select the clock frequency for the timercounterValue Name Description0x0 DIV1 fTCA = fCLK_PER0x1 DIV2 fTCA = fCLK_PER20x2 DIV4 fTCA = fCLK_PER40x3 DIV8 fTCA = fCLK_PER80x4 DIV16 fTCA = fCLK_PER160x5 DIV64 fTCA = fCLK_PER640x6 DIV256 fTCA = fCLK_PER2560x7 DIV1024 fTCA = fCLK_PER1024
Bit 0 ndash ENABLE EnableValue Description0 The peripheral is disabled1 The peripheral is enabled
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 216
2072 Control B - Split Mode
Name CTRLBOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 HCMP2EN HCMP1EN HCMP0EN LCMP2EN LCMP1EN LCMP0EN
Access RW RW RW RW RW RW Reset 0 0 0 0 0 0
Bit 6 ndash HCMP2EN High byte Compare 2 EnableSee HCMP0EN
Bit 5 ndash HCMP1EN High byte Compare 1 EnableSee HCMP0EN
Bit 4 ndash HCMP0EN High byte Compare 0 EnableSetting the HCMPnEN bit in the FRQ or PWM Waveform Generation mode of operation will override the port outputregister for the corresponding WO[n+3] pin
Bit 2 ndash LCMP2EN Low byte Compare 2 EnableSee LCMP0EN
Bit 1 ndash LCMP1EN Low byte Compare 1 EnableSee LCMP0EN
Bit 0 ndash LCMP0EN Low byte Compare 0 EnableSetting the LCMPnEN bit in the FRQ or PWM Waveform Generation mode of operation will override the port outputregister for the corresponding WOn pin
ATmega32083209TCA - 16-bit TimerCounter Type A
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2073 Control C - Split Mode
Name CTRLCOffset 0x02Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 HCMP2OV HCMP1OV HCMP0OV LCMP2OV LCMP1OV LCMP0OV
Access RW RW RW RW RW RW Reset 0 0 0 0 0 0
Bit 6 ndash HCMP2OV High byte Compare 2 Output ValueSee HCMP0OV
Bit 5 ndash HCMP1OV High byte Compare 1 Output ValueSee HCMP0OV
Bit 4 ndash HCMP0OV High byte Compare 0 Output ValueThe HCMPnOV bit allows direct access to the output compare value of the waveform generator when the timercounter is not enabled This is used to set or clear the WO[n+3] output value when the timercounter is not running
Bit 2 ndash LCMP2OV Low byte Compare 2 Output ValueSee LCMP0OV
Bit 1 ndash LCMP1OV Low byte Compare 1 Output ValueSee LCMP0OV
Bit 0 ndash LCMP0OV Low byte Compare 0 Output ValueThe LCMPnOV bit allows direct access to the output compare value of the waveform generator when the timercounter is not enabled This is used to set or clear the WOn output value when the timercounter is not running
ATmega32083209TCA - 16-bit TimerCounter Type A
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2074 Control D
Name CTRLDOffset 0x03Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 SPLITM
Access RW Reset 0
Bit 0 ndash SPLITM Enable Split ModeThis bit sets the timercounter in Split mode operation It will then work as two 8-bit timercounters The register mapwill change compared to normal 16-bit mode
ATmega32083209TCA - 16-bit TimerCounter Type A
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2075 Control Register E Clear - Split Mode
Name CTRLECLROffset 0x04Reset 0x00Property -
This register can be used instead of a Read-Modify-Write (RMW) to clear individual bits by writing a lsquo1rsquo to its bitlocation
Bit 7 6 5 4 3 2 1 0 CMD[10] CMDEN[10]
Access RW RW RW RW Reset 0 0 0 0
Bits 32 ndash CMD[10] CommandThese bits are used for software control of update restart and Reset of the timercounter The command bits arealways read as lsquo0rsquoValue Name Description0x0 NONE No command0x1 - Reserved0x2 RESTART Force restart0x3 RESET Force hard Reset (ignored if the timercounter is enabled)
Bits 10 ndash CMDEN[10] Command EnableThese bits configure what timercounters the command given by the CMD-bits will be applied toValue Name Description0x0 NONE None0x1 - Reserved0x2 - Reserved0x3 BOTH Command (CMD) will be applied to both low byte and high byte timercounter
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 220
2076 Control Register E Set - Split Mode
Name CTRLESETOffset 0x05Reset 0x00Property -
This register can be used instead of a Read-Modify-Write (RMW) to set individual bits by writing a lsquo1rsquo to its bitlocation
Bit 7 6 5 4 3 2 1 0 CMD[10] CMDEN[10]
Access RW RW RW RW Reset 0 0 0 0
Bits 32 ndash CMD[10] CommandThese bits are used for software control of update restart and Reset of the timercounter The command bits arealways read as lsquo0rsquo The CMD bits must be used together with the Command Enable (CMDEN) bits Using the RESETcommand requires that both low byte and high byte timercounter are selected with CMDENValue Name Description0x0 NONE No command0x1 - Reserved0x2 RESTART Force restart0x3 RESET Force hard Reset (ignored if the timercounter is enabled)
Bits 10 ndash CMDEN[10] Command EnableThese bits configure what timercounters the command given by the CMD-bits will be applied toValue Name Description0x0 NONE None0x1 - Reserved0x2 - Reserved0x3 BOTH Command (CMD) will be applied to both low byte and high byte timercounter
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 221
2077 Interrupt Control Register - Split Mode
Name INTCTRLOffset 0x0AReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 LCMP2 LCMP1 LCMP0 HUNF LUNF
Access RW RW RW RW RW Reset 0 0 0 0 0
Bit 6 ndash LCMP2 Low byte Compare Channel 0 Interrupt EnableSee LCMP0
Bit 5 ndash LCMP1 Low byte Compare Channel 1 Interrupt EnableSee LCMP0
Bit 4 ndash LCMP0 Low byte Compare Channel 0 Interrupt EnableWriting the LCMPn bit to lsquo1rsquo enables the low byte Compare Channel n interrupt
Bit 1 ndash HUNF High byte Underflow Interrupt EnableWriting the HUNF bit to lsquo1rsquo enables the high byte underflow interrupt
Bit 0 ndash LUNF Low byte Underflow Interrupt EnableWriting the LUNF bit to lsquo1rsquo enables the low byte underflow interrupt
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 222
2078 Interrupt Flag Register - Split Mode
Name INTFLAGSOffset 0x0BReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 LCMP2 LCMP1 LCMP0 HUNF LUNF
Access RW RW RW RW RW Reset 0 0 0 0 0
Bit 6 ndash LCMP2 Low byte Compare Channel 0 Interrupt FlagSee LCMP0 flag description
Bit 5 ndash LCMP1 Low byte Compare Channel 0 Interrupt FlagSee LCMP0 flag description
Bit 4 ndash LCMP0 Low byte Compare Channel 0 Interrupt FlagThe Low byte Compare Interrupt flag (LCMPn) is set on a compare match on the corresponding compare channel inthe low byte timerFor all modes of operation the LCMPn flag will be set when a compare match occurs between the Low Byte TimerCounter register (TCAnLCNT) and the corresponding compare register (TCAnLCMPn) The LCMPn flag will not becleared automatically and has to be cleared by software This is done by writing a lsquo1rsquo to its bit location
Bit 1 ndash HUNF High byte Underflow Interrupt FlagThis flag is set on a high byte timer BOTTOM (underflow) condition HUNF is not automatically cleared and needs tobe cleared by software This is done by writing a lsquo1rsquo to its bit location
Bit 0 ndash LUNF Low byte Underflow Interrupt FlagThis flag is set on a low byte timer BOTTOM (underflow) condition LUNF is not automatically cleared and needs tobe cleared by software This is done by writing a lsquo1rsquo to its bit location
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 223
2079 Debug Control Register
Name DBGCTRLOffset 0x0EReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DBGRUN
Access RW Reset 0
Bit 0 ndash DBGRUN Run in DebugValue Description0 The peripheral is halted in Break Debug mode and ignores events1 The peripheral will continue to run in Break Debug mode when the CPU is halted
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 224
20710 Low Byte Timer Counter Register - Split Mode
Name LCNTOffset 0x20Reset 0x00Property -
TCAnLCNT contains the counter value for the low byte timer CPU and UPDI write access has priority over countclear or reload of the counter
Bit 7 6 5 4 3 2 1 0 LCNT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash LCNT[70] Counter Value for Low Byte TimerThese bits define the counter value of the low byte timer
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 225
20711 High Byte Timer Counter Register - Split Mode
Name HCNTOffset 0x21Reset 0x00Property -
TCAnHCNT contains the counter value for the high byte timer CPU and UPDI write access has priority over countclear or reload of the counter
Bit 7 6 5 4 3 2 1 0 HCNT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash HCNT[70] Counter Value for High Byte TimerThese bits define the counter value in high byte timer
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 226
20712 Low Byte Timer Period Register - Split Mode
Name LPEROffset 0x26Reset 0x00Property -
The TCAnLPER register contains the TOP value for the low byte timer
Bit 7 6 5 4 3 2 1 0 LPER[70]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bits 70 ndash LPER[70] Period Value Low Byte TimerThese bits hold the TOP value for the low byte timer
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 227
20713 High Byte Period Register - Split Mode
Name HPEROffset 0x27Reset 0x00Property -
The TCAnHPER register contains the TOP value for the high byte timer
Bit 7 6 5 4 3 2 1 0 HPER[70]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bits 70 ndash HPER[70] Period Value High Byte TimerThese bits hold the TOP value for the high byte timer
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 228
20714 Compare Register n For Low Byte Timer - Split Mode
Name LCMPOffset 0x28 + n0x02 [n=02]Reset 0x00Property -
The TCAnLCMPn register represents the compare value of Compare Channel n for the low byte timer This registeris continuously compared to the counter value of the low byte timer TCAnLCNT Normally the outputs from thecomparators are then used to generate waveforms
Bit 7 6 5 4 3 2 1 0 LCMP[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash LCMP[70] Compare Value of Channel nThese bits hold the compare value of channel n that is compared to TCAnLCNT
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 229
20715 High Byte Compare Register n - Split Mode
Name HCMPOffset 0x29 + n0x02 [n=02]Reset 0x00Property -
The TCAnHCMPn register represents the compare value of Compare Channel n for the high byte timer This registeris continuously compared to the counter value of the high byte timer TCAnHCNT Normally the outputs from thecomparators are then used to generate waveforms
Bit 7 6 5 4 3 2 1 0 HCMP[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash HCMP[70] Compare Value of Channel nThese bits hold the compare value of channel n that is compared to TCAnHCNT
ATmega32083209TCA - 16-bit TimerCounter Type A
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 230
21 TCB - 16-bit TimerCounter Type B
211 Featuresbull 16-bit Counter Operation Modes
ndash Periodic interruptndash Time-out checkndash Input capture
bull On eventbull Frequency measurementbull Pulse-width measurementbull Frequency and pulse-width measurement
ndash Single-shotndash 8-bit Pulse-Width Modulation (PWM)
bull Noise Canceler on Event Inputbull Synchronize Operation with TCAn
212 OverviewThe capabilities of the 16-bit TimerCounter type B (TCB) include frequency and waveform generation and inputcapture on event with time and frequency measurement of digital signals The TCB consists of a base counter andcontrol logic that can be set in one of eight different modes each mode providing unique functionality The basecounter is clocked by the peripheral clock with optional prescaling
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 231
2121 Block DiagramFigure 21-1 TimerCounter Type B Block
Counter
CTRLA
CTRLB
EVCTRL
Control
Logic
=
Waveform
Generation
CNT
CCMP
Clear
Count
Match
CAPT(Interrupt Request and Events)
WO
Clock Select
Mode
= 0BOTTOM
Events
Event Action
The timercounter can be clocked from the Peripheral Clock (CLK_PER) or a 16-bit TimerCounter type A(CLK_TCAn)
Figure 21-2 TimerCounter Clock Logic
CTRLA
CLK_PER
DIV2CLK_TCAn
Events
CNT
Control
Logic
CLK_TCB
ATmega32083209TCB - 16-bit TimerCounter Type B
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The Clock Select (CLKSEL) bit field in the Control A (TCBnCTRLA) register selects one of the prescaler outputsdirectly as the clock (CLK_TCB) input
Setting the timercounter to use the clock from a TCAn allows the timercounter to run in sync with that TCAn
By using the EVSYS any event source such as an external clock signal on any IO pin may be used as a controllogic input When an event action controlled operation is used the clock selection must be set to use an eventchannel as the counter input
2122 Signal Description
Signal Description Type
WO Digital Asynchronous Output Waveform Output
213 Functional Description
2131 DefinitionsThe following definitions are used throughout the documentation
Table 21-1 TimerCounter Definitions
Name Description
BOTTOM The counter reaches BOTTOM when it becomes 0x0000
MAX The counter reaches maximum when it becomes 0xFFFF
TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence
CNT Counter register value
CCMP CaptureCompare register value
Note In general the term lsquotimerrsquo is used when the timercounter is counting periodic clock ticks The term lsquocounterrsquois used when the input signal has sporadic or irregular ticks
2132 InitializationBy default the TCB is in Periodic Interrupt mode Follow these steps to start using it
1 Write a TOP value to the CompareCapture (TCBnCCMP) register2 Enable the counter by writing a lsquo1rsquo to the ENABLE bit in the Control A (TCBnCTRLA) register
The counter will start counting clock ticks according to the prescaler setting in the Clock Select (CLKSEL) bitfield in the Control A (TCBnCTRLA) register
3 The counter value can be read from the Count (TCBnCNT) register The peripheral will generate a CAPTinterrupt and event when the CNT value reaches TOP31 If the CompareCapture register is modified to a value lower than the current Count register the
peripheral will count to MAX and wrap around
2133 Operation
21331 ModesThe timer can be configured to run in one of the eight different modes described in the sections below The eventpulse needs to be longer than one system clock cycle in order to ensure edge detection
213311 Periodic Interrupt ModeIn the Periodic Interrupt mode the counter counts to the capture value and restarts from BOTTOM A CAPT interruptand event is generated when the counter is equal to TOP If TOP is updated to a value lower than count uponreaching MAX the counter restarts from BOTTOM
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 233
Figure 21-3 Periodic Interrupt Mode
BOTTOM
MAX
TOP
CNT
TOP changed to
a value lower than CNTCNT set to BOTTOM
CAPT(Interrupt Request and Event)
213312 Time-Out Check ModeIn the Time-Out Check mode the peripheral starts counting on the first signal edge and stops on the next signal edgedetected on the event input channel Start or Stop edge is determined by the Event Edge (EDGE) bit in the EventControl (TCBnEVCTRL) register If the Count (TCBnCNT) register reaches TOP before the second edge a CAPTinterrupt and event will be generated In Freeze state after a Stop edge is detected the counter will restart on a newStart edge If TOP is updated to a value lower than the Count (TCBnCNT) register upon reaching MAX the counterrestarts from BOTTOM Reading the Count (TCBnCNT) register or CompareCapture (TCBnCCMP) register orwriting the Run (RUN) bit in the Status (TCBnSTATUS) register in Freeze state will have no effectFigure 21-4 Time-Out Check Mode
CNT
BOTTOM
MAX
TOP
Event Detector
TOP changed to a value lower
than CNT
CNT set to
BOTTOM
Event Input CAPT(Interrupt Request and Event)
213313 Input Capture on Event ModeIn the Input Capture on Event mode the counter will count from BOTTOM to MAX continuously When an event isdetected the Count (TCBnCNT) register value is transferred to the CompareCapture (TCBnCCMP) register and aCAPT interrupt and event is generated The Event edge detector that can be configured to trigger a capture on eitherrising or falling edges
The figure below shows the input capture unit configured to capture on the falling edge of the event input signal TheCAPT Interrupt flag is automatically cleared after the low byte of the CompareCapture (TCBnCCMP) register hasbeen read
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 234
Figure 21-5 Input Capture on Event
CNT
MAX
BOTTOM
CNT set to
BOTTOM
Copy CNT to
CCMP and CAPT
Copy CNT to
CCMP and CAPT
Event Detector
Event Input CAPT(Interrupt Request and Event)
It is recommended to write zero to the TCBnCNT register when entering this mode from any other mode
213314 Input Capture Frequency Measurement ModeIn the Input Capture Frequency Measurement mode the TCB captures the counter value and restarts on either apositive or negative edge of the event input signal
The CAPT Interrupt flag is automatically cleared after the low byte of the CompareCapture (TCBnCCMP) registerhas been read
The figure below illustrates this mode when configured to act on rising edge
Figure 21-6 Input Capture Frequency Measurement
CNT
MAX
BOTTOM
Event Detector
Event Input
CNT set to
BOTTOM
Copy CNT to CCMP
CAPT and restart
Copy CNT to CCMP
CAPT and restart
CAPT(Interrupt Request and Event)
213315 Input Capture Pulse-Width Measurement ModeIn the Input Capture Pulse-Width Measurement mode the input capture pulse-width measurement will restart thecounter on a positive edge and capture on the next falling edge before an interrupt request is generated The CAPTInterrupt flag is automatically cleared after the low byte of the CompareCapture (TCBnCCMP) register has beenread The timer will automatically switch between rising and falling edge detection but a minimum edge separation oftwo clock cycles is required for correct behavior
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 235
Figure 21-7 Input Capture Pulse-Width Measurement
Event Input
Edge Detector
CNT
MAX
BOTTOM
Start counterCopy CNT to
CCMP and CAPT
Restart
counter
Copy CNT to
CCMP and CAPT
CNT set to
BOTTOM
CAPT(Interrupt Request and Event)
213316 Input Capture Frequency and Pulse-Width Measurement ModeIn the Input Capture Frequency and Pulse-Width Measurement mode the timer will start counting when a positiveedge is detected on the event input signal The count value is captured on the following falling edge The counterstops when the second rising edge of the event input signal is detected This will set the interrupt flag
The CAPT Interrupt flag is automatically cleared after the low byte of the CompareCapture (TCBnCCMP) registerhas been read and the timercounter is ready for a new capture sequence Therefore the Count (TCBnCNT)register must be read before the CompareCapture (TCBnCCMP) register since it is reset to BOTTOM at the nextpositive edge of the event input signal
Figure 21-8 Input Capture Frequency and Pulse-Width Measurement
CNT
MAX
BOTTOM
Start
counter
Copy CNT to
CCMP
Stop counter and
CAPT
CPU reads the
CCMP register
Ignored until CPU
reads CCMP register
Trigger next capture
sequence
Event Detector
Event InputCAPT(Interrupt Request and Event)
213317 Single-Shot ModeThe Single-Shot mode can be used to generate a pulse with a duration defined by the Compare (TCBnCCMP)register every time a rising or falling edge is observed on a connected event channel
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 236
When the counter is stopped the output pin is driven to low If an event is detected on the connected event channelthe timer will reset and start counting from BOTTOM to TOP while driving its output high The RUN bit in the Status(TCBnSTATUS) register can be read to see if the counter is counting or not When the Counter register reaches theCCMP register value the counter will stop and the output pin will go low for at least one prescaler cycle A new eventarriving during this time will be ignored There is a two clock-cycle delay from when the event is received until theoutput is set high
The counter will start counting as soon as the module is enabled even without triggering an event This is preventedby writing TOP to the Counter register Similar behavior is seen if the Event Edge (EDGE) bit in the Event Control(TCBnEVCTRL) register is lsquo1rsquo while the module is enabled Writing TOP to the Counter register prevents this as well
If the Event Asynchronous (ASYNC) bit in the Control B (TCBnCTRLB) register is written to lsquo1rsquo the timer will reactasynchronously to an incoming event An edge on the event will immediately cause the output signal to be set Thecounter will still start counting two clock cycles after the event is received
Figure 21-9 Single-Shot Mode
Edge Detector
CNT
TOP
BOTTOM
Event starts
counter
Counter reaches
TOP value
Output
Ignored Ignored
Event starts
counter
Counter reaches
TOP value
CAPT(Interrupt Request and Event)
213318 8-Bit PWM ModeThe TCB can be configured to run in 8-bit PWM mode where each of the register pairs in the 16-bit CompareCapture (TCBnCCMPH and TCBnCCMPL) register are used as individual Compare registers The period (T) iscontrolled by CCMPH while CCMPL controls the duty cycle of the waveform The counter will continuously countfrom BOTTOM to CCMPL and the output will be set at BOTTOM and cleared when the counter reaches CCMPH
CCMPH is the number of cycles for which the output will be driven high CCMPL+1 is the period of the output pulse
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 237
Figure 21-10 8-Bit PWM Mode
CNT
MAX
TOP
Period (T)
BOTTOM
Output
CCMPH=BOTTOM
CCMPH
CCMPH=TOP CCMPHgtTOP
CCMPL
CAPT(Interrupt Request and Event)
21332 OutputTimer synchronization and output logic level are dependent on the selected Timer Mode (CNTMODE) bit field inControl B (TCBnCTRLB) register In Single-Shot mode the timercounter can be configured so that the signalgeneration happens asynchronously to an incoming event (ASYNC = 1 in TCBnCTRLB) The output signal is thenset immediately at the incoming event instead of being synchronized to the TCB clock Even though the output is setimmediately it will take two to three CLK_TCB cycles before the counter starts counting
The different configurations and their impact on the output are listed in the table belowTable 21-2 Output Configuration
CCMPEN CNTMODE ASYNC Output
1
Single-Shot mode
0The output is high whenthe counter starts and theoutput is low when thecounter stops
1The output is high whenthe event arrives and theoutput is low when thecounter stops
8-bit PWM mode Not applicable 8-bit PWM mode
Other modes Not applicableThe output initial level setsthe CCMPINIT bit in theTCBnCTRLB register
0 Not applicable Not applicable No output
It is not recommended to change modes while the peripheral is enabled as this can produce an unpredictable outputThere is a possibility that an interrupt flag is set during the timer configuration It is recommended to clear the TimerCounter Interrupt Flags (TCBnINTFLAGS) register after configuring the peripheral
21333 Noise CancelerThe Noise Canceler improves the noise immunity by using a simple digital filter scheme When the Noise Filter(FILTER) bit in the Event Control (TCBnEVCTRL) register is enabled the peripheral monitors the event channel andkeeps a record of the last four observed samples If four consecutive samples are equal the input is considered to bestable and the signal is fed to the edge detector
When enabled the Noise Canceler introduces an additional delay of four system clock cycles between a changeapplied to the input and the update of the Input Compare register
The Noise Canceler uses the system clock and is therefore not affected by the prescaler
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 238
21334 Synchronized with TimerCounter Type AThe TCB can be configured to use the clock (CLK_TCA) of a TimerCounter type A (TCAn) by writing to the ClockSelect bit field (CLKSEL) in the Control A register (TCBnCTRLA) In this setting the TCB will count on the exactsame clock source as selected in TCAn
When the Synchronize Update (SYNCUPD) bit in the Control A (TCBnCTRLA) register is written to lsquo1rsquo the TCBcounter will restart when the TCAn counter restarts
2134 EventsThe TCB can generate the events described in the following tableTable 21-3 Event Generators in TCB
Generator NameDescription Event Type Generating Clock Domain Length of Event
Peripheral Event
TCBn CAPT CAPT flag set Pulse CLK_PER One CLK_PER period
The conditions for generating the CAPT and OVF events are identical to those that will raise the correspondinginterrupt flags in the TimerCounter Interrupt Flags (TCBnINTFLAGS) register Refer to the Event System section formore details regarding event users and Event System configuration
The TCB can receive the events described in the following tableTable 21-4 Event Users and Available Event Actions in TCB
User NameDescription Input Detection AsyncSync
Peripheral Input
TCBnCAPT
Time-Out Check Count mode
Edge
Sync
Input Capture on Event Count mode
Input Capture Frequency Measurement Count mode
Input Capture Pulse-Width Measurement Count mode
Input Capture Frequency and Pulse-Width MeasurementCount mode
Single-Shot Count mode Both
COUNT Event as clock source in combination with a count mode Sync
CAPT and COUNT are TCB event users that detect and act upon input events
The COUNT event user is enabled on the peripheral by modifying the Clock Select (CLKSEL) bit field in the Control A(TCBnCTRLA) register to EVENT and setting up the Event System accordingly
If the Capture Event Input Enable (CAPTEI) bit in the Event Control (TCBnEVCTRL) register is written to lsquo1rsquoincoming events will result in an event action as defined by the Event Edge (EDGE) bit in Event Control(TCBnEVCTRL) register and the Timer Mode (CNTMODE) bit field in Control B (TCBnCTRLB) register The eventneeds to last for at least one CLK_PER cycle to be recognized
If the Asynchronous mode is enabled for Single-Shot mode the event is edge-triggered and will capture changes onthe event input shorter than one system clock cycle
2135 InterruptsTable 21-5 Available Interrupt Vectors and Sources
Name Vector Description Conditions
CAPT TCB interrupt Depending on the operating mode See the description of the CAPT bit in theTCBnINTFLAG register
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 239
When an interrupt condition occurs the corresponding interrupt flag is set in the Interrupt Flags register of theperipheral (peripheralINTFLAGS)
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheralrsquos InterruptControl (peripheralINTCTRL) register
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is setThe interrupt request remains active until the interrupt flag is cleared See the peripheralrsquos INTFLAGS register fordetails on how to clear interrupt flags
2136 Sleep Mode OperationTCBn is by default disabled in Standby Sleep mode It will be halted as soon as the Sleep mode is entered
The module can stay fully operational in the Standby Sleep mode if the Run Standby (RUNSTDBY) bit in theTCBnCTRLA register is written to lsquo1rsquo
All operations are halted in Power-Down Sleep mode
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 240
214 Register Summary - TCB
Offset Name Bit Pos
0x00 CTRLA 70 RUNSTDBY SYNCUPD CLKSEL[10] ENABLE0x01 CTRLB 70 ASYNC CCMPINIT CCMPEN CNTMODE[20]0x02
0x03
Reserved
0x04 EVCTRL 70 FILTER EDGE CAPTEI0x05 INTCTRL 70 CAPT0x06 INTFLAGS 70 CAPT0x07 STATUS 70 RUN0x08 DBGCTRL 70 DBGRUN0x09 TEMP 70 TEMP[70]
0x0A CNT70 CNT[70]158 CNT[158]
0x0C CCMP70 CCMP[70]158 CCMP[158]
215 Register Description
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 241
2151 Control A
Name CTRLAOffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 RUNSTDBY SYNCUPD CLKSEL[10] ENABLE
Access RW RW RW RW RW Reset 0 0 0 0 0
Bit 6 ndash RUNSTDBY Run in StandbyWriting a lsquo1rsquo to this bit will enable the peripheral to run in Standby Sleep mode Not applicable when CLKSEL is set to0x2 (CLK_TCA)
Bit 4 ndash SYNCUPD Synchronize UpdateWhen this bit is written to lsquo1rsquo the TCB will restart whenever TCA0 is restarted or overflows This can be used tosynchronize capture with the PWM period
Bits 21 ndash CLKSEL[10] Clock SelectWriting these bits selects the clock source for this peripheral
Value Name Description
0x0 CLKDIV1 CLK_PER
0x1 CLKDIV2 CLK_PER 2
0x2 CLKTCA Use CLK_TCA from TCA0
0x3 Reserved
Bit 0 ndash ENABLE EnableWriting this bit to lsquo1rsquo enables the TimerCounter type B peripheral
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 242
2152 Control B
Name CTRLBOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 ASYNC CCMPINIT CCMPEN CNTMODE[20]
Access RW RW RW RW RW RW Reset 0 0 0 0 0 0
Bit 6 ndash ASYNC Asynchronous EnableWriting this bit to lsquo1rsquo will allow asynchronous updates of the TCB output signal in Single-Shot modeValue Description0 The output will go HIGH when the counter starts after synchronization1 The output will go HIGH when an event arrives
Bit 5 ndash CCMPINIT CompareCapture Pin Initial ValueThis bit is used to set the initial output value of the pin when a pin output is usedValue Description0 Initial pin state is LOW1 Initial pin state is HIGH
Bit 4 ndash CCMPEN CompareCapture Output EnableThis bit is used to set the output value of the CompareCapture OutputValue Description0 CompareCapture Output is lsquo0rsquo1 CompareCapture Output has a valid value
Bits 20 ndash CNTMODE[20] Timer ModeWriting these bits selects the Timer modeValue Name Description0x0 INT Periodic Interrupt mode0x1 TIMEOUT Time-out Check mode0x2 CAPT Input Capture on Event mode0x3 FRQ Input Capture Frequency Measurement mode0x4 PW Input Capture Pulse-Width Measurement mode0x5 FRQPW Input Capture Frequency and Pulse-Width Measurement mode0x6 SINGLE Single-Shot mode0x7 PWM8 8-Bit PWM mode
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 243
2153 Event Control
Name EVCTRLOffset 0x04Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 FILTER EDGE CAPTEI
Access RW RW RW Reset 0 0 0
Bit 6 ndash FILTER Input Capture Noise Cancellation FilterWriting this bit to lsquo1rsquo enables the Input Capture Noise Cancellation unit
Bit 4 ndash EDGE Event EdgeThis bit is used to select the event edge The effect of this bit is dependent on the selected Count Mode (CNTMODE)bit field in TCBnCTRLB ldquomdashrdquo means that an event or edge has no effect in this mode
Count Mode EDGE Positive Edge Negative Edge
Periodic Interrupt mode0 mdash mdash
1 mdash mdash
Timeout Check mode0 Start counter Stop counter
1 Stop counter Start counter
Input Capture on Event mode0 Input Capture interrupt mdash
1 mdash Input Capture interrupt
Input Capture FrequencyMeasurement mode
0 Input Capture clear and restartcounter interrupt mdash
1 mdash Input Capture clear and restartcounter interrupt
Input Capture Pulse-WidthMeasurement mode
0 Clear and restart counter Input Capture interrupt
1 Input Capture interrupt Clear and restart counter
Input Capture Frequency and Pulse-Width Measurement mode
0bull On the 1st Positive Clear and restart counterbull On the following Negative Input Capturebull On the 2nd Positive Stop counter interrupt
1bull On the 1st Negative Clear and restart counterbull On the following Positive Input Capturebull On the 2nd Negative Stop counter interrupt
Single-Shot mode0 Start counter mdash
1 mdash Start counter
8-Bit PWM mode0 mdash mdash
1 mdash mdash
Bit 0 ndash CAPTEI Capture Event Input EnableWriting this bit to lsquo1rsquo enables the input capture event
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 244
2154 Interrupt Control
Name INTCTRLOffset 0x05Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CAPT
Access RW Reset 0
Bit 0 ndash CAPT Capture Interrupt EnableWriting this bit to lsquo1rsquo enables interrupt on capture
ATmega32083209TCB - 16-bit TimerCounter Type B
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2155 Interrupt Flags
Name INTFLAGSOffset 0x06Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CAPT
Access RW Reset 0
Bit 0 ndash CAPT Capture Interrupt FlagThis bit is set when a capture interrupt occurs The interrupt conditions are dependent on the Counter Mode(CNTMODE) bit field in the Control B (TCBnCTRLB) registerThis bit is cleared by writing a lsquo1rsquo to it or when the Capture register is read in Capture modeTable 21-6 Interrupt Sources Set Conditions by Counter Mode
Counter Mode Interrupt Set Condition TOPValue CAPT
Periodic Interrupt mode Set when the counter reaches TOP
CCMP CNT == TOPTimeout Check mode Set when the counter reaches TOP
Single-Shot mode Set when the counter reaches TOP
Input Capture FrequencyMeasurement mode
Set on edge when the Capture register isloaded and the counter restarts the flagclears when the capture is read
--
On Event copy CNT toCCMP and restartcounting (CNT ==BOTTOM)
Input Capture on Eventmode
Set when an event occurs and the Captureregister is loaded the flag clears when thecapture is read
On Event copy CNT toCCMP and continuecounting
Input Capture Pulse-WidthMeasurement mode
Set on edge when the Capture register isloaded the previous edge initialized thecount the flag clears when the capture isread
Input Capture Frequencyand Pulse-WidthMeasurement mode
Set on the second edge (positive ornegative) when the counter is stopped theflag clears when the capture is read
8-Bit PWM mode Set when the counter reaches CCML CCML CNT == CCML
ATmega32083209TCB - 16-bit TimerCounter Type B
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2156 Status
Name STATUSOffset 0x07Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 RUN
Access R Reset 0
Bit 0 ndash RUN RunWhen the counter is running this bit is set to lsquo1rsquo When the counter is stopped this bit is cleared to lsquo0rsquoThe bit is read-only and cannot be set by UPDI
ATmega32083209TCB - 16-bit TimerCounter Type B
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2157 Debug Control
Name DBGCTRLOffset 0x08Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DBGRUN
Access RW Reset 0
Bit 0 ndash DBGRUN Debug RunValue Description0 The peripheral is halted in Break Debug mode and ignores events1 The peripheral will continue to run in Break Debug mode when the CPU is halted
ATmega32083209TCB - 16-bit TimerCounter Type B
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2158 Temporary Value
Name TEMPOffset 0x09Reset 0x00Property -
The Temporary register is used by the CPU for single-cycle 16-bit access to the 16-bit registers of this peripheral Itcan be read and written by software Refer to 16-bit access in the AVR CPU chapter There is one commonTemporary register for all the 16-bit registers of this peripheral
Bit 7 6 5 4 3 2 1 0 TEMP[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash TEMP[70] Temporary Value
ATmega32083209TCB - 16-bit TimerCounter Type B
copy 2020 Microchip Technology Inc Preliminary Datasheet DS40002174A-page 249