28 July 20 04 Changes TIM-2->TIM-3A->TIM-3B - Matt War ren 1 ATLAS SCT/Pixel TIM FDR/PRR Physics & Astronomy HEP Electronics Matthew Warren John Lane, Martin Postranecky Changes TIM-2 TIM-3A TIM- 3B ATLAS SCT TIM FDR/PRR 28 June 2004
28 July 2004
Changes TIM-2->TIM-3A->TIM-3B - Matt Warren 1ATLAS SCT/Pixel TIM FDR/PRR
Physics & AstronomyHEP Electronics
Matthew WarrenJohn Lane, Martin Postranecky
Changes TIM-2 TIM-3A TIM-3B
ATLAS SCT TIM FDR/PRR28 June 2004
28 July 2004
Changes TIM-2->TIM-3A->TIM-3B - Matt Warren 2ATLAS SCT/Pixel TIM FDR/PRR
Background
OUT OF
DATE• TIM-2 produced using AMD/
Lattice MACH5 CPLDs.
• These devices now obsolete
• More importantly, the firmware code is obsolete (obscure DSL language).
• Using modern, large FPGAs provides both cost savings as well as flexibility of having all logic reserves in one place.
• Re-writing the code in a better supported language (VHDL) allows for better code maintainability and greater flexibility when choosing devices.
28 July 2004
Changes TIM-2->TIM-3A->TIM-3B - Matt Warren 3ATLAS SCT/Pixel TIM FDR/PRR
TIM-3 Design
• Xilinx IIE FPGA Family chosen– Xilinx used by all of our collaborators.– Spartan much cheaper than Virtex II (at the time).– New 600E part just released (2003), so family unlikely
to go obsolete soon.
• Two FPGAs used– Smaller 200E part used for VME interface– Larger 600E part performs all ‘TIM’ functions
• Clocks now controlled via dedicated fail-over
MUX/PLLs
FPGA related features are discussed further under in
the Firmware talk.
28 July 2004
Changes TIM-2->TIM-3A->TIM-3B - Matt Warren 4ATLAS SCT/Pixel TIM FDR/PRR
PCBs Compared
•10 CPLD’s reduced to 2 FPGA’s (456 pin BGA).
•32kB RAM and 64x128 FIFO moved into FPGA.
•Most DIL’s replaced by SMD (excl. backplane interfaces)
TIM2 TIM3A
28 July 2004
Changes TIM-2->TIM-3A->TIM-3B - Matt Warren 5ATLAS SCT/Pixel TIM FDR/PRR
Changes for TIM-3B
TIM3B is the pre-production version of TIM.
Only minor changes to TIM-3A design:
• TTCrq QPLL connector added and routed to FPGA
• Various front-panel mods for easier debugging/testing in a full crate.– 16 ‘ROD Busy’ LEDs under FPGA control.– JTAG connection available on front panel.– FPGA ‘Load’ micro-switch for special situations.– Better access to debug connector with possibility of a
front-panel mounting.
• Jumper to disable trigger veto logic.
• PCB stiffener bars added.
28 July 2004
Changes TIM-2->TIM-3A->TIM-3B - Matt Warren 6ATLAS SCT/Pixel TIM FDR/PRR
Coming Soon …