Asynchronous fine grained power gated logic

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Asynchronous Fine-grain Power-gated LogicBy

YERNINTI ANIL KUMAR(13331D5701)

Under the esteemed guidance ofDr. M. Satyanarayana, M.Tech, Ph.DASSOCIATE PROFESSOR DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERINGMAHARAJ VIJAYARAM GAJAPATHIRAJ COLLEGE OF ENGINEERINGTopics to be coveredAbstractWhat is Power gating?How the Asynchronous transfer mode works?Operation of Asynchronous Fine-grained Power-gated Logic(AFPL) without(w/o) Partial Charge Reuse(PCR).Operation of AFPL-PCR.Advantages of AFPL-PCR over AFPL w/o PCR.Circuit Simplification techniques.AFPL-PCR implementation of an eight-bit five-stage pipelined KoggeStone adder.References.

AbstractA novel low-power logic family called Asynchronous Fine-grain Power-gated Logic (AFPL) is presented in this seminar.

Each pipeline stage in the AFPL circuit is comprised of efficient charge recovery logic (ECRL) gates and Handshake Controller (HC).

Each ECRL stage implement the logic function of the stage, and a handshake controller, which handles handshaking with the neighboring stages and provides power to the ECRL gates.The partial charge reuse (PCR) in the AFPL circuit utilizes part of the charge on the output nodes of an ECRL gate entering the discharge phase to charge the output nodes of another ECRL gate about to evaluate, reducing the energy dissipation required to complete the evaluation of an ECRL gate.

AFPL-PCR adopts an enhanced C-element, called C-element.

In its handshake controllers such that an ECRL gate in AFPL-PCR can enter the sleep mode early once its output has been received by the downstream pipeline stage.POWER CONTROL LOGIC(ON)Logic implementation networkVDDPower Gating illustrationFig. 1 Illustration of Power gatingPOWER CONTROL LOGIC(OFF)Logic implementation networkVDDPower Gating illustrationFig. 1 Illustration of Power gatingSymbolEquivalent representationValid token (1,0) or (0,1)Empty token (0,0)Logic High 1Logic low 0

Table 1. The symbol representations

Valid Code wordHand shaking Signals in asynchronous modeSenderReceiver

Acknowledgement assertedFig. 2 Asynchronous mode transfer

Empty Code wordSenderReceiver

Acknowledgement assertedHand shaking Signals in asynchronous modeFig. 2 Asynchronous mode transferSenderReceiver

Acknowledgement deassertedHand shaking Signals in asynchronous modeFig. 2 Asynchronous mode transfer

C-ElementCompletion DetectorSingle pipeline stage in AFPL w/o PCRFig. 3 Single pipeline stage of AFPL w/o PCR

Fig. 4 ECRL AND/NAND gateIn the AFPL pipeline, the handshake controller HCi in stage Si performs the following tasks: detecting the validity of the inputs to the ECRL logic gates in stage Sioffering power to the ECRL logic gates in stage Sidetecting whether the outputs of stage Si have been received by the downstream stage Si+2informing the upstream stage Si2 when Si2 can remove its outputs.

Every stage in the AFPL pipeline repeats the operation cycle comprised of the wait, evaluate, hold, and discharge phases.

The forwarding of a valid token causes a pipeline stage to evaluate; the forwarding of an empty token causes a pipeline stage to discharge.AinRiResetVpixx10000hold01011000110holdTable 2. Truth table for C-element

Operation of AFPL w/o PCR Pipeline Stages

Operation of AFPL w/o PCR Pipeline Stages

Operation of AFPL w/o PCR Pipeline Stages

Operation of AFPL w/o PCR Pipeline Stages

Operation of AFPL w/o PCR Pipeline Stages

C*- Element

Completion detectorSingle pipeline stage in AFPL-PCRFig. 5 Pipeline stage of AFPL-PCR There are two main differences between AFPL-PCR and AFPL w/o PCR.

First, AFPL-PCR employs the PCR unit PCRi+1 to control charge reuse between pipeline stages Si and Si+2.

Second, the handshake controller HCi in AFPL-PCR employs an enhanced C-element, which is called C-element, to control the power node Vpi of the associated ECRL gates.

The C-element offers the advantage that an ECRL gate can achieve early discharging if its outputs are no longer required, without waiting for the next empty token to arrive at this stage.AinRiResetVpixx10000hold010110001100Table 3. Truth table of C*- element

Operation of AFPL-PCR Pipeline Stages

Operation of AFPL-PCR Pipeline Stages

Operation of AFPL-PCR Pipeline Stages

Operation of AFPL-PCR Pipeline Stages

Operation of AFPL-PCR Pipeline StagesAdvantages of C*- element and PCRIn AFPL-PCR with C*-element, VDD is cut off from Vpi immediately when Aini arrives, thus most of the charge flowing through the PCRi+1 unit comes from Vpi rather than VDD.

Part of the charge on the output nodes of gate Gi are reused to charge the output nodes of gate Gi+2 to reduce energy dissipation.

The use of the C*-element makes it possible to synchronize the discharging of gate Gi with the evaluating of gate Gi+2, and to have gate Gi enter the sleep mode early to further reduce static power dissipation.Circuit Simplification Hardware cost for implementing the AFPL circuit will be enormous if every ECRL logic gate in the AFPL pipeline needs a dedicated handshake controller.

We can reduce the hardware complexity of AFPL by employing the following two methods of circuit simplification.All ECRL logic gates in the same AFPL pipeline stage can share a common handshake controller. The CD in the handshake controller can be replaced by a simple OR gate if, in the preceding pipeline stage, a particular logic gate has a longer propagation delay than the other logic gates.

Figure 6 shows the example of circuit simplification technique for the AFPL pipeline.

Fig. 6 Circuit simplification technique for AFPL-PCR pipeline stages. AFPL-PCR implementation of an eight-bit five-stage pipelined KoggeStone adderFig. 7 shows the Virtuoso schematic diagram of the AFPL-PCR implementation of an eight-bit five-stage pipelined KoggeStone adder.

In this implementation, all ECRL gates in the same pipeline stage share a common handshake controller to mitigate the hardware overhead.

By this the handshake controllers and PCR units account for 14% of the total transistor count.

Fig. 7 Virtuoso schematic diagram of the AFPL-PCR implementation of an eight-bit five-stage pipelined KoggeStone adderReferencesMeng-Chou Chang and Wei-Hsiang Chang Asynchronous Fine-Grain Power-Gated Logic IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013 Z. Chen, M. Johnson, L. Wei, and K. Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks, in Proc. Int. Symp. Low Power Electron. Design, 1998, pp. 239244.S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, Scaling of stack effect and its application for leakage reduction, in Proc. Int. Symp. Low Power Electron. Design, 2001, pp. 195200.Y. Oowaki, M. Noguchi, S. Takagi, D. Takashima, M. Ono, Y. Matsunaga, K. Sunouchi, H. Kawaguchiya, S. Matsuda, M. Kamoshida, T. Fuse, S. Watanabe, A. Toriumi, S. Manabe, and A. Hojo, A sub-0.1 m circuit design with substrate-over-biasing, in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1998, pp. 8889.S. Mutob, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, 1 V power supply high-speed digital circuit technology with multithreshold-voltage CMOS, IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847854, Aug. 1995.T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, Boosted gate MOS (BGMOS): Device/circuit cooperation scheme to achieve leakage-free giga-scale integration, in Proc. IEEE Custom Integr. Circuits Conf., 2000, pp. 409412.K.-S. Min and T. Sakurai, Zigzag super cut-off CMOS (ZSCCMOS)scheme with self-saturated virtual power lines for subthreshold-leakage suppressed sub-1-v-vdd LSIs, in Proc. Eur. Solid-State Circuits Conf., 2002, pp. 679682.

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