ASYNCHRONOUS DESIGN IN VLSI · Web viewTo design in a circuit in asynchronous logic is not easy due to various hazards and races it had, and it is hard to develop automation for entire

ASYNCHRONOUS DESIGN IN VLSI

TITAC-2 32 BIT ASYNCHRONOUS MICROPROSESSOR

EE552 (Spring 2003)EXTRA CREDIT PROJECT

Prof. JAMES ELLISON

Submitted by:Name: Dhruva Kumar Singh

Student I.D.: 885-20-8498Email: [email protected] No: 323-737-4573

I alone prepared and wrote this project. I received no help from anyone one

else. This material is not copied or paraphrased from any other source except

where specifically indicated. I grant my permission for this project to be placed

on the course homepage during future semesters. I understand that I could

receive an F for the course retroactively, even after graduation, if this work is

later found to be plagiarized.

My soul purpose of this project is to provide reader a greater understanding

on the topic. I have listed all the papers that I referred in the Bibliography section

of this paper.

INDEX

1. ABSTRACT

2. INTRODUCTION

3. METHODOLIGIESa. Self timed circuits

1. Two phase protocol

2. Four face protocol

b. Delay elements

c. Basic blocks

1. Muller C – element

2. Self timed combinational element

d. Micropipelines

1. Basic elements of Micropipeline

a. Switch

b. Latch

c. Register

2. Classification of Micropipeline

a. Without processing

b. With processing

4. BUFFERING ELEMENTS

5. BENEFITS AND DRAWBACKS

6. CONCLUSION

7. BIBLIOGRAPHY

ABSTRACT

From last few decades we are studying asynchronous design but due to

some difficulties it faces, designer prefers synchronous design over

asynchronous design in commercial purpose. The promise of no clock skew, the

higher degree of modularity, the low power consumption have attracted modern

VLSI designer towards asynchronous design.

To design in a circuit in asynchronous logic is not easy due to various

hazards and races it had, and it is hard to develop automation for entire design

process. On the contrary in synchronous design today we have almost

automated design procedures.

In this paper, I will discuss some of the design approaches for asynchronous

design which will be helpful in designing an asynchronous VLSI design.

INTRODUCTION

In today’s world as the size of design are going smaller day by day ,so the

power consumption in them is increasing opposite to it. Today a microprocessor

dissipate about 70 W which is very high and to cool that chip we need fan .But

designer are trying to increase the speed day by day so this power dissipation

will increase more. This power reduces the battery life which is key feature in any

VLSI design. Gates dissipate energy as they switches, and we think it should be

as it is performing some operation but in real synchronous design there are many

gates which are just being connected to clocks. This lead to excessive power

consumption, that is not negligible even in low power devices such as CMOS

transistors.

Second major problem a synchronous design faces a problem of clock skew.

In any design we want clock to reach at all the places at same time or with some

reasonable delays. but as the circuits are going smaller and the length of

interconnect is going longer therefore to achieve this task is becoming

harder .this difficulty restricts both clock speed and computational power, as most

of the clock period is spend on clock distribution.

The asynchronous design removed both the problem because it eliminates

the clock. And above all the power dissipation is from that part of chip which is

doing any computational problem. The Philips group designed an asynchronous

digital compact cassette error detector which consumes 80% less power than the

similar synchronous version. The AMULET group at Manchester University

successfully implemented an asynchronous version of ARM processor .the

asynchronous version achieved a power dissipation comparable to fourth

generation ARM, around 150 mW, in a similar technology.

In synchronous logic we design our circuit according to worst case delay, this

lead to increase of size in some MOS transistors which never work during

computation and they consume lot of power due to clock, whereas in

asynchronous design we take average case delay due to this sizing in optimum

and the power consumption is less.

In synchronous circuit we use to enhance our performance by developing

new technology. In asynchronous design that will not be the case as we will

increase our performance just by modifying our critical path instead of whole

circuit in new technology and this will lead to increase in average performance of

asynchronous circuit as performance of circuit depend mainly on critical path.

Now I will discuss some of the methodologies used in asynchronous circuits.

METHODOLIGIES

There are many methodologies for analyzing and designing asynchronous

circuits .Some of them are self timed signaling(hand shaking) ,underlying delay

models ,mode of operations and formalism of design circuits.

SELF TIMED CIRCUITS

Contrary to synchronous circuits, asynchronous or self timed circuits do not

have any global clock that governs the operation of whole circuits. Self timed

elements synchronize themselves by hand shake signals. The absence of global

clock makes the behavior to be non deterministic and permits the implementation

of highly concurrent systems. Self –timed signaling must take into account the

design constraints of the systems. Such constraints rule the behavior of both self

timed modules (functional constraint) and on the set on inputs signal, in which

the circuit has to operate (domain constraints). The general self timed signals

rules, also known as weak conditions are the following:

1. Some inputs become defined before some output becomes

defined.

2. All inputs become defined before all outputs become defined.

3. All outputs become defined before some inputs become undefined.

4. Some inputs become undefined before some outputs become

undefined.

5. All inputs become undefined before all output become undefined.

6. All outputs become undefined before some inputs become defined.

The rules 1,2,4,5 are functional constraints and 3, 6 are domain constraint.

There are two protocols in asynchronous circuits:

1. Two Phase protocol : In this first sender send a request

signal ,then the receiver send a acknowledgement signal, therefore it is

known as two phase protocol .both request and acknowledgment signal

are implemented by voltages at different levels at different wires .in this

protocol we don’t make any distinction between direction of voltage

signals . Both rising and falling transition denote a single transition event.

This protocol follows the weak rule 1, 2, 3. It is very fast and energy saving

but requires an extra logic to store the previous state to know whether

transition has occurred on a wire. This protocol is generally used in inter

chip communication.

Two Phase signaling protocol

In two phases signaling encoding is as follows:

In each pair of wire one wire represent 1 and another represent 0.so

transition on 0 wire shows the transfer of 0 and the transition on 1 wire show

transfer of 1.both wire cannot transfer at same time.

a. First phase: transfer of data.

b. Second phase: transfer of acknowledgement signal by the receiver.

2. Four Phase protocol: In this protocol we first send a request to

receiver then he send us a acknowledgement ,then we send second

request to receiver for which he send us another acknowledgement ,

therefore it is known as four phase protocol. The request and

acknowledgment are implemented by voltage transition on different wires.

In this protocol at the end of every four phase the voltage return to starting

value and the initial value is zero therefore it is also known as return to

zero signaling. This implementation is expensive under the speed and

power consumption point of view but is easy to implement and require less

hardware. It is used in intra chip communication.

Four Phase signaling protocol

In four phases signaling we may use different type of encoding .the most

common encoding is as follows:

First we define four states for each pair of wires. These states are as

follows:

1. 00 =reset

2. 01 =valid 1

3. 10 =valid 0

4. 11=unused state

a. First phase :in this phase every pair of wire leaves the reset value for

valid 0 or valid 1.now the receiver detect the arrival of new set of data. This

detection leads to replacement of request signal.

b. Second phase: receiver send an acknowledgment signal to sender that

data is consumed

c. Third phase: now all the wires r reset to reset state

d. Fourth phase: now the acknowledgement is reset.

DELAY MODELS

For every circuits we design there is a delay model, which tells us about

the delay in the circuits and the range of delay which the signal will face while

propagating. These delay models are required to analyze the circuits in every

possible working condition, like what will be the delay when there is no hazard

or what will be the delay when circuit will face a hazard. The interconnect

wires and gates imposes maximum delay in the circuit. There are two types of

delay models:

1 pure delay: this delay only shift the time of voltage signal propagating

through them.

2 inertial delays: sometime in a circuit due to active components like

capacitance and inductance the voltage level decreases of even some signal

in a particular bandwidth is filtered. The delay model which captures this

effect is known as inertial delay model.

Based on above delays models the delays models are further classified in

four types:

1 Zero delay: in this model the value of delay is zero

2 Fixed delay: in this model the value of delay is constant.

3 Bounded delay: in this model the value of delay is fixed under certain

boundary.

4 Unbounded delay: in this model we cannot predict the value of delay

except it will never be infinite.

Generally zero delay model is used for interconnect wire and unbounded

delay is used for gates in the circuit.

BASIC BLOCKS

In this section I will discuss some of the fundamental blocks which are

generally used for designing any asynchronous systems.

MULLER C-ELEMENT

The Muller C – element implement the Boolean function c=c(a+b)+ab, where

c is the output and a, b are input to the circuits. This functions implies if inputs

are different it retain the previous value and if input are same then output will

have same input value. The C –element is associative in nature, so we can

cascade C-elements in a proper way.

Below I am showing some of the implementation of C-elements.

NMOS IMPLEMENTATION SUTHERLAND’S IMPLEMENTATION

MARTIN’S IMPLEMENTATION VAN BERKEL’S IMPLEMENTATION

SELF –TIMED COMBINATINAL ELEMENTS

In this we generally use the ordinary combinational circuits. If we add

delay element to it turns in to a self timed combinational element. For two

phase protocol the delay should be symmetrical and for phase protocol the

delay should be asymmetrical.

SELF TIMED COMBINATIONAL ELEMENT

MICROPIPELINES

The concept of Micropipeline was introduced by Sutherland in his Turing

award lecture. Micropipelines are asynchronous circuits which gain popularity in

today VLSI design. Many VLSI design are fabricated are fabricated and working

successfully. The AMULET microprocessor is one example of it. The

micropipeline provides us the tool for implementing event driven clastic pipelines

(Asynchronous FIFO) and general pipelines like decoders. The clastic pipeline

differs from pipeline used in synchronous circuits by two ways:

1. They are clock free and the transfer of data depends on local

events only, whereas in synchronous design the transfer of data depends

on clocking signal.

2. In synchronous pipeline rate of input and output should be same

otherwise the pipeline will have error but in clastic pipeline the rate of input

and output may differ depending on local buffering elements.

BASIC ELEMENTS OF MICROPIPELINE

The basic elements for any pipeline circuits are:

1. Switch: it is the basic element of any latch or register we used in

our design. Below one of the implementation of switch is shown.

Sutherland’s CMOS switch: Symbol and Implementation

This switch is governed by capture signal c instead of clock signal. The

working of this switch is as follows:

1. C=0 output (o) is compliment of b

2. C=1 output (o) is compliment of a

2. Latch: it is defined for transferring the input to the output for

particular combination of controls signals. The implementation of latch is

shown below.

A. SLOW LATCH B.FAST LATCH

The control signals for above latch are capture signal (c) and pass signal (p).it

works as follows:

1. When c =1 and p= 0 or c=0 and p=1 the latch act as opaque. This

means that there is feedback path between output and input so the input

is not transferred as output.

2. When c=1 and p=1 or c=0 and p=0 the latch act as transparent .this

mean the output follows the input.

3. Registers: It is made up of latches. Its implementation is shown below.

a. SYMBOL b. IMPLEMENTATION

the register have two input signals which are capture (c) and pass signal (p)

and it has two outputs Pd and Cd which are the delayed capture and pass

signal.

CLASSIFICATION OF MICROPIPELINE

The Micropipeline circuits are classified into two categories:

1. WITHOUT PROCESSING: This circuit is equivalent to FIFO i.e. First In

First Out. This circuit comprises of two parts:

a. Registers: Many registers are cascaded to form a data path from input to

output.

b. Muller C-element: it is used to give controlling signal to the registers.

Each register is controlled by two signals:

a. capture signal from the C element of the same stage of the

pipeline

b. Pass signal from the C element of next stage of the pipeline.

In Micropipeline each stage gets a new value of data and passes its

present value of data to next stage.

WITHOUT PROCESSING MICROPIPELINEAfter applying reset signal if all the pass signal and capture signals are “0”

then input data is passed to the output and the FIFO is said to empty i.e. all the

register are in transparent mode. If both capture signal and pass signal are in

opposite logic levels the Micropipeline act as opaque circuit so it is called full.

In Micropipeline the sender always wait for Aim before sending new data in

pipeline through Rin ,as it tell that previous data is passed to next stage.

Similarly at the output side the receiver should wait for Aout signal to occurred

first before taking new data from pipeline.

2. WITH PROCESSING: The basic diagram of this pipeline is same as

without processing except we have combinational logic circuit CL between two

stages.

WITH PROCESSING MICROPIPELINE

When capture signal is applied then data is passed in to registers. After that if

we apply pass signal the register act as transparent so data is passes from input

to output. In this pipelining we delay the capture signal and pass signal to

generate capture done and pass done signal so that combinational logic can

perform it work to give right value of data .the value of delay must be greater than

the processing time of combinational logic.

BUFFERING ELEMENTS

We require buffering in Micropipeline and register so that we can get delay in

them .for buffering we use an inverter. The possible implementation is shown

below.

GENERLIZED IMPLEMENTATION NMOS IMPLEMENTATION

BENEFITS AND DRAWBACKS

There are many benefits of using asynchronous design such as:

1. No clock: In asynchronous design since there is no clock so we

don’t have to worry about clock skew and delays in clock. Clock also

dissipates lot of energy about 40% in the design. By eliminating clock we

are saving area of chip and power also. We can use that area and power

for improving the design.

2. Low power : As there is no clock in asynchronous design so power

dissipation due to clock moving in interconnect and due to clock applying

to gates of transistor which are not doing any computational is saved.

3. Adaptability: Since synchronous design is based mainly on clock

and there is relation between clock and environment we have to take care

of it otherwise our circuit will not work properly in different environment

conditions. As in asynchronous design there is no clock so we don’t have

to take care of it and it will work properly in any environment.

4. Average delay: In synchronous design we use worst case delay

and to calculate worst case delay take lot of time and sizing of the circuit

depend on worst case delay ,which also result in high power dissipation.

On the contrary in asynchronous design we use average case delay of the

critical path only so we have optimum sizing which save lot of power.

5. Less electromagnetic emission: In synchronous design we

always feed the data at the edge of clock which result is an

electromagnetic spice and its harmonic .Due to this spike all the capacitor

and inductor in the circuit get affected .But in asynchronous design as

work is evenly distributed so the electromagnetic emission is less.

6. Speed: In any design speed is the one of the major factor .in

asynchronous design as we take average case delay and work is evenly

distributed so the speed of asynchronous design is more than

synchronous design having same power consumption.

In spite of having all these advantages asynchronous design have drawbacks

also .some of them are:

1 Tools: In synchronous design we have CAD tools which make the

designing very easy .on the other hand we don’t have any tools in asynchronous

design.

2 Hard to design: The asynchronous circuit is hard to design as there is no

software which may help the designer. The requirement of asynchronous design

that it will work in fundamental or in burst mode make it hard to design.

3 Testing: Many designer think how will they test their design .in

synchronous design we make clocking speed slow or fast and test the behavior

of circuit. But in asynchronous design as there is no clock we cannot test the

design by this approach.

4 No proper education: Today in every part of world the education is mainly

based on synchronous design with little knowledge of asynchronous design. If

any company wants to make asynchronous design first of all it will not get the

engineers and second it will not invest their money for training them.

CONCLUSION

In this paper I had only touched some of the basic approaches in

asynchronous design to prepare reader for further reading. Now a day’s the

several design approaches are developed in asynchronous design in the field of

Micropipeline and other fields. In this paper I left some key topics like testing of

asynchronous design. The reader can get these topics on various papers

available in IEEE journals and on the internet. After reading this paper a question

arises “will we ever see a fully asynchronous design?” The answer to this

question is “YES” but not on big scale. The reason for this is as today all the

design are based on synchronous design and companies had already invested

billions of dollars to develop tools for those design. Above all the designs are

working properly, so now the companies will not spend millions of dollars for

completely new approach to ward a design. VLSI design is facing the same

situation as internet faced in few decades ago when both cable TV companies

and telecommunication companies faced for providing internet. The solution was

that nowadays big companies like AT&T provide both as the infrastructure is

same for both cable and communication. So we can see a chip in future which

will be hybrid of both synchronous and asynchronous design approaches. The

hybrid design will be faster and will dissipate less energy from now day’s

designs. Now days many cellular phone companies are using this approach so

that they can provide better phones with better battery life. To achieve this task is

a challenge for engineers, so hardware engineers have to accept this challenge

to provide better service.

BILBLIOGRAPHY

1. Scott McPeak , “ Asynchronous Logic ,UC Berkley ,CS 250,Fall

1999,U.S.A”

2. Mike Lewis , Linda Brackenbury , “CADRE : A Low – Power, Low –

EMI DSP Architecture for Digital Mobile Phones , AMULET Group,

University of Manchester, United Kingdom”

3. Steve Furber , “Computing without Clocks: Micropipelining the

ARM Processor , University of Manchester, United Kingdom ”

4. Gianluca Cornetta ,Jordi Cortadella, “ Asynchronous Pipelined

Datapaths Design Techniques .A Survey , Universitat Politecnica

de Catalunya,Spain”

5. Maitham Shams, Jo C. Edergen, Mohamed I. Elmasry, “

Asynchronous Circuits , University of Waterloo, Canada and Sun

Microsystems Laboratories , U.S.A”