Asymmetric Crypto Asymmetric Crypto - - Processor Processor Core Core Laboratory of Reliable Computing Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan Chyr-Pyng Su, Yung-Chang Lin, Chih- Wea Wang, Chih-Tsun Huang and Cheng-Wen Wu
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Asymmetric Crypto-Processor Core - UCLAcadlab.cs.ucla.edu/icsoc/protected-dir/june_pdf_presentations/cheng... · RSA Asymmetric Algorithm • The relation between ciphertext and a
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A built-in self-diagnosis (BISD) to test 8 memory coresFull-scan: 6 scan chains, each with 123 scan registersA builtA built--in selfin self--diagnosis (BISD) to test 8 memory coresdiagnosis (BISD) to test 8 memory coresFullFull--scan: 6 scan chains, each with 123 scan registersscan: 6 scan chains, each with 123 scan registers
Chih-Tsun Huang Jun 23 2001 11
ComparisonComparisonComparison
13.1k
4.5k
77k
76k
74k
Gate Count
79k
18.6k
512k
174.8k
286k
NB
No2.3100k100M0.6μμμμm0.51M512Su
79k
10.5k
289k
164k
Baud
Rate
Yes6100M0.35μμμμm0.81M512Our design (16-bit)
Yes2.37125M0.6μμμμm6.5M512Hsieh (8-bit)
No6.7300M0.6μμμμm0.53M512Hong
No3.9125M0.6μμμμm0.39M512Yang
Scalable
Key SizeααααClockTech.#. of clocks
/512 bitsKey Size
NB is normalized baud rate.αααα is NB / gate count.
Chih-Tsun Huang Jun 23 2001 12
SummarySummarySummary• An RSA cryptography engine with small area