Assembly Language for x86 Assembly Language for x86 Processors Processors 7th Edition 7th Edition Chapter 12: Floating-Point Processing and Instruction Encoding (c) Pearson Education, 2015. All rights reserved. You may modify and copy this slide show for your personal use, or for use in the classroom, as long as this copyright statement, the author's name, and the title are not changed. Slide show prepared by the author Revised by Zuoliu Ding at Fullerton College, 09/2014 Kip R. Irvine
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Assembly Language for x86 Processors Assembly Language for x86 Processors 7th Edition7th Edition
Chapter 12: Floating-Point Processing and Instruction Encoding
(c) Pearson Education, 2015. All rights reserved. You may modify and copy this slide show for your personal use, or for use in the classroom, as long as this copyright statement, the author's name, and the title are not changed.
Slide show prepared by the author
Revised by Zuoliu Ding at Fullerton College, 09/2014
Kip R. Irvine
Irvine, Kip R. Assembly Language for x86 Processors 7/e, 2015. 2
Chapter OverviewChapter Overview
• Floating-Point Binary Representation• Floating-Point Unit• x86 Instruction Encoding
Irvine, Kip R. Assembly Language for x86 Processors 7/e, 2015. 3
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Converting Single-Precision to DecimalConverting Single-Precision to Decimal
1. If the MSB is 1, the number is negative; otherwise, it is positive.2. The next 8 bits represent the exponent. Subtract binary
01111111 (decimal 127), producing the unbiased exponent. Convert the unbiased exponent to decimal.
3. The next 23 bits represent the significand. Notate a “1.”, followed by the significand bits. Trailing zeros can be ignored. Create a floating-point binary number, using the significand, the sign determined in step 1, and the exponent calculated in step 2.
4. Unnormalize the binary number produced in step 3. (Shift the binary point the number of places equal to the value of the exponent. Shift right if the exponent is positive, or left if the exponent is negative.)
5. From left to right, use weighted positional notation to form the decimal sum of the powers of 2 represented by the floating-point binary number.
Irvine, Kip R. Assembly Language for x86 Processors 7/e, 2015. 18
ExampleExample
Convert 0 10000010 0101100000000000000000 to Decimal
1. The number is positive.
2. The unbiased exponent is binary 00000011, or decimal 3.
3. Combining the sign, exponent, and significand, the binary number is +1.01011 X 23.
4. The unnormalized binary number is +1010.11.
5. The decimal value is +10 3/4, or +10.75.
Irvine, Kip R. Assembly Language for x86 Processors 7/e, 2015. 19
What's NextWhat's Next
• Floating-Point Binary Representation• Floating-Point Unit• x86 Instruction Encoding
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 21
Infix Postfix
a+b ab+
(a+b)/c ab+c/
(a+b)*(c-d) ab+cd-*
5*6-4 5 6 * 4 -
5 ST(0)
5 6 ST(1) ST(0)
5 6 * ST(0)
5 6 * 4 ST(1) ST(0)
5 6 * 4 - ST(0)
5
• Stack status in evaluating 5 6 * 4 - :
5
6
30
30
4
26
Irvine, Kip R. Assembly Language for x86 Processors 7/e, 2015. 22
FPU Register StackFPU Register Stack• Eight individually addressable 80-bit data registers named R0
through R7 • Three-bit field named TOP in the FPU status word identifies
the register number that is currently the top of stack.
• Reference: SIMPLY FPU at MASM Forum
FPU Register, AdvancedFPU Register, Advanced
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• LOAD a value: turn the barrel clockwise by one notch and load the value in the top compartment. The first value loaded immediately after the initialized FPU goes into R7. (Barrel Compartment)
• Values only can be loaded to or popped from the TOP compartment
Rule #1: An register compartment MUST be free (empty) in order to load a value into it.Rule #2: The programmer must keep track of the relative location of the existing register values while other values may be loaded to or popped from the TOP register.
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• Opcode register: stores opcode of last noncontrol instruction executed
• Control register: controls precision and rounding method for calculations
• Status register: top-of-stack pointer, condition codes, exception warnings
• Tag register: indicates content type of each register in the register stack
• Last instruction pointer register: pointer to last non-control executed instruction
• Last data (operand) pointer register: points to data operand used by last executed instruction
Tag Word (0FFFFh at FINIT ), AdvancedTag Word (0FFFFh at FINIT ), Advanced
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• Each pair of bits means that the FPU register : 00 = contains a valid non-zero value 01 = contains a value equal to 0 10 = contains a special value (NAN, infinity, or denormal) 11 = is empty
• If a valid non-zero value is first loaded, it goes into BC7:0011111111111111b (3FFFh)
• If a second value zero (0) is then loaded, goes into BC6:0001111111111111b (1FFFh)
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RoundingRounding• FPU attempts to round an infinitely accurate result
from a floating-point calculation• may be impossible because of storage limitations
• Example• suppose 3 fractional bits can be stored, and a
calculated value equals +1.0111.
• rounding up by adding .0001 produces 1.100
• rounding down by subtracting .0001 produces 1.011
Round Method Real Rounded
To nearest even 1.0111 1.100
Down to negative infinity 1.0111 1.011
Up to positive infinity 1.0111 1.100
Toward zero 1.0111 1.011
Real Rounded
-1.0111 -1.100
-1.0111 -1.100
-1.0111 -1.011
-1.0111 -1.011
Control Word (037Fh at FINIT), AdvancedControl Word (037Fh at FINIT), Advanced
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• The RC field (bits 11 and 10) or Rounding Control: 00 = Round to nearest, or to even if equidistant (default) 01 = Round down (toward -infinity) 10 = Round up (toward +infinity) 11 = Truncate (toward 0)
• Bits 5-0 are the interrupt masks:PM (bit 5) or Precision Mask UM (bit 4) or Underflow Mask OM (bit 3) or Overflow Mask ZM (bit 2) or Zero divide Mask DM (bit 1) or Denormalized operand Mask IM (bit 0) or Invalid operation Mask
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• Six types of exception conditions• Invalid operation #I
• Divide by zero #Z
• Denormalized operand #D
• Numeric overflow #O
• Numeric underflow #U
• Inexact precision #P
• Each has a corresponding mask bit• if set when an exception occurs, the exception is handled
automatically by FPU• if clear when an exception occurs, a software exception
handler is invoked
Status Word (0000h at FINIT), AdvancedStatus Word (0000h at FINIT), Advanced
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• TOP (bits 13-11): FPU keeps track of which BC at the TOP
• IR (bit 7): Interrupt Request, set (1) while an exception handled and reset (0) when the exception handling completed
• SF (bit6): Stack Fault exception is set to either load a value into a register which is not free (then C1=1) or pop a value from a register which is free (then C1=0). (Such SF also an invalid operation I =1)
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FPU Code Example 2FPU Code Example 2• Sum of an ArrayARRAY_SIZE = 20
.data
sngArray REAL8 ARRAY_SIZE DUP(1.5)
.code
finit
mov esi,0 ; array index
fldz ; push 0.0 on stack
mov ecx,ARRAY_SIZE
L1:
fld sngArray[esi]
fadd
add esi,TYPE REAL8
loop L1
Q: How many FPU Registers are used?
; add memory into ST(0); add ST(0), ST(1), pop
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Mixed-Mode ArithmeticMixed-Mode Arithmetic
• Combining integers and reals. • Integer arithmetic instructions such as ADD and MUL cannot
handle reals• FPU has instructions that promote integers to reals and load
the values onto the floating point stack.• Example: Z = N + X.dataN SDWORD 20X REAL8 3.5Z REAL8 ?.codefild N ; load integer into ST(0)fwait ; wait for exceptionsfadd X ; add mem to ST(0)fstp Z ; store ST(0) to mem
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Masking and Unmasking ExceptionsMasking and Unmasking Exceptions
• Exceptions are masked by default• Divide by zero just generates infinity, without halting the
program
• If you unmask an exception• processor executes an appropriate exception handler• Unmask the divide by zero exception by clearing bit 2:
.data
ctrlWord WORD ?
.code
fstcw ctrlWord ; get the control word
and ctrlWord,1111111111111011b ; unmask divide by zero
fldcw ctrlWord ; load it back into FPU
Exception Example: Divide by ZeroException Example: Divide by Zero
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 52
.datactrlWord WORD ?val1 DWORD 1val2 REAL8 0.0
.code fstcw ctrlWord ; get control word and ctrlWord,1111111111111011b ; unmask Divide by 0 fldcw ctrlWord ; load it back into FPU
fild val1 fdiv val2 ; divide by zero,
; if masked, ST0 = 1#INF, no exception fst val2 ; When this comes,
; exception handler is invoked
fstcw ctrlWord ; get control word or ctrlWord,100b ; mask Divide by 0 fldcw ctrlWord ; load it back into FPU
Look into All FPU Internals? AdvancedLook into All FPU Internals? Advanced
Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 53
FPU_ENVIRON STRUCTcontrolWord WORD ?ALIGN DWORDstatusWord WORD ?ALIGN DWORDtagWord WORD ?ALIGN DWORDinstrPointerOffset DWORD ?instrPointerSelector DWORD ?operandPointerOffset DWORD ?operandPointerSelector WORD ?WORD ? ; not used