Assembly Language

BASIC STRUCTURE OF COMPUTER

HARDWARE AND SOFTWARE

INTRODUCTION

A digital computer is a fast electronic calculating machine that accepts digitized input information,

processes it according to a list of internally stored

instructions, and produces the resulting output

information.

The list of instructions is called a computer program, and the internal storage is called computer memory.

Types of Computers

1. Personal Computers. This is the most common

computer which has found wide use in homes,

schools, and business offices.

2. Workstations. Although still of desktop

dimensions, these machines have a computational

power which is significantly higher than that of

personal computers. Workstations are often used

in engineering applications, especially for

interactive design work (CAD/CAM).

Basic Structure of Computer Hardware and Software 1

3. Mainframes. A large and powerful computer

used for business data processing in medium to

large corporations that require much more

computing and storage capacity than

workstations can handle.

4. Supercomputers. These are used for large-scale

numerical calculations found in applications such

as weather forecasting and aircraft design and

simulation. In mainframes and supercomputers,

the main functional units may comprise a number

of separate and often large parts.

In its simplest form, a computer consists of five functionally independent main parts: input, memory,

arithmetic and logic, output, and control units.

Arithmetic

and

Logic

Control

Processor

Input

Output

I/O

Memory


BASIC FUNCTIONAL UNITS OF A COMPUTER

The Input Unit accepts coded information from human operators or from other computers.

Examples:

keyboard, joystick, mouse, trackball,

scanner, bar code readers

Memory Unit

1. Primary Storage or Main Memory. This is

where programs are stored during their execution.

The MM is a fast memory capable of operating at

electronic speeds.

The information in MM is often processed in

groups of fixed size called words. The number of

bits in a word is the word length of the computer.

Typical word lengths range from 16 to 64 bits.

The MM is organized so that the contents of one

word, containing n bits, can be stored or retrieved

in one basic operation.

Since programs must reside in MM during

execution, MM is often referred to as the

bottleneck in most computer operations.


To provide easy access to any word in MM, a

distinct address is associated with each word

location. Addresses are numbers that identify

successive locations.

MM is also known as random-access memory

(RAM). RAM is memory in which any location

can be reached in a short, fixed amount of time.

The time required to access one word is the

memory access time. For RAMs, this time is

fixed, independent of the location of the word

being accesses. It typically ranges from 10 to

100 nanoseconds for most modern computers.

.

.

.

0

1

2

4,194,302

4,194,303

Address of 1st

Memory Location

Memory

Location


2. Secondary Storage. This is used when large

amounts of data have to be stored, particularly if

some of the data need not be accessed very

frequently.

Examples: magnetic disks, drums, tapes

Arithmetic and Logic Unit (ALU). This is where the execution of most operations takes place. It contains a

number of high-speed storage elements called

registers.

used for temporary storage of frequently

used operands.

Each register can store one word of data.

access times are 5 to 10 times faster than

memory access times.

Control Unit (CU). This is the nerve center of a computer. It sends control signals to other units and

senses their state.

The ALU together with CU is the Central Processing

Unit (CPU) of a computer.


The control and arithmetic and logic units are usually

many times faster than other devices connected to a

computer system. This enables a single processor to

control a number of external devices such as video

terminals, magnetic tape and disk memories, sensors,

displays, and mechanical controllers. This is possible

because the vast difference in speed enables the fast

processor to organize and control the activity of many

slower devices

Output Unit. It sends processed results to the outside world.

Examples: CRT/monitor, printers, plotters,

modems

The operation of a computer can be summarized as follows:

1. The computer accepts information in the form of

programs and data through an input unit and

stores it in memory.

2. Information stored in the memory is fetched,

under program control, into an arithmetic and

logic unit, where it is processed.

3. Processed information leaves the computer

through an output unit.

4. All activities inside the machine are directed by

the control unit.


BASIC CONCEPTS OF COMPUTER ARCHITECTURE

Computer Architecture is the design of computers, including their instruction sets, hardware components,

and system organization.

Most computers follow the Von Neumann Architecture.

also known as the Stored Program

Architecture or the Fetch-Decode-

Execute Architecture.

A Von Neumann architecture simply means that programs (together with data) are stored in main

memory during execution.

Not all computers follow the Von Neumann architecture. Some examples are processor array

architecture, multiprocessor architecture, dataflow

architecture, and neural network architecture.


ASSEMBLY LANGUAGE

Types of Programming Language

1. Machine Language. The natural or primitive

language that the computer actually understands.

This programming language consists of 0s and 1s which makes programming very difficult.

Sample machine language program to add 5 and

3 (using the Intel microprocessor instruction set):

10111000

00000101

00000000

10111011

00000011

00000000

00010001

11011000


2. Assembly Language

A programming language that uses

abbreviations or mnemonics in place of binary patterns in order to make the task of

programming easier. Mnemonics are designed to

be easy to remember and are a significant

improvement over binary digits.

An assembly language program has to be

converted to machine language before a computer

can execute it. An assembler is a special

program that translates assembly language

mnemonics into machine language.

Sample assembly language program to add 5 and

3 (using the Intel microprocessor instruction set):

MOV AX, 05

MOV BX, 03

ADC AX, BX

NOTE: Both machine and assembly languages

are low-level programming languages.


3. High-Level Language

A programming language that uses English-like

commands or instructions. High-level languages

are the easiest to use and contains many

complicated or advanced instructions.

A high-level language has to be converted to

machine language before a computer can execute

it. A compiler is a special program that translates

high-level language instructions into machine

language.

Examples of High-level Languages:

1. FORTRAN (FORmula TRANslation)

2. COBOL (COmmon Business-Oriented

Language)

3. BASIC (Beginners All-purpose Symbolic Instruction Code)

4. Pascal

Sample BASIC program to add 5 and 3:

LET A = 5

LET B = 3

LET C = A + B


Advantages of using high-level languages over low-level languages:

1. Easy to Learn. Low-level languages are

more cryptic than high-level language.

2. Predefined Functions. Most high-level

languages provide many pre-defined

functions and subroutines, thereby

simplifying programming tasks.

3. Portability. Low-level languages are

specific towards a certain processor. The

instruction set of the Intel processors (IBM

PCs and compatibles) is very much different from the instruction set of the

Motorola processors (Apple Macintosh).


Advantages of using low-level languages over high-level languages:

1. Compact Code. Programs are executed in

their machine language format. Programs

written in a high-level language should still

be compiled and translated to machine

language. Most compilers are not optimized

to generate compact code.

2. Speed. This is directly related to compact

code. The shorter the code, the shorter the

execution time of the program.

3. Flexible. Low-level language does not

constrain the programmer to follow a certain

programming convention (i.e. modularity)

nor a rigid coding constraint (i.e. the called

routine should be placed before the calling

routine).

Application programs are now more and more complex and test the high-level language to its limit.

High-level programmers now use assembly language-

based subroutines to augment the capabilities of high-

level languages.


BASIC OPERATIONAL CONCEPTS

Example of a typical assembly language instruction:

ADD R0, LOCA

Add the operand at memory

location LOCA to the operand in a

register in the processor, R0 and

place the result into register R0.

The given instruction requires the performance of

several steps:

1. The instruction must be transferred or

fetched from the MM into the CPU.

2. The operand at LOCA must be fetched and

added to the contents of R0.

3. The resultant sum is stored in register R0.


In order to fetch/read an instruction or data from main memory:

1. The CPU first sends the address of the memory

location to be read.

2. The CPU then issues or sends the read signal to

the memory.

3. The word is then read out of memory and is

loaded into a CPU internal register.

In order to store/write data into main memory:

1. The CPU first sends the address of the memory

location to be written.

2. The CPU then sends the write signal together

with the data or word to be written to memory.


Connections between the processor and the main memory:

The PC (Program Counter) contains the memory

address of the instruction to be executed. During

execution, the contents of the PC are updated to point

to the next instruction.

The MAR (Memory Address Register) holds the

address of the location to or from which data are to be

transferred.

The MDR (Memory Data Register) contains the data

to be written or read out of the addressed location.

The IR (Instruction Register) contains the instruction

that is being executed.

Main Memory

MAR

PC

IR

MDR

R0

R1

.

.

.

Rn-1

Control

ALU

n General Purpose

Registers

CPU


Operating Steps:

1. PC is set to point to the first instruction of the

program (the operating system loads the memory

address of the first instruction).

2. The contents of the PC are transferred to the

MAR (which are automatically transmitted to the

MM) and a Read signal is sent to the MM.

3. The addressed word is read out of MM and

loaded into the MDR.

4. The contents of MDR are transferred to the IR.

The instruction is ready to be decoded and

executed.

5. During execution, the contents of the PC are

incremented or updated to point to the next

instruction.

If operand or data needed by the instruction

resides in MM:

1. It will have to be fetched by sending its

address to the MAR and initiating a

read cycle.

2. When the operand has been read from

MM into the MDR, it may be

transferred from the MDR to the ALU

If result is to be stored in MM:

1. The result is sent to the MDR.

2. The address of the location where the

result is to be stored is sent to the MAR

and a write cycle is initiated.


BUS STRUCTURES

A bus is a collection of wires that connect several devices within a computer system.

When a word of data is transferred between units, all its bits are transferred in parallel.

A computer must have some lines for addressing and control purposes.

Three main groupings of lines:

1. Data Bus. This is for the transmission of data.

2. Address Bus. This specifies the location of data

in MM.

3. Control Bus. This indicates the direction of data

transfer and coordinates the timing of events

during the transfer.


Single-Bus Structure

All units are connected to a single bus, so it provides

the sole means of interconnection.

Only two units can actively use the bus at any given

time.

Bus control lines are used to arbitrate multiple

requests for the use of the bus.

Buffer Registers are used to hold information during

transfers. These prevent a high-speed processor from

being locked to a slow I/O device during a sequence

of data transfers.

Input Output Memory Processor


Two-Bus Structure

In the second configuration, I/O transfers are made

directly to or from the memory. A special purpose

processor called peripheral processor or I/O channel

is needed as part of the I/O equipment to control and

facilitate such transfers.

Input

Output

Processor Memory

I/O Bus

Memory

Bus

Input

Output

Memory Processor

I/O Bus

Memory

Bus

Configuration 2

Configuration 1


MEMORY LOCATIONS AND ADDRESSES

MM is organized so that a group of n bits can be stored or retrieved in a single basic operation.

The M addresses constitute the address space of the computer system.

Example: For the Intel 8088/86 Microprocessor

Address Space = 1,048,576 addresses or memory

locations

using binary encoding of

addresses, 20 bits are needed to

represent all addresses,

220 = 1,048,576

bn-1

b0

b1. . .

.

.

.

.

.

.

0

1

i

M - 1

Addressesn bits

word 0

word 1

word i

word M - 1


The contents of memory locations can represent either:

1. instructions

2. operands or data

numbers

characters

An instruction usually contains two parts:

1. the part that specifies the operation to be

performed (op-code field).

2. the part that may be used to specify operand

addresses.

Examples:

1. 32-bit instruction

2. 16-bit instruction (8088/86)

10001011 11101100

MOV SP TO BP

8 bits 24 bits

Operation

FieldAddressing Information


MAIN MEMORY OPERATIONS

Fetch or Read. This transfers the contents of a specific MM location to the CPU. The word in the

MM remains unchanged.

Read/Fetch Cycle:

1. CPU sends address of the desired

location.

2. MM reads the data stored at that

address and sends it to the CPU.

Store or Write. This transfers a word of information from the CPU to a specific MM location. This

destroys the former contents of that location.

Write/Store Cycle:

1. CPU sends address of the desired

location to the MM, together with the

data to be stored into that location.

2. Data is written at desired location.


INSTRUCTIONS AND INSTRUCTION SEQUENCING

Types of Instructions:

1. Data transfers between MM and CPU

registers.

2. Arithmetic and logic operations on data.

3. Program sequencing and control.

4. I/O operations or transfers.

Notations

R1 [LOC]

The contents of memory location LOC

are transferred into register R1.

C [A] + [B]

The operands in memory locations A

and B are fetched from MM and

transferred into the CPU, where they

will be added in the ALU. Then the

resulting sum is to be stored into

memory location C in MM.


Three-Address Instructions

ADD A, B, C A [B] + [C]

B and C = source operands

A = destination operands

Two-Address Instructions

ADD A, B A [A] + [B]

MOVE B, C B [C]

A common convention used is to write two-

operand instructions in the form:

operation destination, source

One-Address Instructions

Since addition is a two-operand operation, an

implicit assumption must be made regarding the

location of one of the operands as well as the

result.

A general purpose CPU register,

usually called the accumulator, may be

used for this purpose.


Examples:

ADD A ACC [A] + [ACC]

Add the contents of memory

location A to the contents of the

accumulator and place the sum

into the accumulator.

LOAD A ACC [A]

Move the contents of memory

location A into the accumulator.

STORE A A [ACC]

Move the contents of memory

location A into the accumulator.

Sample Program:

LOAD A ACC [A]

ADD B ACC [B] + [ACC]

STORE C C [ACC]

Zero-Address Instructions

Instructions where the locations of all operands

are defined implicitly.


Two-Phase Procedure in Instruction Execution:

1. Instruction Fetch.

Instruction is fetched from MM

location whose address is in the

program counter. The instruction

is then placed in the instruction

register in the CPU.

2. Instruction Execute.

The instruction in the instruction

register is examined to determine

which operation is to be

performed. The CPU then

performs the specified operation.


Instruction Execution and Straight-Line Sequencing.

Example 1:

To begin the execution of this program, the

address of its first instruction (i) must be placed

into the PC.

The CPU control circuits automatically proceed

to fetch and execute instructions, one at a time, in

the order of increasing addresses. This is

straight-line sequencing.

MOVE R0, AADD R0, B

.

.

.

.

.

.

i

i + 1

AddressesContents

MOVE C, R0i + 2

A

.

.

.

B

C

3-Instruction

Program

S egment

Data for the

program


Example 2:

This program will add a list of n numbers. The

addresses of the memory locations containing the

n numbers are symbolically given as NUM1,

NUM2, . . ., NUMn, and the resulting sum is

placed in memory location SUM.

MOVE R0, NUM1

ADD R0, NUM2

.

.

.

i

i + 1

AddressesContents

ADD R0, NUM3i + 2

ADD R0, NUMni + n - 1

MOVE SUM, R0i + n

.

.

.

S UM

NUM1

NUM2

.

.

.

NUMn


Branching

The fundamental idea in program loops

is to cause a straight-line sequence of

instructions to be executed repeatedly.

CLEAR R0

MOVE R1, N

Determine address of

"Next" number and

add "Next" number to

R0

DEC R1

Branch > 0

LOOPS TART

.

.

.

S UM

NUM1

NUM2

.

.

.

NUMn

LOOPS TART

MOVE S UM, R0

N

Program

Loop


8086/8088 ARCHITECTURE

HISTORY OF THE INTEL MICROPROCESSORS

The 4-bit Microprocessors

Intel released the worlds first p in 1971. The

4004 is a 4-bit p with maximum memory of only up to 4,096 4-bit memory locations (2,048

bytes). It only has 45 instructions and was used

in very limited applications such as early video

games and small p-based controllers.


1. In 1972, Intel released the 8008 which is an

8-bit p capable of addressing 16,384 bytes and has 48 instructions. It can execute an

ADD instruction in 20 s.

2. In 1973, Intel released the 8080. The 8080

can address a total of 65,536 bytes and can

execute an ADD instruction in 2 s only.

3. In 1977, the 8085 was released. It addresses

the same amount of memory as the 8080 but

it can execute an ADD instruction in 1.3 s. It also has a built-in clock generator and

system controller.



In 1978, Intel released the 8086 p and a year

later the 8088. Both are 16-bit ps and can execute instructions in as little as 400 ns. Both

can address a total of 1,048,576 bytes or

524,288 16-bit words.

These 16-bit microprocessors have multiplication

and division instructions. These functions were

not available in most 8-bit ps.

The main difference between the 8086 and the

8088 is the size of their external data bus. The

external data bus of the 8088 is only 8-bits wide

while that of the 8086 is 16-bits wide (take note

the internal data bus of the 8088 is 16-bits wide).

The reason for this is that many designers still

wanted to use the cheaper 8-bit support and

peripheral chips in their 16-bit systems.

The 8088 was the p used by IBM in their Personal Computer (PC), the PC XT, and the

Portable Computer.


BASIC 8086/8088 ARCHITECTURE

Execution Unit (EU). This is responsible for executing the instructions.

Bus Interface Unit (BIU). This is responsible for fetching an instruction, the operand of an instruction

or data from the MM.

Instruction Pointer (IP). This is the program counter.

Prefetch Queue. The 8086/8088 prefetches the succeeding instructions while executing the current

one.

Register

Array

Segment

Register and

IP

Bus

Controller

Prefetch

Queue

ALU & CU

IR

EU BIU


8086/8088 BUS STRUCTURE

Basic 8086 and 8088 Systems

The M/IO (or IO/M) signal is for selecting the memory or I/O of the system. If it is a logic 0, then

memory is selected; if it is logic 1, I/O is selected.

8086

S ystem

Address Bus

Data Bus

Control Bus

A0 to A19

D0 to D15

RD, WR, M/IO

To

Memory

and I/O

8088

S ystem

Address Bus

Data Bus

Control Bus

A0 to A19

D0 to D7

RD, WR, IO/M

To

Memory

and I/O


MEMORY AND THE 8086/8088

Logical memory is the name given to the memory viewed by the programmer.

The logical memory space is the same for both the

8086 and the 8088. It starts at memory location

00000H and extends to location FFFFFH. The logical

memory is 8 bits wide.

A 16-bit word of memory begins at any byte address

and extends for two consecutive bytes. For example,

the word at location 00122H is stored at byte 00122H

and 00123H with the least significant byte stored in

location 00122H.

1 M

Bytes

FFFFDH

00001H

00002H

00000H

FFFFEH

FFFFFH

8086/8088

Logical

Memory Map


The physical memory is the actual organization of the memory that the hardware designers see. The physical

memory map of the 8088 is identical to its logical

memory map.

The physical memory of the 8086 contains two banks

of memory.

The advantage of this organization is that the 8086 can

read or write a 16-bit word in one operation (provided

the addresses of the data are even). The 8088 requires

two reads or writes to transfer 16 bits of data.

512 K

Bytes

FFFFBH

00003H

00005H

00001H

FFFFDH

FFFFFH

512 K

Bytes

FFFFAH

00002H

00004H

00000H

FFFFCH

FFFFEH

Odd Bank Even Bank

16 bits


DEDICATED AND GENERAL USE OF MEMORY

Addresses 00000H to 00013H (20 memory locations) are dedicated while addresses 00014H to 0007FH

(108 memory locations) are reserved.

These 128 bytes or memory locations

are used for storage or pointers to

interrupt service routines.

Addresses FFFF0H to FFFFBH (12 memory locations) are dedicated for functions such as storage

of the hardware reset jump instruction.

Addresses FFFFCH to FFFFFH (4 memory locations) are reserved for use with future products.


THE PROGRAMMING MODEL

All forms of programming depend upon a clear understanding of the internal register structure of the

p.

Register Structure of the 8086/8088

AH AL

BH BL

CH CL

DH DL

AX Accumulator

BX Base

CX Count

DX Data

S P S tack Pointer

BP Base Pointer

S I S ource Index

DI Destination Index

IP Instruction Pointer

CS Code S egment

DS Data S egment

S S S tack S egment

ES Extra S egment

Flags

8 Bits 8 Bits

16 Bits

General

Purpose

Register

Pointer and

Index

Registers

S egment

Registers


General Purpose Registers. These are used in any manner that the programmer wishes. Each is

addressable as a 16-bit register (AX, BX, CX, DX) or

as two 8-bit registers (AH, AL, BH, BL, CH, CL, DH,

and DL).

1. AX (Accumulator). This is often used to

hold temporary result after an arithmetic and

logic operation.

2. BX (Base). This is often used to hold the

base address of data located in the memory.

3. CX (Count). This holds the count for

certain instructions such as shift count (CL)

for shifts and rotates, the number of bytes

(CX) operated upon by the repeated string

instructions, and a counter (CX) with the

LOOP instruction.

4. DX (Data). This holds the most significant

part of the product after a 16-bit

multiplication and the most significant part

of the dividend before a division.


Pointer and Index Registers. Although the pointer and index registers are also general purpose in nature,

they are more often used to index or point to the

memory location holding the operand data for many

instructions.

1. SP (Stack Pointer). This is used to address

data in a LIFO (last-in first-out) stack

memory. This occurs most often when the

PUSH and POP instructions are executed.

2. BP (Base Pointer). This is often used to

address an array of data in memory.

3. SI (Source Index). This is used to address

source data indirectly for use with string

instructions.

4. DI (Destination Index). This is normally

used to address destination data indirectly

for use with the string instructions.


Status Register or Processor Status Word. This contains 16 bits, but 7 of them are not used. Each bit

in the PSW is a flag. These flags are divided into the

conditional flags (they reflect the result of the

previous operation involving the ALU) and the

control flags (they control the execution of special

functions).

The conditional flags are:

1. Sign Flag (SF) - b7

This is equal to the MSB of the result

of the previous operation. 0 if positive,

1 if negative.

2. Zero Flag (ZF) - b6

This is set to 1 if the result of the

previous operation is zero and 0 if the

result is nonzero.

3. Parity Flag (PF) - b2

This is set to 1 if the low-order 8 bits of

the result of the previous operation

contain an even number of 1s.

Otherwise, it is reset to 0.


4. Carry Flag (CF) - b0

An addition causes this flag to be set to

1 if there is a carry out of the MSB, and

a subtraction causes it to be set to 1 if

a borrow is needed.

5. Overflow Flag (OF) - b11

This is set to 1 if an overflow occurs, i.e., a result

is out of range. More specifically, for addition

this flag is set to 1 when there is a carry into the

MSB and no carry out of the MSB or vice-versa.

For subtraction, it is set to 1, when the MSB

needs a borrow and there is no borrow from the

MSB, or vice-versa.

6. Auxiliary Carry Flag (AF) - b4

This flag is used exclusively for BCD

arithmetic. It is set to 1 if there is a

carry out of bit 3 (b3) during an

addition or a borrow by bit 3 during a

subtraction.


Examples:

0010 0011 0100 0101

+ 0011 0010 0001 1001

0101 0101 0101 1110

SF = 0 ZF = 0 PF = 0 CF = 0 AF = 0 OF = 0

0101 0100 0011 1001

+ 0100 0101 0110 1010

1001 1001 1010 0011

SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 OF = 1

0110 0010 1010 0000

+ 1001 1101 0110 0000

0000 0000 0000 0000

SF = 0 ZF = 1 PF = 1 CF = 1 AF = 0 OF = 0

0001 0010 0011 0100

- 0100 1010 1110 0000

1100 0111 0101 0100

SF = 1 ZF = 0 PF = 0 CF = 1 AF = 0 OF = 0


The control flags are:

1. Direction Flag (DF) - b10

This flag is used by string manipulation instructions. If clear, the string is processed from its beginning

with the first element having the lowest address. Otherwise, the string is processed from the high address

towards the low address.

2. Interrupt Enable Flag (IF) - b9

If set, a certain type of interrupt (a

maskable interrupt) can be recognized

by the CPU; otherwise, these interrupts

are ignored.

3. Trap Flag (TF) - b8

If set, the 8086/8088 will enter into a

single-step mode. In this mode, the

CPU executes one instruction at a time.


SEGMENT REGISTERS AND MEMORY SEGMENTATION

Even though the 8086/8088 has a 1 MB memory address space, not all this memory can be active at any

one time.

The MM can be partitioned into 64 K (65,536) byte segments where each segment represents an

independently addressable unit of memory consisting

of 64 K consecutive byte-wide storage locations.

Each segment is assigned a base address that identifies its starting point, that is, its lowest-

addressed byte storage location.

64 KB

S egment

Base Address


GENERATING A MEMORY ADDRESS

A logical address in the 8086/8088 is identified by a segment (its base address) and an offset. The offset

identifies the distance in bytes that the storage location

of interest resides from this starting address.

Both segment base address and offset are 16 bits long. Therefore, the lowest-addressed byte in a segment has

an offset of 0000H and the highest-addressed byte has

an offset of FFFFH.

However, the physical addresses that are used to access memory are 20 bits long. The generation of the

physical address involves combining a 16-bit offset

value and a 16-bit segment base address value that is

shifted-left by 4 bits with its LSBs being filled with 0s.

.

.

.

Data

Base Address

.

.

.

64 KB

Segment

Offset


Examples:

1. Segment Base Address = 1234H

Offset Address = 0022H

Computing for the physical address:

Physical Segment Base Address = 12340H

+ Offset Address = 0022H

Physical Address = 12362H

2. Segment Base Address = 123AH

Offset Address = 341BH

Computing for the physical address:

Physical Segment Base Address = 123A0H

+ Offset Address = 341BH

Physical Address = 157BBH

Take note that the offset address is sometimes called the effective address.

Logical addresses are often written following the segment base address:offset format.

Example: 1234H:0022H


Only four of these segments can be active at any one time. They are the code segment, stack segment, data

segment, and extra segment.

The locations of the segments of memory that are active are identified by the value of the address held in

the 8086/8088s four internal segment registers; CS, SS, DS, and ES.

Code

S egment

S tack

S egment

Data

S egment

Extra

S egment

CS

S S

DS

ES

S egment

Registers


The segments are:

1. Code Segment. This contains the program or

code. The address of the next instruction

executed by the 8086/8088 is generated by

adding the contents of IP (offset address) to the

contents of CS x 10H.

2. Data Segment. This contains data referenced by

almost all instructions and many addressing

modes. Data are almost always moved into or

out of MM via the data segment. The physical

address of the data is generated by adding the

contents of one of the index or pointer registers

(BX, DI, or SI) to the contents of DS x 10H.

3. Stack Segment. This is for the LIFO stack. The

physical address is a combination of the contents

stack pointer (SP) plus SS x 10H.

4. Extra Segment. This is normally for string

instructions. When a string instruction is

executed, the destination location is addressed by

the destination index register (DI) plus ES x 10H.


THE STACK

The stack is implemented in MM of the 8086/8088. It is 64 KB long and is organized from a software point

of view as 32 K words.

The lowest-addressed byte in the current stack is pointed to by the base address in the SS register.

Any number of stacks may exist in the 8086/8088. A new stack can be brought in by simply changing the

value in the SS register. However, only one may be

active at any one time.

The SP contains an offset from the value in SS. The address obtained in the SS and SP is the physical

address of the top of the stack or TOS (the last storage

location in the stack to which data were pushed).

The value of SP is initialized to FFFFH upon start-up of the microcomputer. Combining the value with the

current value in SS gives the highest-addressed

location in the stack (bottom of the stack). The stack

grows down in memory from offset FFFFH to 0000H.


Whenever a word of data is pushed onto the stack, the high-order 8 bits are placed in the location addressed

by SP - 1, and the low-order 8 bits are placed in the

location addressed by SP - 2.

SP is then decremented by 2 so that the next

word of data is stored in the next available

memory location.

Example:

PUSH BX

Assume: BX = 1234H

SS = 1800H SP = 3A74H

Bottom of the Stack = SS x 10H + FFFFH

= 18000H + FFFFH

= 27FFFH

Stack Segment = 18000H up to 27FFFH

Top of the Stack = SS x 10H + SP

= 18000H + 3A74H

= 1BA74H

PUSH BX; 1BA73H (BH) = 12H

1BA72H (BL) = 34H

New Top of Stack = 1BA72H (SP = 3A72H)


Whenever a word of data is popped from the stack, the low-order 8 bits are removed from the location

addressed by SP, and the high-order 8 bits are

removed from the location addressed by SP + 1.

SP is then incremented by 2.

Example:

POP CX

Assume: SS = 1234H SP = 281AH

Bottom of the Stack = SS x 10H + FFFFH

= 12340H + FFFFH

= 2233FH

Stack Segment = 12340H up to 2233FH


= 12340H + 281AH

= 14B5AH

POP CX; CL (14B5AH)

CH (14B5BH)

New Top of Stack = 14B5CH (SP = 281CH)


ADDRESSING MODES

Addressing modes refer to the way in which an operand is specified.

Data Addressing Modes:

Case Study: MOV destination, source

1. Register Addressing. The operand to be

accessed is specified as residing in an internal

register of the 8086/8088.

Examples:

MOV AX, CX; AX [CX]

MOV BX, DX; BX [DX]

In both examples, AX and BX are the destination

operands while CX and DX are the source

operands.

2. Immediate Addressing. The source operand is

part of the instruction instead of the contents of a

register. Typically, immediate operands

represent constant data.

Examples:

MOV AL, 15H; AL 15H

MOV AX, 1A3F; AX 1A3FH


3. Direct Addressing. The location following the

instruction opcode holds an effective memory

address (EA) instead of data. This EA is the 16-

bit offset of the storage location specified by the

current value of the DS register.

Examples:

MOV AX, BETA

AX [DS x 10H + BETA]

If BETA = 1234H and DS = 0200H, then:

PA = DS x 10H + BETA

= 02000H + 1234H = 03234H

MOV AX, BETA; AX [03234H]

AL [03234H]

AH [03235H]


MOV AX, LIST

AX [DS x 10H + LIST]

If LIST = 000AH and DS = BAAFH, then:

PA = DS x 10H + LIST

= BAAF0H + 000AH = BAAFAH

MOV AX, LIST; AX [BAAFAH]

AL [BAAFAH]

AH [BAAFBH]

MOV CL, [2000H]

CL [DS x 10H + 2000H]

If DS = 1000H, then:

PA = DS x 10H + 2000H

= 10000H + 2000H = 12000H

MOV CL, [2000H]; CL [12000H]


4. Register Indirect Addressing. Similar to direct

addressing but this time, the EA resides in either

a base register (BX, BP) or index register (SI, DI)

within the 8086/8088.

Examples:

MOV AX, [BX]; AX [DS x 10H + BX]

If BX = C15EH and DS = 1829H, then:

PA = DS x 10H + BX

= 18290H + C15EH = 243EEH

MOV AX, [BX]; AX [243EEH]

AL [243EEH]

AH [243EFH]

MOV AX, [SI]; AX [DS x 10H + SI]

If SI = 00BEH and DS = 58A2H, then:

PA = DS x 10H + SI

= 58A20H + 00BEH = 58ADEH

MOV AX, [SI]; AX [58ADEH]

AL [58ADEH]

AH [58ADFH]


If BP is used, then the stack segment is addressed

instead of the data segment

Example:

MOV CX, [BP]; AX [SS x 10H + BP]

If BP = 1800H and SS = 8050H, then:

PA = SS x 10H + BP

= 80500H + 1800H = 81D00H

MOV CX, [BP]; CX [81D00H]

CL [81D00H]

CH [81D01H]


5. Register Relative Addressing or Base

Addressing. The physical address of the operand

is obtained by adding a direct or indirect

displacement to the contents of either BX or BP

and the current value in DS or SS, respectively.

Examples:

MOV AX, [BX + 1000H]

AX [DS x 10H + BX + 1000H]

If BX = 0100H and DS = 0200H, then:

PA = DS x 10H + BX + 1000H

= 02000H + 0100H + 1000H

= 03100H

MOV AX, [BX + 1000H]; AX [03100H]

AL [03100H]

AH [03101H]


MOV AL, [BX] + BETA

AX [DS x 10H + BX + BETA]

If BX = 1000H, BETA = 1234H and DS =

0200H, then:

PA = DS x 10H + BX + BETA

= 02000H + 1000H + 1234H

= 04234H

MOV AL, [BX] + BETA;

AL [04234H]

MOV DI, SET[BX]

DI [DS x 10H + SET + BX]

If BX = FB04H, SET = 001AH, and DS =

0210H, then:

PA = DS x 10H + SET + BX

= 02100H + 001AH + FB04H

= 11C1EH

MOV DI, SET[BX]; DI [11C1EH]

DIlow [11C1EH]

DIhigh [11C1FH]


6. Base-Plus-Index Addressing. This is used to

transfer a byte or word between a register and the

memory location indicated by the sum of a base

register and an index register.

Examples:

MOV AX, [BX + SI]

AX [DS x 10H + BX + SI]

If SI = 2000H, BX = 1234H, and DS = 0200H,

then:

PA = DS x 10H + BX + SI

= 02000H + 1234H + 2000H

= 05234H

MOV AX, [BX + SI]; AX [05234H]

AL [05234H]

AH [05235H]


MOV [BX + DI], SP

[DS x 10H + BX + DI] SP

If DI = 175CH, BX = 1256H, and DS = 0205H,

then:

PA = DS x 10H + BX + DI

= 02050H + 1256H + 175CH

= 04A02H

MOV [BX + SI], SP; 04A02H [SP]

04A02H [SPlow]

04A03H [SPhigh]


7. Base-Relative-Plus-Index Addressing. This is

used to transfer a byte or word between a register

and the memory location addressed by a base

register and an index register plus a

displacement.

Examples:

MOV AX, [BX + SI + 0100H];

AX [DS x 10H + BX + SI + 1000H]

If DS = 1000H, BX = 0020H, and SI = 0010H,

then:

PA = DS x 10H + BX + SI + 1000H

= 10000H + 0020H + 0010H + 1000H

= 11030H

MOV AX, [BX + SI + 1000H];

AX [11030H]

AL [11030H]

AH [11031H]


MOV AX, FILE[BX + DI];

AX [DS x 10H + BX + DI + FILE]

If DS = 1F00H, BX = 3000H, DI = 0015H, AND

FILE = 1234H, then:

PA = DS x 10H + BX + DI + FILE

= 1F000H + 3000H + 0015H + 1234H

= 23249H

MOV AX, FILE[BX + DI];

AX [23249H]

AL [23249H]

AH [2324AH]


BASIC 8086/8088 INSTRUCTIONS

INTRODUCTION

The instruction set of a microcomputer defines the basic operations that a programmer can make the

device perform.

There are 117 basic instructions for the 8086/88 chip.

Classification of Instructions:

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logic Instructions

4. Shift Instructions

5. Rotate Instructions

6. Flag Control Instructions

7. Jump Instructions

8. String Instructions


DATA TRANSFER INSTRUCTIONS

Data transfer instructions facilitate the movement of data either between registers or between a register and

main memory. They do not affect the flags.

The MOV Instruction

Format: MOV D, S

Action: D [S]

Destination Source Example

register register MOV CX, BX

register MM MOV CX, [BP+SI]

MM register MOV [BX], DX

register immediate MOV CX, 80FEH

MM immediate MOV word ptr [BX], 1834H

seg reg register MOV DS, BX

register seg reg MOV AX, CS

seg reg MM MOV SS, [1AFFH]

MM seg reg MOV [BP+SI+1000H], DS


Pointers:

1. The MOV instruction does not allow both source

and destination operands to be memory locations

(no memory to memory transfers). The

instruction MOV [BX], FILE is invalid.

2. Both source and destination operands should be

of the same data size. Therefore, the instruction

MOV AH, BX is invalid.

3. Immediate data cannot be moved to a segment

register. MOV DS, 1800H is therefore invalid.

Instead, use:

MOV AX, 1800H

MOV DS, AX

4. The destination operand cannot be immediate

data. MOV 1800H, AX is therefore invalid.

5. More often than not, register CS cannot be the

destination operand.

6. If the destination operand is a memory location

and the source operand is immediate data, the

prefix byte ptr or word ptr should appear after the

MOV instruction to denote the data size of the

immediate operand.


The XCHG Instruction

The XCHG (Exchange) instruction swaps the

contents of the source and destination operands.

Format: XCHG D, S

Action: [D] [S]


MM register XCHG [BX], CX

register register XCHG AH, BL

Pointers:

1. The XCHG instruction does not allow both

source and destination operands to be memory

locations (no memory to memory transfers). The

instruction XCHG [BX], FILE is therefore

invalid.



XCHG AH, BX is invalid.


3. Immediate addressing cannot be used with this

instruction. The instruction XCHG AX, 1800H

is invalid.

4. A data exchange can also be done using several

MOV instructions:

MOV CX, AX

MOV DX, BX

MOV AX, DX

MOV BX, CX

However, four registers are needed in order to

implement an exchange between two registers.

5. Segment registers cannot be used as operands in

the XCHG instruction. XCHG ES, BX is

therefore invalid. Instead use:

MOV CX, ES

XCHG BX, CX

MOV ES, CX


The PUSH Instruction

The PUSH instruction decrements SP by 2 and then

moves a word data from the source operand to the top

of the stack pointed to by SP.

Format: PUSH S

Action: SP SP - 2

[SP+ 1] [SH]

[SP] [SL]

Source Example

register PUSH AX

seg reg PUSH DS

MM PUSH BETA

Pointers:

1. The PUSH instruction pushes word-sized data

only.


The POP Instruction

POP transfers a word data pointed to by SP to the

destination operand. Afterwards, the value of SP is

incremented by 2.

Format: POP D

Action: DL [SP]

DH [SP + 1]

SP SP + 2

Destination Example

register POP AX

seg reg POP DS

MM POP BETA

Pointers:

1. The POP instruction pops word-sized data only.

2. POP CS is not allowed. However, the

instruction PUSH CS is valid.


The LEA Instruction

The LEA (Load Effective Address) instruction is for

transferring the effective address (not data) of the

source operand to the destination operand.

Format: LEA D, S

Action: D EA of S

Pointers:

1. The source operand should always be one of the

memory addressing modes, while the destination

operand should always be a 16-bit register.

2. In the LEA instruction, the effective address is

moved to the destination operand. Therefore, the

destination operand is like a pointer.

3. Usually, registers BX, BP, DI, or SI are used as

the destination operand since these registers

could be used as offset registers.


Examples:

Assume the following:

DS = 5000H

LIST = 1800H

If the MOV DI, LIST instruction is

executed, the contents of memory location

51800H and 51801H are transferred to

register DI. DI will therefore contain the

word 3322H.

However, if the LEA DI, LIST instruction

is executed, this will transfer the effective

address of the source operand to register DI.

Therefore, DI will now contain 1800H.

44H

33H

22H

11H

51800H

517FFH

51801H

51802H


ARITHMETIC INSTRUCTIONS

Review of Some Concepts Regarding the Binary Number System

1. Unsigned Integer. Unsigned integers may either

be 8 bits or 16 bits in length. Unsigned integers

are viewed as positive numbers only. This means

that all bits are considered in determining the

magnitude of a number.

The value range of an unsigned integer is from 0

to 2n - 1. For 8 bits, the range is from 0 to 255,

while for 16 bits, the range is from 0 to 65,535.

2. Signed Integer. Signed integers are viewed as

either positive or negative numbers. Because of

this, the most significant bit is viewed as a sign

bit (0 for positive and 1 for negative).

The value range of a signed integer is -2n-1 to 2n-1

- 1. For 8 bits, the range is from -128 to +127

while for 16 bits, the range is from -32,768 to

+32,767. Negative numbers are represented in

twos complement.


3. Binary-Coded Decimal (BCD). In BCD, each

decimal digit is represented in one nibble.

Examples:

99 = 1001 1001

103 = 0001 0000 0011

BCD uses only 10 out of 16 possible

combinations. The following 6 combinations are

never used: 1010, 1011, 1100, 1101, 1110, and

1111.

There are some situations in which arithmetic

operations on BCD numbers require some

adjustments. This happens if the result of the

operation falls into one of the six unused

combinations.

Examples:

12 = 0001 0010

+ 45 = 0100 0101

57 0101 0111

In this example, there is no need to

adjust result.


12 = 0001 0010

+ 49 = 0100 1001

61 0101 1011

Since 1011 is an invalid BCD code,

there is a need to adjust result. This

can be done by adding 6 (0110) to the

result:

0101 1011

+ 0110

0110 0001 = 61

The 8086/8088 provides adjustment instructions

for BCD-based arithmetic operations.

4. Packed BCD. In packed BCD, two BCD digits

could be packed into one byte.

5. Unpacked BCD. In unpacked BCD, one BCD

digit is represented in one byte. The BCD digit is

represented in the least significant nibble, while

the most significant nibble may be 0 or any value.


Arithmetic instructions cover the four basic arithmetic operations: addition, subtraction, multiplication, and

division. Arithmetic instructions affect the status

flags.

The ADD Instruction

The ADD instruction adds the source operand to the

destination operand and then places the result in the


Format: ADD D, S

Action: D [D] + [S]


register register ADD BX, CX

register MM ADD DX, [BP + SI]

MM register ADD [BX + DI], CX

register immediate ADD BX, 0015H

MM immediate ADD byte ptr BETA, 12H

Pointers:

1. The ADD instruction does not allow both

source and destination operands to be

memory locations (no memory to memory

addition). Therefore, the instruction ADD

[BX], BETA is invalid.


2. Both source and destination operands

should be of the same data size. The

instruction ADD AH, BX is therefore

invalid.

3. The destination operand cannot be

immediate data. Therefore, the instruction

ADD 1800H, CX is invalid.

4. All status flags are affected after execution.

5. As with the MOV instruction, if the

destination operand is a memory location

and the source operand is immediate data,

the prefix byte ptr or word ptr should appear

after the ADD instruction to denote the data

size of the immediate operand.

The ADC Instruction

The ADC (Add with Carry) instruction adds the

source operand and the carry flag to the destination

operand and places the result in the destination

operand.

Format: ADC D, S

Action: D [D] + [S] + [CF]

One of the uses of the ADC instruction is in the

implementation of 32-bit addition (adding two 32-bit

numbers).


Example:

012F 8749H

+ 3054 9312H

3184 1A5BH

Although there are no 32-bit addition

instructions, the problem is easily solved by

using the ADD and the ADC instructions.

MOV AX, 012FH

MOV BX, 8749H

MOV CX, 3054H

MOV DX, 9312H

ADD BX, DX

ADC AX, CX

The INC Instruction

The INC (Increment) instruction adds 1 to the


Format: INC D

Action: D [D] + 1

Destination Example

register INC AX

MM INC byte ptr [BX]


Pointers:

1. The destination operand is viewed as an unsigned

integer.

2. The INC instruction does not affect the carry

flag.

3. Segment registers cannot be used as the

destination operand. Therefore, the instruction

INC CS is invalid.

4. If the destination operand is a memory location,

the prefix byte ptr or word ptr should appear after

the INC instruction to denote the data size of the


The DAA Instruction

The DAA (Decimal Adjust for Addition) instruction

adjusts the result of a previous addition of two valid

packed decimal operands.

Format: DAA

Pointers:

1. The result of the previous operation should be in

register AL.

2. OF is undefined after execution.

3. DAA should be executed immediately after an

ADD, ADC, or INC instruction.


4. The instruction will adjust the result as follows: if

AF = 1, or either of the nibbles is greater than 9,

then 6 is added to the nibble(s) concerned.

Example:

MOV AL, 15H

MOV BL, 15H

ADD AL, BL

DAA

In this example, the values of AL and BL are

viewed as packed BCD. Since DAA is used to

adjust the addition operation, the destination

operand should be at AL. Prior to DAA, the

value of AL is 2AH. After the DAA instruction,

the value of AL is adjusted to 30H. The

operation is as follows:

15H = 0001 0101

15H = 0001 0101

0010 1010 = 2AH

+ 0110

0011 0000 = 30H

Since the least significant nibble of the

intermediate result is greater than 9, DAA adjusts

the result by adding 6 to the least significant

nibble.


The AAA Instruction

The AAA (ASCII Adjust for Addition) instruction

adjusts the result of a previous addition of two valid

unpacked decimal operands.

Format: AAA

Pointers:


register AL.

2. OF, PF, SF, and ZF are undefined after

execution.

3. AAA should be executed immediately after an

ADD, ADC, or INC instruction.


the least significant nibble is greater than 9, then

6 is added to AL, and 1 is added to AH.

5. Regardless of the value of the least significant

nibble, the most significant nibble is always

zeroed out.


Example:

MOV AL, 35H; ASCII value of 5

MOV BL, 34H; ASCII value of 4

ADD AL, BL

AAA


viewed as unpacked BCD (ASCII numbers).

Since AAA is used to adjust the addition

operation, the destination operand should be at

AL. Prior to AAA, the value of AL is 69H.

After the AAA instruction, the value of AL is

adjusted to 09H. The operation is as follows:

35H = 0011 0101

34H = 0011 0100

0110 1001 = 69H

Since the least significant nibble not greater than

9, the only adjustment needed is to zero out the

most significant nibble.


The SUB Instruction

The SUB instruction subtracts the source operand

from the destination operand and the places the result

in the destination operand.

Format: SUB D, S

Action: D [D] - [S]

The SBB Instruction

The SBB (Subtract with Borrow) instruction subtracts

the source operand and the carry flag from the

destination operand and then places the result in the


Format: SBB D, S

Action: D [D] - [S] - [CF]

Just like in addition, subtracting a 32-bit number from

another 32-bit number can be done with the

combination of the SUB and the SBB instructions.


Example:

3054 8312H

- 012F 8749H

2F24 FBC9H

MOV AX, 3054H

MOV BX, 8312H

MOV CX, 012FH

MOV DX, 8749H

SUB BX, DX

SBB AX, CX

The DEC Instruction

The DEC (Decrement) instruction subtracts 1 from

the destination operand.

Format: DEC D

Action: D [D] - 1

Destination Example

register DEC AX

MM DEC word ptr [BX]


Pointers:

1. The destination operand is viewed as an unsigned

integer.

2. The DEC instruction does not affect the carry

flag.



DEC CS is invalid.



the DEC instruction to denote the data size of the


The NEG Instruction

The NEG (Negate) instruction converts the specified

operand to its 2s complement equivalent and the result returned to the operand location. This is, in

effect, reversing the sign of an integer.

Format: NEG D

Action: D 0 - [D]

Destination Example

register NEG AX

MM NEG byte ptr [BX]


Pointers:

1. Attempting to negate an operand having a value

of zero causes no change to the operand and

resets the carry flag (CF = 0).

2. Attempting to negate an operand having a value

of either 80H or 8000H causes no change to the

operand and sets the overflow flag (OF = 1).



NEG CS is invalid.



the NEG instruction to denote the data size of the


Example:

Determine the value of AL and the value of

the flags following the instruction sequence:

MOV AL, 05H

NEG AL

AL contains:

0000 0000

- 0000 0101

1111 1011 = FBH = - 5

The flags are affected as follows:

CF = AF = SF =1, PF = ZF = OF = 0


The DAS Instruction

The DAS (Decimal Adjust for Subtraction)

instruction adjusts the result of a previous subtraction

of two valid packed decimal operands.

Format: DAS

Pointers:


register AL.

2. OF is undefined after execution.

3. DAS should be executed immediately after a

SUB, SBB, or DEC instruction.


AF = 1, or either of the nibbles is greater than 9,

then 6 is subtracted from the nibble(s) concerned.


Example:

MOV AL, 34H

MOV BL, 19H

SUB AL, BL

DAS


viewed as packed BCD. Since DAS is used to

adjust the subtraction operation, the destination

operand should be at AL. Prior to DAS, the

value of AL is 1BH. After the DAS instruction,

the value of AL is adjusted to 15H. The

operation is as follows:

34H = 0011 0100

19H = 0001 1001

0001 1011 = 1BH

- 0110

0001 0101 = 15H

Since the least significant nibble of the

intermediate result is greater than 9, DAS adjusts

the result by subtracting 6 to the least significant

nibble.


The AAS Instruction

The AAS (ASCII Adjust for Subtraction) instruction

adjusts the result of a previous subtraction of two

valid unpacked decimal operands.

Format: AAS

Pointers:


register AL.

2. OF, PF, SF, and ZF are undefined after

execution.

3. AAS should be executed immediately after a

SUB, SBB, or DEC instruction.


the least significant nibble is greater than 9, then

6 is subtracted from AL, and 1 is subtracted from

AH.

5. Regardless of the value of the least significant

nibble, the most significant nibble is always

zeroed out.


Example:

MOV AL, 39H; ASCII value of 9

MOV BL, 34H; ASCII value of 4

SUB AL, BL

AAS

In this example, the values of AL and BL are viewed as

unpacked BCD (ASCII numbers). Since AAS is

used to adjust the subtraction operation, the

destination operand should be at AL. Prior to

AAS, the value of AL is 05H. After the AAS

instruction, the value of AL is adjusted to 05H.

The operation is as follows:

39H = 0011 1001

34H = 0011 0100

0000 0101 = 05H

Since the least significant nibble not greater than

9, the only adjustment needed is to zero out the

most significant nibble.


The CMP Instruction

The CMP (Compare) instruction subtracts the source

operand from the destination operand. It then discards

the result but it updates the values of all the status

flags.

Format: CMP D, S

Action: [D] - [S]


register register CMP BX, CX

register MM CMP CX, BETA

MM register CMP BETA, DX

register immediate CMP SI, ABCDH

MM immediate CMP byte ptr [BX], 34H

Pointers:

1. The CMP instruction does not allow both source


(no memory to memory comparison). CMP

[BX], BETA is therefore invalid.



CMP AX, CL is invalid.

3. As with the MOV instruction, if the destination

operand is a memory location and the source

operand is immediate data, the prefix byte ptr or

word ptr should appear after the CMP instruction

to denote the data size of the immediate operand.


Program Tracing Example:

Trace the following program. Assume the following:

all flags and registers (unless specified otherwise) are

initially zero, DS = 8000H, SS = 8001H, the label

ALPHA = 0020H. Use the attached memory map (if

necessary).

MOV AX, ALPHA

MOV SP, AX

POP BX

ADD BX, AX

SUB BX, 0020H

XCHG BX, BP

MOV CX, [BP]

SBB AX, CX

ADC AX, 0029H

ADD AL, CL

DAA

NEG AX

LEA SI, ALPHA

MOV DX, [SI]


Solution:

1. The instruction MOV AX, ALPHA simply loads the

contents of the memory location whose offset is

ALPHA to AX.

Physical Address = DS x 10H + ALPHA

= 80000H + 0020H

= 80020H

Since [80020H] = 50H and [80021H] = 00H, the

contents of AX will be 0050H. The flags are not

affected (all flags are still zero).

2. The instruction MOV SP, AX copies the contents of

AX to SP. SP will therefore be equal to 0050H. Flags

are not affected.

3. The instruction POP BX transfers the contents of the

top of the stack to register BX.


= 80010H + 0050H

= 80060H


contents of BX will be 0010H. The new contents of

SP will be SP + 2 = 0052H. Flags are not affected.


4. The instruction ADD BX, AX adds the contents of BX

to the contents of AX and stores the results in BX.

AX = 0050H

+ BX = 0010H

0060H

The new contents of BX will be 0060H. The flags

will be:

OF SF ZF AF PF CF

0 0 0 0 1 0

5. The instruction SUB BX, 0020H will subtract 0020H

from the contents of register BX.

BX = 0060H

- 0020H

0040H

The new contents of BX will be 0040H. The flags

will be:

OF SF ZF AF PF CF

0 0 0 0 0 0


6. The instruction XCHG BX, BP will merely exchange

the contents of BX and BP with one another.

Since BP = 0000H and BX = 0040H, the new contents

will be BP = 0040H and BX = 0000H. The flags are

not affected and will remain as (from previous

instruction):

OF SF ZF AF PF CF

0 0 0 0 0 0

7. The instruction MOV CX, [BP] moves the contents of

the memory location whose offset is pointed to by BP

to CX. Since BP is used, the SS register is addressed

instead of DS.

Physical Address = SS x 10H + BP

= 80010H + 0040H

= 80050H

Since [80050H] = 31H and [80051H] = 1FH, then the

new contents of CX will be 1F31H. The flags are not

affected and will remain as (from previous

instruction):

OF SF ZF AF PF CF

0 0 0 0 0 0


8. The instruction SBB AX, CX will subtract the contents

of CX and the carry flag from AX and stores the

results to AX.

AX = 0050H

- CX = 1F31H

- CF = 0

E11FH

The new contents of AX will be E11FH. The flags

will be:

OF SF ZF AF PF CF

0 1 0 1 0 1

9. The instruction ADC AX, 0029H adds the contents of

the hexadecimal number 0029H and the carry flag to

AX and stores the results to AX.

AX = E11FH

+ 0029H

+ CF = 1

E149H

The new contents of AX will be E149H. The flags

will be:

OF SF ZF AF PF CF

0 1 0 1 0 0


10. The instruction ADD AL, CL will add the contents of

AL to CL and store the results to AL.

AL = 49H

+ CL = 31H

7AH

The new contents of AL will be 7AH. The flags will

be:

OF SF ZF AF PF CF

0 0 0 0 0 0

11. The instruction DAA means that the previous addition

should be treated as a BCD addition.

Since the result of the previous addition is an invalid

BCD number (7AH), the DAA instruction will adjust

the result.

AL = 7AH

+ 06H

80H

The new contents of AL will be 80H. The flags will

be:

OF SF ZF AF PF CF

X 1 0 1 0 0


12. The instruction NEG AX will simply perform 2s complement on the contents of AX.

The contents of AX is E180H. The twos complement of E180H is 1E80H.

The new contents of AX will be 1E80H. The flags

will be:

OF SF ZF AF PF CF

0 0 0 0 0 1

13. The instruction LEA SI, ALPHA will load the

effective address or offset represented by the label

ALPHA to register SI.

Since ALPHA is 0020H, the new contents of SI will

be 0020H.

The flags are not affected and will remain as (from

previous instruction):

OF SF ZF AF PF CF

0 0 0 0 0 1


14. The instruction MOV DX, [SI] simply moves the

contents of the memory location whose offset is

pointed to by SP to DX.

Physical Address = DS x 10H + SI

= 80000H + 0020H

= 80020H


contents of DX will be 0050H. The flags are not

affected and will remain as (from previous

instruction):

OF SF ZF AF PF CF

0 0 0 0 0 1


MEMORY MAP

80000H 11H 80020H 50H 80040H 85H 80060H 10H

80001H 2BH 80021H 00H 80041H D0H 80061H 00H

80002H 3EH 80022H 0AH 80042H 7AH 80062H 59H

80003H 22H 80023H 6FH 80043H EDH 80063H 42H

80004H 80H 80024H A5H 80044H 47H 80064H 87H

80005H 67H 80025H 2FH 80045H 46H 80065H 50H

80006H 54H 80026H 17H 80046H A7H 80066H 9FH

80007H 5FH 80027H DAH 80047H 7EH 80067H 5AH

80008H 0EH 80028H 08H 80048H 96H 80068H C0H

80009H 0FH 80029H 0BH 80049H F2H 80069H 97H

8000AH F4H 8002AH 2EH 8004AH BCH 8006AH AEH

8000BH 6BH 8002BH CFH 8004BH 52H 8006BH 7CH

8000CH 4CH 8002CH 25H 8004CH 8BH 8006CH 1AH

8000DH 75H 8002DH D7H 8004DH F9H 8006DH 84H

8000EH AAH 8002EH 39H 8004EH 53H 8006EH 2EF

8000FH EFH 8002FH 56H 8004FH BBH 8006FH 9EH

80010H FDH 80030H 20H 80050H 31H 80070H B9H

80011H 3DH 80031H DFH 80051H 1FH 80071H C2H

80012H 4FH 80032H 8FH 80052H F7H 80072H 2EH

80013H 08H 80033H 44H 80053H FFH 80073H 2DH

80014H 9AH 80034H 69H 80054H 13H 80074H 51H

80015H 49H 80035H F6H 80055H B1H 80075H ADH

80016H 5DH 80036H 29H 80056H CCH 80076H 36H

80017H 33H 80037H 5BH 80057H 16H 80077H 69H

80018H CDH 80038H DDH 80058H 26H 80078H 00H

80019H F1H 80039H ACH 80059H 92H 80079H F9H

8001AH 0AH 8003AH 72H 8005AH 7BH 8007AH 1DH

8001BH ABH 8003BH F6H 8005BH BFH 8007BH FEH

8001CH 07H 8003CH 91H 8005CH C7H 8007CH 61H

8001DH 62H 8003DH 20H 8005DH B2H 8007DH A9H

8001EH 19H 8003EH 82H 8005EH 39H 8007EH DEH

8001FH 9EH 8003FH DCH 8005FH BDH 8007FH 4DH


LOGIC INSTRUCTIONS

Logic instructions include the logic operations AND, OR, XOR, and NOT. Also included in this group is

the TEST instruction. The TEST instruction is

somewhat similar to the CMP instruction where the

flags are modified but the operands are not altered.

The AND Instruction

The AND (Logical AND) instruction logically ANDs

the source and the destination operands and stores the

result in the destination operand.

Format: AND D, S

Action: D [D] [S]


register register AND BX, CX

register MM AND DX, [BP + SI]

MM register AND BETA, CX

register immediate AND BX, 0015H

MM immediate AND byte ptr BETA, 12H


Pointers:

1. The AND instruction does not allow both source


(no memory to memory AND). Therefore, the

instruction AND SET, FILE is invalid.


of the same data size. The instruction AND AH,

BX is therefore invalid.


data. Therefore, the instruction AND 1800H, CX

is invalid.

4. CF and OF are always 0 after execution while AF

is undefined.




word ptr should appear after the AND instruction



6. The AND instruction can be used to clear out or

zero out certain bits in a byte or word. In order

to do this, simply logically AND a bit mask

pattern and the byte or word concerned. A bit

mask pattern contains a pattern of 1s and 0s. A 0 in a bit position will cause that bit position to

be zeroed out, while a 1 in a bit position will not

change the value.

Example:

MOV AL, 05H

MOV BL, FEH

AND AL, BL

AL = 0 0 0 0 0 1 0 1

(mask) BL = 1 1 1 1 1 1 1 0

AL = 0 0 0 0 0 1 0 0

bit 0 is zeroed out, the rest of the

bits remain the same.

Flags:

CF, OF, PF, ZF, SF, are all equal to 0.

AF is undefined.


The OR Instruction

The OR (Logical OR) instruction logically ORs the

source and the destination operands and stores the


Format: OR D, S

Action: D [D] + [S]


register register OR BX, CX

register MM OR DX, [BP + SI]

MM register OR BETA, CX

register immediate OR BX, 0015H

MM immediate OR byte ptr BETA, 12H

Pointers:

1. The OR instruction does not allow both source


(no memory to memory OR). OR SET, FILE is

therefore invalid.



OR AH, BX is invalid.


data. Thus, the instruction OR 1800H, CX is

invalid.


is undefined.





word ptr should appear after the OR instruction


6. The OR instruction can be used to set a certain

bit to 1 in a byte or word. In order to do this,

simply logically OR a bit mask pattern and the

byte or word concerned. A bit mask pattern

contains a pattern of 1s and 0s. A 1 in a bit position will cause that bit position to be set to 1,

while a 0 in a bit position will not change the

value.

Example:

MOV CL, 05H

MOV DL, 80H

OR CL, DL

CL = 0 0 0 0 0 1 0 1

(mask) DL = 1 0 0 0 0 0 0 0

CL = 1 0 0 0 0 1 0 1

bit 7 is set to 1, the rest of the bits

remain the same.

Flags:

CF, OF , PF, and ZF are all equal to 0.

SF = 1 while AF is undefined.


The XOR Instruction

The XOR (Logical XOR) instruction logically XORs

the source and the destination operands and stores the


Format: XOR D, S

Action: D [D] [S]


register register XOR BX, CX

register MM XOR DX, [BP + SI]

MM register XOR BETA, CX

register immediate XOR BX, 0015H

MM immediate XOR byte ptr BETA, 12H

Pointers:

1. The XOR instruction does not allow both source


(no memory to memory XOR). XOR SET,

FILE is therefore invalid.


of the same data size. The instruction XOR AH,

BX is invalid.



data. Thus, the instruction XOR 1800H, CX is

invalid.


is undefined.




word ptr should appear after the XOR instruction


6. It is faster for the 8086/8088 to initialize a

register to zero using the XOR instruction rather

than the MOV instruction. Since any value

XORed to itself to zero, XOR AL, AL is faster

to execute than MOV AL, 00H.


The NOT Instruction

The NOT (Logical NOT) instruction performs a 1s complement on the operand.

Format: NOT D

Action: D [D]

Destination Example

register NOT AX

MM NOT byte ptr BETA

Pointers:


data. Thus, the instruction NOT 1800H is

invalid.

2. Flags are not affected.



the NOT instruction to denote the data size of the



The TEST Instruction

The TEST instruction logically ANDs the source and

the destination operands. The result is discarded but

the values of the status flags are updated.

Format: TEST D, S

Action: [D] [S]

Pointers:

1. The TEST instruction does not allow both source


(no memory to memory AND). Therefore, the

instruction TEST SET, FILE is invalid.


of the same data size. The instruction TEST AH,

BX is therefore invalid.


is undefined.




word ptr should appear after the TEST

instruction to denote the data size of the

immediate operand.


SHIFT INSTRUCTIONS

Shift instructions are instructions that also perform bit manipulation.

Shift Instructions can be classified as either logical shift or arithmetic shift.

Shift instructions can also be classified by the direction of the shift (i.e., shift to the left or shift to

the right).

Thus there are four types of shift instructions: shift logical left (SHL), shift logical right (SHR), shift

arithmetic left (SAL), and shift arithmetic right

(SAR).

Logical shifts are used mostly to isolate bits in bytes or words, while arithmetic shifts are used mostly to

multiply and divide binary numbers by powers of two.


The SHL/SAL Instructions

SHL (Shift Logical Left) and SAL (Shift Arithmetic

Left) are two different mnemonics but perform the

same operation. Both instructions shift to the left the

destination operand by the number of bits specified in

the count operand. As bits are shifted, zeroes are

shifted in on the right.

Format: SAL D, Count or SHL D, Count

Action:

Destination Example

register SHL AL, CL

MM SHL byte ptr BETA, CL

register SHL AL, 1

MM SHL byte ptr BETA, 1

CF Operand

0


Pointers:

1. The number of bits to be shifted can be specified

as a constant of 1 (only a constant value of 1 is

allowed) or in register CL. Register CL is used if

more than 1 bit is to be shifted.

2. CF always contains the last bit shifted out of the


3. OF is undefined if more than 1 bit is shifted. If

only 1 bit is shifted, OF is cleared to 0 if the sign

bit retains its original value; otherwise, it is set to

1.

4. AF is undefined after execution.

5. SAL/SHL can be used to multiply by powers of

two (i.e., D * 2CL). For example, if two bits are

shifted to the left, the value of the destination

operand is multiplied by 4 (22).

6. For an 8-bit operand, when shifting it to the

Assembly Language

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