ASPIC Front-end CCD Readout Circuit For LSST camera 1 LPNHE C. Juramy, D. Martin, H. Lebbolo, P. Antilogus, P. Bailly, R. Sefri, S. Bailey LAL C. de La Taille, F. Wicek, J. Jeglot , M. Moniez, V. Tocut Sefri Rachid @LPNHE La Londe-les-Maures october2009
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ASPIC Front-end CCD Readout Circuit For LSST camera
LPNHE C. Juramy, D. Martin, H. Lebbolo, P. Antilogus, P. Bailly, R. Sefri, S. Bailey LAL C. de La Taille, F. Wicek, J. Jeglot , M. Moniez, V. Tocut. ASPIC Front-end CCD Readout Circuit For LSST camera. IN2P3 contribution to camera electronics. IN2P3 contribution: - PowerPoint PPT Presentation
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ASPIC
Front-end CCD Readout Circuit
For LSST camera
1
LPNHE C. Juramy, D. Martin, H. Lebbolo, P. Antilogus, P. Bailly, R. Sefri, S.
Bailey
LAL C. de La Taille, F. Wicek, J. Jeglot , M. Moniez, V. Tocut
Sefri Rachid @LPNHE La Londe-les-Maures october2009
Sefri Rachid @LPNHE La Londe-les-Maures october2009
2
IN2P3 contribution to camera electronics
IN2P3 contribution: Video Signal
Processing
IN2P3 contribution: Video Signal
Processing
SCC
ASPIC
Clock / DSITiming /
Amplitude
18 bitADC’s
Front EndElectronicsCCD Clocks
3 serial 4 parallel 1 reset
16 outputs 500 X 2K
DSI
BackEndElectronics
digitalanalog
BackEnd
ModuleFPGA
(1/Raft)
....
-100°C
TimingControlModule
Scientific Data 21 Rafts
189 CCD’s6GB / Frame
Warm Electronics
-40°C
3
ASPIC: 1rst proto
ASPIC: Analog Signal Processing IC
– 1rst prototype: mid 2007 to mid 2008 2 solutions explored based on ‘Correlated
Double Sampling’
• With integrator : Dual Slope Integrator (DSI)• Without integrator : ‘Clamp & Sample’
4 channels of each on the same silicium substrate to perform crosstalk tests
Sefri Rachid @LPNHE La Londe-les-Maures october2009
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ASPIC: 1rst proto
Sefri Rachid @LPNHE La Londe-les-Maures october2009
6Sefri Rachid @LPNHE La Londe-les-Maures october2009
COLD TESTS
7Sefri Rachid @LPNHE La Londe-les-Maures october2009
Power vs Temperature
8Sefri Rachid @LPNHE La Londe-les-Maures october2009
Offset vs. Temperature
9Sefri Rachid @LPNHE La Londe-les-Maures october2009
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Proto 1 design The first prototype has demonstrated
Comparison between DSI and C&S in same chipDSI principle and multi channel IC feasibility at low temperature with low crosstalk Good fit between simulations and measurementsC&S feasibility
Sefri Rachid @LPNHE La Londe-les-Maures october2009
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ASPIC: 2nd proto
3 input amplifier gains : 2.5 – 5 – 7.5
to deal with CCD gain spread.
3 integration time constants : 500ns – 1µs – 1.5µs
to deal with CCD readout frequency.
Idle mode : DC current reduction by a factor of 1.000
baseline : { gain 5 + 500ns integration time}
Multi Gain
Technologie : AMS CMOS 0.35µ 5V 8 Channel full DSI Package : CQFP100 8 Dual Slope Integrators
Sefri Rachid @LPNHE La Londe-les-Maures october2009
Warm Test Stand
12Sefri Rachid @LPNHE La Londe-les-Maures october2009
Linearity
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dsi_c1 gain 5 It = 500ns T = 193K
dsi_c1 gain 7.5 It = 500ns T = 193K
Sefri Rachid @LPNHE La Londe-les-Maures october2009
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Main Improvement : noise
Noise vs 1/sqrt(Tint) @ -100°C
0
1
2
3
4
5
6
7
8
9
0 0,01 0,02 0,03 0,04 0,05 0,06
1/sqrt(Tint)
µV
R=5k - C=100pf
R=10k - C=100pf
R=15k - C=100pf
Proto 1 - Noise density simulations & Measurements
0
5
10
15
20
25
30
35
40
45
50
0 0,05 0,1 0,15
1/SQRT(Tint)
µV
Noise measurement LPNHE
Noise measurement LAL
Noise simulation
Noise simulations and measurements of ASPIC 119µV RMS noise for a Time of Integration of 500ns
Noise simulations of ASPIC 2 @ -100°C6µV RMS noise for a Time of Integration of 500ns
Sefri Rachid @LPNHE La Londe-les-Maures october2009
Simulation
Integration Time (ns) Input Noise uV
500 9
400 10,6
300 13,2
200 17,61
100 33,5
Crosstalk measurements @ 300K
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The crosstalk of ASPIC02 is about 0,02 and 0,03% (Adjacents channels)
The crosstalk between ch3 and ch5 is about 0,002 % and 0,008%
Sefri Rachid @LPNHE La Londe-les-Maures october2009
ΔV = Crosstalk
Adjacent channel output signal X 10
Signal source -100mV pulse
Signal source -100mV pulse
16
LAL/LPNHE Cryostats
LAL cryostat
dedicated to
prototyping tests
LPNHE cryostat dedicated to
prototyping & pre-prod tests Already cooled down – used for ASPIC1
Sefri Rachid @LPNHE La Londe-les-Maures october2009
CLASSIC
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• 8 channels Clamp & Sample chip • Pin to pin compatible with ASPIC 2• 3 bit programmable gain input
amplifier• 4 bit programmable output time
constant filter to match the readout frequency
• Two differents C&S topologies • Idle mode
Sefri Rachid @LPNHE La Londe-les-Maures october2009
CLASSIC Schematic
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New functionalities / ASPIC1:
Switched-capacitor gainProgrammable input gain amplifierProgrammable time constant filter Two different C&S topologies:
1st : One channel noise : 3.9 µV18mW/channel and < 1% nonliearity
2ndPositive gain channel noise : 2.81 µVNegative gain channel noise : 2.47µV18mW/channel and < 1% nonliearity
DSI vs C&S
• Signal de sortie d’un CCD = signal de faible niveau: chaque photo-électron produira quelques µV.
• Forme du signal complexe – nécessité d’un timing précis
t
V out
res et feedthrough
R eference level
C harge dump
s ignal level
Le traitement de l’image doit se faire en lisant le niveau de référence et le signal
La différence de ces signaux donnera le nombre d’électrons du pixel lu
Technique: Correlated Double Sampling
Etage de sortie d’un CCD
Sefri Rachid @LPNHE La Londe-les-Maures october2009
DSI vs C&S• Dual Slope Integrator
– Suppression automatique du bruit de reset des CCD – Utilisé dans SNAP: A low power, wide dynamic range multigain signal
processor for the SNAP CCD – JP Walder et Al. – NSS Oct 2004.