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ASIC,Customer-Owned
Tooling,and Processor Design
Nancy NettletonManager, VLSI ASIC Device EngineeringApril 2000
Design Style Myths ThatLead EDA Astray
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Design Style Myths
COT is a design style that achieves
higher performance through greaterownership of physical design.
ASICs are slower than processors
because of design margin.Design automation tactics tuned onprocessors are effective on ASICs if
they are more heavily automated.
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Evolution of the ASIC DesignFlow
Synthesis
Floorplan
Placement
Timing Closure
Routing
Late 90s018um-0.25um
Synthesis
Floorplan
Placement
Timing Closure
Routing
Xcap Closure
Today
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Difference Between ASIC &COT
Wafer
Yield
Final Test
Yield
FabPackage/
Assembly/
Test
Tested
PartsPhysical
Design
Logical
DesignNetlist +
Timing
Constraints
GDSII
ASIC SupplierCustomer
Customer Foundry Pkg/Test
ASIC model: ASIC supplier responsible forphysical design, silicon fabrication, &package/assembly/test.
COT model: Customer responsible for physical
design, wafer, and final test yield.
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Meaning of Customer-OwnedTooling Has Changed
Used to mean who owned physical
design, the foundry or the customer.Now it means who is responsible forthe supply chain, regardless of the
design flow used.The term Customer-Owned Tooling
No longer defines a design flow.
Transfer of silicon responsibility from avertically integrated ASIC supplier to thecustomer (with commensurate cost reduction).
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Implications of Yield Ownership
Was the waferprocessed correctly?
Was the design properly
targeted within processdistribution?
Two Types
of Yield
ASICSupplier
ASIC
Supplier
ASIC
Model
Foundry
Customer
COT
Model
Physical design determines target within a process
distribution. Clock
Power
Signal Integrity
Performance Verification
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Yield and Performance
ASICs target full yield at target
performance.Clock rate often defined by system interface
No value in running faster.
Non-functional if slower.Processors typically do not targetfull yield at target performance.
Marketable at many performance points.Added value for higher performance parts, even ifyield is limited.
Can still sell slower parts.
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Microprocessor Design FlowOverview
RTL
Custom
Circuit
Design
CustomLayout
Memory
Design
CustomLayout
Datapath
Mapping
DatapathCompilation
Synthesis
Place
&
Route
Chip
Integration
Reduced Emphasis on Synthd Logic
UltraSparcI/II 20+%
UltrasparcIII 15%
Next Gen Sparc 5%
Most Like ASIC
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Key Differences in Design Content
ASIC Processor
Synthesized Logic
Memory
Datapath
Custom Circuit
Design
Dominated by
synthesized logic
Dominated by custom
circuit design.
Compiled memories
embedded in logic.
Custom memories as
independent blocks.
Heavily partitioned. Lightly partitioned.
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Key MethodologyDifferences
ASIC Processor
DelayCalculation
CircuitSimulation
Timing Sign-off
Synthesized CustomPower & Clock
100s of K gates 10s of K gatesBlock Size
Modeled SimulatedNoise Analysis
Automated ManualTiming Closure
Automated ManualNoise Repair
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Migrating to COTASIC SupplierCustomer
FabPackage/
Assembly/
Test
PhysicalLogical
ASIC
Customer Foundry Pkg/Test
FabPackage/
Assembly/Test
PhysicalLogical
COT
More Custom Tuning?
Not Necessarily. . .
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If Customer Owns
Physical Design, WhyNot Tune It?ASIC content is fundamentally different
than processor content.Volatile system IP is partitioned onto ASICsHighly tuned system interfaces
Definition evolves right up to system power-on.
Rapid silicon implementation is often moreimportant than detailed tuning.
Even if customer owns physical design, the
nature of the system IP may prohibit designtuning.
Then why go COT?$ $ $ $ $ $ $ $ $ $
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Different DesignObjectivesProcessor
System chips
More stable architecture (throughpartitioning)Achieve best possible timing
Less stable architecture (because of
system partitioning)Achieve acceptable timing
on limited
numberof well-understood critical paths.
on largenumberof unknown critical paths.
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ImplicationsProcessors becoming
increasingly unsuitable as provinggrounds for prevalent silicondesign techniques.
Excellent vehicles for circuitdesign and performance-relatedproblems.
Not representative of systemchips
Small, homogeneous synthesized logic blocksHeavily partitioned and tuned
Less automation.
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Conclusion
Customer-Owned Tooling is abusiness model, not a design style.
Ownership of physical design doesnot equate to higher performance.
Performance of system chips is
often defined by IP and schedule,not design techniques.
Heavy partitioning and custom circuit
design make processor designincreasingly less representative ofsystem chip automation.
