Asian Test Symposium 2013 eeprom qualification

Automotive EEPROM qualification and cost

optimization2013 Asian Test Symposium

18-21st Nov 2013

08/17/2012 V16.2

Peter Sarson CEng MIETTest Development Manager

Full Service Foundry

Purpose

• Reduce Test Time of ams AG EEPROM

products

– Reduce loading of Production Testers– Reduce product cost

Outline

• What is an EEPROM?

• Important Specifications

• Test Mode Implementation

• EEPROM quality and lifetime

• Initial Release to Production

• Production Ramp Up Phase

• Cost optimization

• Quality confirmation

What is an EEPROM

• Electrical Erasable Programmable Read Only

Memory

• Non Volatile Memory

• You can reprogram a number of times

Important Specifications

1. Maximum Guaranteed Write Operations –

Endurance loops

2. Write operation Program and Erase voltages

3. Charge contained within each bit cell

Design for Test – Usual Problems

1.No external access to bitcell for current

measure• Cannot guarantee charge density

2.No external access to the source voltage• usually done with the internal bandgap voltage

Test Mode Solutions

1.Current Sense amplifier used to mux bitcells• External current source used • Current difference measurement• Parametric test can be done digitally

2.Direct access to the voltage reference

• Guarantee of voltage seen by bit cell

3.Direct access to bit cell through mux• Measure the exact bit cell current

one addition pin for all functionality

Test Mode Architecture

Fast Bit Screen - Characterisation

Identify bitcells with Program/Erase voltage <

certain value– Over lifetime the Program/Erase voltage will

decrease – Bit cell will become un-writable

THIS IS CRITICAL TO QUALITY

Fast Bits - Characterisation

Program voltage profile

Program voltage ramp

100mV Steps

Bit Cell Current

• Its possible to check every bitcell current– Would take a long time in production– This was used for the initial debug

• One address is parametrically checked in

production– Other bits use sense amp for digital margin test

• The value for 1st address is stored– Use of a database for Lot data– Max/Min current values of all bits stored from

digital margin test

To guarantee 10 year lifetime

• Find marginal fast bit devices on wafer– execute maximum spec write cycles

• Bake for 4000 hours at 250°C– 10 years lifetime guarantee at 150°C.

– All failures seen were triggered at 24hours

• Check data that was written is un-corrupted

We have a reliable EEPROM

and we can prove it!

Extending to Production Test

• Bake– The wafers are baked at 250deg for 24hours

• and 2nd Stage Retest– Bit cell currents measured again– Max/Min current of digital margin test checked

again– Result compared to the pre bake result– Any drift > 1uA and the device is failedTHIS IS CRITICAL TO QUALITY

300 billion bit cells later !!!!!

• 10 million EEPROMS shipped

• Fast bit wafers have been captured

• No RMA received for any EEPROM

• How can we optimise?

– Without compromising quality?

Quality Costs Money

• Current test is characterisation – Voltage

Sweep

• We need a voltage for Erase/Program Test

– that reliably erases/programs all bits – doesn’t impact yield – maintains the quality level

Binflip

Characterisation data• FastBit wafer used with

many marginal parts

• Marginal parts can flip

• We care about Bad to

Good

• What's the repeatability

like?

Repeatability

• Issue due to cutting

the distribution

– to ensure good devices only

One shot Repeatability

How to Prove the fail to pass

• Prove once more these are good devices

• Subject these parts to full endurance cycles

• Bake the wafer for qualification period again

• Check the retention data

Endurance Retention Pre Bake

F 8.000 V 7.800 V 12.200 V Volt1stProgramBit24999.100 - 25000.000 25000.100 EnduranceLoopCnt-0.100 - 0.000 - 0.100 RetentionExtReadmax

Post Bake-0.100 0.000 0.100 RetentionExtReadmax

DATA WAS RETAINED AFTER QUALIFICATION REDO

Conclusion

– 50% Test Time saving• Large increase in quality

– Reconfirmation that the original characterisation was correct

– 0.5-1% decrease in yield

– Huge cost saving