LAB: 1 TITLE: INTRODUCTION TO SCHEMATIC LOGIC DESIGN Learning Outcomes: At the end of the practical, student able to: i. Explain schematic design using CPLD ii. Explain function clocks (wave form) in digital computer. iii. Use schematic CPLD to simulate digital output for SR, D, master slave and JK flip-flop. iv. Design shift register using flip-flop JK. Laboratory Equipment: i. Computer ii. Software Altera Max Plus II
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
LAB: 1
TITLE: INTRODUCTION TO SCHEMATIC LOGIC DESIGN
Learning Outcomes:
At the end of the practical, student able to:
i. Explain schematic design using CPLD
ii. Explain function clocks (wave form) in digital computer.
iii. Use schematic CPLD to simulate digital output for SR, D, master slave and JK flip-flop.
What we can conclude in this practical lab ,we be able to explain the schematic design using CPL. After that ,we be able to explain the function clocks(waveform) in digital computer. Then , we can use the schematic CPLD to stimulate digital output for SR flip-flop,D flip-flop ,Master Slave flip-flop and JK flip-flop . More than that ,we know how to design shift register using flip-flop JK . We learn that a digital system can be represented at different levels of abstraction . This keeps the description and design of complex system manageable.Lastly, we managed to understand that the highest level of abstraction is the behavional level that describes a system in terms of what it does(or how it behaves) rather than in terms of its components and interconnection between them.